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Searched +full:max +full:- +full:clk +full:- +full:rate +full:- +full:hz (Results 1 – 25 of 235) sorted by relevance

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/OK3568_Linux_fs/u-boot/drivers/power/dvfs/
H A Drockchip_wtemp_dvfs.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <clk.h>
21 * 1. U-Boot parse cpu/dmc opp table from kernel dtb, anyone of
22 * "rockchip,low-temp = <...>" and "rockchip,high-temp = <...>" present in
25 * 1.1. When temperature trigger "rockchip,low-temp", increase 50mv voltage
26 * as target voltage. If target voltage is over "rockchip,max-volt",
27 * just set "rockchip,max-volt" as target voltage and lower 2 level freq,
29 * 1.2. When temperature trigger "rockchip,high-temp", just apply opp table[0]
32 * 2. U-Boot parse cpu/dmc thermal zone "trip-point-0" temperature from kernel
38 * 1. Appy it after clk and regulator drivers setup;
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/OK3568_Linux_fs/kernel/include/linux/
H A Dclk.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/include/linux/clk.h
7 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
17 struct clk;
22 * DOC: clk notifier callback types
24 * PRE_RATE_CHANGE - called immediately before the clk rate is changed,
25 * to indicate that the rate change will proceed. Drivers must
27 * rate change. Callbacks may either return NOTIFY_DONE, NOTIFY_OK,
30 * ABORT_RATE_CHANGE: called if the rate change failed for some reason
32 * the clk will be called with ABORT_RATE_CHANGE. Callbacks must
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/msm/edp/
H A Dedp_ctrl.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
6 #include <linux/clk.h>
25 #define EDP_TRAIN_FAIL -1
64 struct clk *aux_clk;
65 struct clk *pixel_clk;
66 struct clk *ahb_clk;
67 struct clk *link_clk;
68 struct clk *mdp_core_clk;
113 u32 rate; /* in kHz */ member
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/iio/adc/
H A Dst,stm32-adc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/iio/adc/st,stm32-adc.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
10 STM32 ADC is a successive approximation analog-to-digital converter.
13 stored in a left-aligned or right-aligned 32-bit data register.
17 voltage goes beyond the user-defined, higher or lower thresholds.
22 - Fabrice Gasnier <fabrice.gasnier@st.com>
27 - st,stm32f4-adc-core
28 - st,stm32h7-adc-core
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/OK3568_Linux_fs/kernel/drivers/pwm/
H A Dpwm-tegra.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * drivers/pwm/pwm-tegra.c
5 * Tegra pulse-width-modulation controller driver
7 * Copyright (c) 2010-2020, NVIDIA Corporation.
8 * Based on arch/arm/plat-mxc/pwm.c by Sascha Hauer <s.hauer@pengutronix.de>
11 * 1. 13-bit: Frequency division (SCALE)
12 * 2. 8-bit : Pulse division (DUTY)
13 * 3. 1-bit : Enable bit
18 * achieved is (max rate of source clock) / 256.
19 * e.g. if source clock rate is 408 MHz, maximum output frequency can be:
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/OK3568_Linux_fs/kernel/drivers/cpufreq/
H A Dimx6q-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk.h>
11 #include <linux/nvmem-consumer.h>
68 old_freq = clk_get_rate(clks[ARM].clk) / 1000; in imx6q_set_target()
81 dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n", in imx6q_set_target()
111 * For i.MX6UL, it has a secondary clk mux, the cpu frequency change in imx6q_set_target()
114 * - Enable pll2_pfd2_396m_clk and reparent pll1_sw_clk to it in imx6q_set_target()
115 * - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it in imx6q_set_target()
116 * - Disable pll2_pfd2_396m_clk in imx6q_set_target()
127 clk_set_rate(clks[ARM].clk, (old_freq >> 1) * 1000); in imx6q_set_target()
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H A Dsh-cpufreq.c4 * Copyright (C) 2002 - 2012 Paul Mundt
7 * Clock framework bits from arch/avr32/mach-at32ap/cpufreq.c
9 * Copyright (C) 2004-2007 Atmel Corporation
27 #include <linux/clk.h>
31 static DEFINE_PER_CPU(struct clk, sh_cpuclk);
46 struct cpufreq_policy *policy = target->policy; in __sh_cpufreq_target()
47 int cpu = policy->cpu; in __sh_cpufreq_target()
48 struct clk *cpuclk = &per_cpu(sh_cpuclk, cpu); in __sh_cpufreq_target()
54 return -ENODEV; in __sh_cpufreq_target()
58 /* Convert target_freq from kHz to Hz */ in __sh_cpufreq_target()
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H A Ds3c24xx-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2006-2008 Simtec Electronics
18 #include <linux/clk.h>
24 #include <linux/soc/samsung/s3c-cpufreq-core.h>
25 #include <linux/soc/samsung/s3c-pm.h>
30 /* note, cpufreq support deals in kHz, no Hz */
39 static struct clk *_clk_mpll;
40 static struct clk *_clk_xtal;
41 static struct clk *clk_fclk;
42 static struct clk *clk_hclk;
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/OK3568_Linux_fs/u-boot/drivers/i2c/
H A Dstm32f7_i2c.c4 * SPDX-License-Identifier: GPL-2.0+
8 #include <clk.h>
131 * struct stm32_i2c_spec - private i2c specification timing
132 * @rate: I2C bus speed (Hz)
133 * @rate_min: 80% of I2C bus speed (Hz)
134 * @rate_max: 120% of I2C bus speed (Hz)
135 * @fall_max: Max fall time of both SDA and SCL signals (ns)
136 * @rise_max: Max rise time of both SDA and SCL signals (ns)
138 * @vddat_max: Max data valid time (ns)
145 u32 rate; member
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/OK3568_Linux_fs/kernel/drivers/opp/
H A Dti-opp-supply.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2017 Texas Instruments Incorporated - https://www.ti.com/
5 * Dave Gerlach <d-gerlach@ti.com>
11 #include <linux/clk.h>
25 * struct ti_opp_supply_optimum_voltage_table - optimized voltage table
35 * struct ti_opp_supply_data - OMAP specific opp supply data
49 * struct ti_opp_supply_of_data - device tree match data
52 * @efuse_voltage_uv: Are the efuse entries in micro-volts? if not, assume
53 * milli-volts.
64 * _store_optimized_voltages() - store optimized voltages
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H A Dcore.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2009-2010 Texas Instruments Incorporated.
13 #include <linux/clk.h>
25 * The root of the list of all opp-tables. All opp_table structures branch off
38 list_for_each_entry(opp_dev, &opp_table->dev_list, node) in _find_opp_dev()
39 if (opp_dev->dev == dev) in _find_opp_dev()
51 mutex_lock(&opp_table->lock); in _find_opp_table_unlocked()
53 mutex_unlock(&opp_table->lock); in _find_opp_table_unlocked()
62 return ERR_PTR(-ENODEV); in _find_opp_table_unlocked()
66 * _find_opp_table() - find opp_table struct using device pointer
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/OK3568_Linux_fs/kernel/drivers/clocksource/
H A Dnomadik-mtu.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2010 Linus Walleij for ST-Ericsson
16 #include <linux/clk.h>
33 /* per-timer registers take 0..3 as argument */
41 #define MTU_CRn_PERIODIC 0x40 /* if 0 = free-running */
66 static u32 nmdk_cycle; /* write-once */
79 return -readl(mtu_base + MTU_VAL(0)); in nomadik_read_sched_clock()
87 /* Clockevent device: use one-shot mode */
103 /* Timer: configure load and background-load, and fire it up */ in nmdk_clkevt_reset()
145 /* ClockSource: configure load and background-load, and fire it up */ in nmdk_clksrc_reset()
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H A Dasm9260_timer.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2014 Oleksij Rempel <linux@rempel-privat.de>
10 #include <linux/clk.h>
19 #define DRIVER_NAME "asm9260-timer"
23 * 0x0 - plain read write mode
24 * 0x4 - set mode, OR logic.
25 * 0x8 - clr mode, XOR logic.
26 * 0xc - togle mode.
48 * 1 - Timer Counter and Prescale Counter are enabled for counting
49 * 0 - counters are disabled */
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/OK3568_Linux_fs/kernel/drivers/firmware/arm_scmi/
H A Dclock.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2018-2020 ARM Ltd.
51 } rate[0]; member
75 struct scmi_clock_info *clk; member
86 ret = ph->xops->xfer_get_init(ph, PROTOCOL_ATTRIBUTES, in scmi_clock_protocol_attributes_get()
91 attr = t->rx.buf; in scmi_clock_protocol_attributes_get()
93 ret = ph->xops->do_xfer(ph, t); in scmi_clock_protocol_attributes_get()
95 ci->num_clocks = le16_to_cpu(attr->num_clocks); in scmi_clock_protocol_attributes_get()
96 ci->max_async_req = attr->max_async_req; in scmi_clock_protocol_attributes_get()
99 ph->xops->xfer_put(ph, t); in scmi_clock_protocol_attributes_get()
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/iio/imu/
H A Dadi,adis16480.txt6 - compatible: Must be one of
12 * "adi,adis16495-1"
13 * "adi,adis16495-2"
14 * "adi,adis16495-3"
15 * "adi,adis16497-1"
16 * "adi,adis16497-2"
17 * "adi,adis16497-3"
18 - reg: SPI chip select number for the device
19 - spi-max-frequency: Max SPI frequency to use
20 see: Documentation/devicetree/bindings/spi/spi-bus.txt
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/OK3568_Linux_fs/kernel/drivers/mmc/host/
H A Dsdhci-s3c.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* linux/drivers/mmc/host/sdhci-s3c.c
14 #include <linux/dma-mapping.h>
16 #include <linux/platform_data/mmc-sdhci-s3c.h>
18 #include <linux/clk.h>
104 * struct sdhci_s3c - S3C SDHCI instance
114 * @no_divider: No or non-standard internal clock divider.
124 struct clk *clk_io;
125 struct clk *clk_bus[MAX_BUS_CLK];
132 * struct sdhci_s3c_driver_data - S3C SDHCI platform specific driver data
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/OK3568_Linux_fs/u-boot/arch/arm/mach-sunxi/
H A Dclock_sun4i.c4 * (C) Copyright 2007-2012
10 * SPDX-License-Identifier: GPL-2.0+
30 &ccm->cpu_ahb_apb0_cfg); in clock_init_safe()
31 writel(PLL1_CFG_DEFAULT, &ccm->pll1_cfg); in clock_init_safe()
37 &ccm->cpu_ahb_apb0_cfg); in clock_init_safe()
39 setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_DMA); in clock_init_safe()
41 writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg); in clock_init_safe()
43 setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_SATA); in clock_init_safe()
44 setbits_le32(&ccm->pll6_cfg, 0x1 << CCM_PLL6_CTRL_SATA_EN_SHIFT); in clock_init_safe()
58 &ccm->apb1_clk_div_cfg); in clock_init_uart()
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/OK3568_Linux_fs/kernel/include/sound/sof/
H A Ddai-intel.h1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
52 /* DMIC max. four controllers for eight microphone channels */
55 /* SSP Configuration Request - SOF_IPC_DAI_SSP_CONFIG */
61 uint32_t mclk_rate; /* mclk frequency in Hz */
62 uint32_t fsync_rate; /* fsync frequency in Hz */
63 uint32_t bclk_rate; /* bclk frequency in Hz */
87 /* HDA Configuration Request - SOF_IPC_DAI_HDA_CONFIG */
91 uint32_t rate; member
95 /* ALH Configuration Request - SOF_IPC_DAI_ALH_CONFIG */
99 uint32_t rate; member
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/OK3568_Linux_fs/kernel/sound/soc/codecs/
H A Drk730.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * rk730.c -- RK730 ALSA SoC Audio driver
16 #include <linux/clk.h>
40 struct clk *mclk;
45 static const DECLARE_TLV_DB_SCALE(adc_dig_tlv, -95625, 375, 0);
47 static const DECLARE_TLV_DB_SCALE(dac_dig_tlv, -95625, 375, 0);
49 static const DECLARE_TLV_DB_SCALE(d2s_tlv, -1800, 300, 0);
51 static const DECLARE_TLV_DB_SCALE(adc_tlv, -1200, 300, 0);
53 static const DECLARE_TLV_DB_SCALE(mux_tlv, -600, 600, 0);
55 static const DECLARE_TLV_DB_SCALE(mix_buf_tlv, -1800, 300, 0);
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H A Dda7219.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * da7219.c - DA7219 ALSA SoC Codec Driver
11 #include <linux/clk.h>
13 #include <linux/clk-provider.h>
26 #include <sound/soc-dapm.h>
33 #include "da7219-aad.h"
41 static const DECLARE_TLV_DB_SCALE(da7219_mic_gain_tlv, -600, 600, 0);
42 static const DECLARE_TLV_DB_SCALE(da7219_mixin_gain_tlv, -450, 150, 0);
43 static const DECLARE_TLV_DB_SCALE(da7219_adc_dig_gain_tlv, -8325, 75, 0);
44 static const DECLARE_TLV_DB_SCALE(da7219_alc_threshold_tlv, -9450, 150, 0);
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/OK3568_Linux_fs/kernel/drivers/input/touchscreen/
H A Dlpc32xx_ts.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * LPC32xx built-in touchscreen driver
12 #include <linux/clk.h>
43 #define LPC32XX_TSC_ADCCON_X_SAMPLE_SIZE(s) ((10 - (s)) << 7)
44 #define LPC32XX_TSC_ADCCON_Y_SAMPLE_SIZE(s) ((10 - (s)) << 4)
57 #define MOD_NAME "ts-lpc32xx"
60 __raw_readl((dev)->tsc_base + (reg))
62 __raw_writel((val), (dev)->tsc_base + (reg))
68 struct clk *clk; member
83 struct input_dev *input = tsc->dev; in lpc32xx_ts_interrupt()
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_core_perf.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
12 #include <linux/clk.h>
21 * enum dpu_perf_mode - performance tuning mode
34 * @_dpu_core_perf_calc_bw() - to calculate BW per crtc
35 * @kms - pointer to the dpu_kms
36 * @crtc - pointer to a crtc
48 pstate = to_dpu_plane_state(plane->state); in _dpu_core_perf_calc_bw()
52 crtc_plane_bw += pstate->plane_fetch_bw; in _dpu_core_perf_calc_bw()
55 bw_factor = kms->catalog->perf.bw_inefficiency_factor; in _dpu_core_perf_calc_bw()
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/OK3568_Linux_fs/kernel/drivers/media/rc/img-ir/
H A Dimg-ir-hw.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2010-2014 Imagination Technologies Ltd.
7 * This ties into the input subsystem using the RC-core. Protocol support is
14 #include <linux/clk.h>
18 #include <media/rc-core.h>
19 #include "img-ir.h"
63 /* functions for preprocessing timings, ensuring max is set */
68 if (range->max < range->min) in img_ir_timing_preprocess()
69 range->max = range->min; in img_ir_timing_preprocess()
72 range->min = (range->min*unit)/1000; in img_ir_timing_preprocess()
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/OK3568_Linux_fs/kernel/include/soc/rockchip/
H A Drockchip_system_monitor.h1 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
28 unsigned int max; /* Maximum frequency in MHz */ member
38 * struct temp_opp_table - System monitor device OPP description structure
39 * @rate: Frequency in hertz
49 unsigned long rate; member
59 * struct monitor_dev_info - structure for a system monitor device
64 * @devp: Device-specific system monitor profile
77 * @low_limit: Limit maximum frequency when low temperature, in Hz
78 * @high_limit: Limit maximum frequency when high temperature, in Hz
84 * in Hz
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/pl111/
H A Dpl111_display.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * (C) COPYRIGHT 2012-2013 ARM Limited. All rights reserved.
7 * Copyright (c) 2006-2008 Intel Corporation
12 #include <linux/clk.h>
15 #include <linux/dma-buf.h>
32 irq_stat = readl(priv->regs + CLCD_PL111_MIS); in pl111_irq()
38 drm_crtc_handle_vblank(&priv->pipe.crtc); in pl111_irq()
44 writel(irq_stat, priv->regs + CLCD_PL111_ICR); in pl111_irq()
53 struct drm_device *drm = pipe->crtc.dev; in pl111_mode_valid()
54 struct pl111_drm_dev_private *priv = drm->dev_private; in pl111_mode_valid()
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