1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * da7219.c - DA7219 ALSA SoC Codec Driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (c) 2015 Dialog Semiconductor
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Author: Adam Thomson <Adam.Thomson.Opensource@diasemi.com>
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/acpi.h>
11*4882a593Smuzhiyun #include <linux/clk.h>
12*4882a593Smuzhiyun #include <linux/clkdev.h>
13*4882a593Smuzhiyun #include <linux/clk-provider.h>
14*4882a593Smuzhiyun #include <linux/i2c.h>
15*4882a593Smuzhiyun #include <linux/of_device.h>
16*4882a593Smuzhiyun #include <linux/property.h>
17*4882a593Smuzhiyun #include <linux/regmap.h>
18*4882a593Smuzhiyun #include <linux/slab.h>
19*4882a593Smuzhiyun #include <linux/pm.h>
20*4882a593Smuzhiyun #include <linux/module.h>
21*4882a593Smuzhiyun #include <linux/delay.h>
22*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
23*4882a593Smuzhiyun #include <sound/pcm.h>
24*4882a593Smuzhiyun #include <sound/pcm_params.h>
25*4882a593Smuzhiyun #include <sound/soc.h>
26*4882a593Smuzhiyun #include <sound/soc-dapm.h>
27*4882a593Smuzhiyun #include <sound/initval.h>
28*4882a593Smuzhiyun #include <sound/tlv.h>
29*4882a593Smuzhiyun #include <asm/div64.h>
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun #include <sound/da7219.h>
32*4882a593Smuzhiyun #include "da7219.h"
33*4882a593Smuzhiyun #include "da7219-aad.h"
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun /*
37*4882a593Smuzhiyun * TLVs and Enums
38*4882a593Smuzhiyun */
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun /* Input TLVs */
41*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(da7219_mic_gain_tlv, -600, 600, 0);
42*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(da7219_mixin_gain_tlv, -450, 150, 0);
43*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(da7219_adc_dig_gain_tlv, -8325, 75, 0);
44*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(da7219_alc_threshold_tlv, -9450, 150, 0);
45*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(da7219_alc_gain_tlv, 0, 600, 0);
46*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(da7219_alc_ana_gain_tlv, 0, 600, 0);
47*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(da7219_sidetone_gain_tlv, -4200, 300, 0);
48*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(da7219_tonegen_gain_tlv, -4500, 300, 0);
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun /* Output TLVs */
51*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(da7219_dac_eq_band_tlv, -1050, 150, 0);
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun static const DECLARE_TLV_DB_RANGE(da7219_dac_dig_gain_tlv,
54*4882a593Smuzhiyun 0x0, 0x07, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 1),
55*4882a593Smuzhiyun /* -77.25dB to 12dB */
56*4882a593Smuzhiyun 0x08, 0x7f, TLV_DB_SCALE_ITEM(-7725, 75, 0)
57*4882a593Smuzhiyun );
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(da7219_dac_ng_threshold_tlv, -10200, 600, 0);
60*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(da7219_hp_gain_tlv, -5700, 100, 0);
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun /* Input Enums */
63*4882a593Smuzhiyun static const char * const da7219_alc_attack_rate_txt[] = {
64*4882a593Smuzhiyun "7.33/fs", "14.66/fs", "29.32/fs", "58.64/fs", "117.3/fs", "234.6/fs",
65*4882a593Smuzhiyun "469.1/fs", "938.2/fs", "1876/fs", "3753/fs", "7506/fs", "15012/fs",
66*4882a593Smuzhiyun "30024/fs"
67*4882a593Smuzhiyun };
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun static const struct soc_enum da7219_alc_attack_rate =
70*4882a593Smuzhiyun SOC_ENUM_SINGLE(DA7219_ALC_CTRL2, DA7219_ALC_ATTACK_SHIFT,
71*4882a593Smuzhiyun DA7219_ALC_ATTACK_MAX, da7219_alc_attack_rate_txt);
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun static const char * const da7219_alc_release_rate_txt[] = {
74*4882a593Smuzhiyun "28.66/fs", "57.33/fs", "114.6/fs", "229.3/fs", "458.6/fs", "917.1/fs",
75*4882a593Smuzhiyun "1834/fs", "3668/fs", "7337/fs", "14674/fs", "29348/fs"
76*4882a593Smuzhiyun };
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun static const struct soc_enum da7219_alc_release_rate =
79*4882a593Smuzhiyun SOC_ENUM_SINGLE(DA7219_ALC_CTRL2, DA7219_ALC_RELEASE_SHIFT,
80*4882a593Smuzhiyun DA7219_ALC_RELEASE_MAX, da7219_alc_release_rate_txt);
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun static const char * const da7219_alc_hold_time_txt[] = {
83*4882a593Smuzhiyun "62/fs", "124/fs", "248/fs", "496/fs", "992/fs", "1984/fs", "3968/fs",
84*4882a593Smuzhiyun "7936/fs", "15872/fs", "31744/fs", "63488/fs", "126976/fs",
85*4882a593Smuzhiyun "253952/fs", "507904/fs", "1015808/fs", "2031616/fs"
86*4882a593Smuzhiyun };
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun static const struct soc_enum da7219_alc_hold_time =
89*4882a593Smuzhiyun SOC_ENUM_SINGLE(DA7219_ALC_CTRL3, DA7219_ALC_HOLD_SHIFT,
90*4882a593Smuzhiyun DA7219_ALC_HOLD_MAX, da7219_alc_hold_time_txt);
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun static const char * const da7219_alc_env_rate_txt[] = {
93*4882a593Smuzhiyun "1/4", "1/16", "1/256", "1/65536"
94*4882a593Smuzhiyun };
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun static const struct soc_enum da7219_alc_env_attack_rate =
97*4882a593Smuzhiyun SOC_ENUM_SINGLE(DA7219_ALC_CTRL3, DA7219_ALC_INTEG_ATTACK_SHIFT,
98*4882a593Smuzhiyun DA7219_ALC_INTEG_MAX, da7219_alc_env_rate_txt);
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun static const struct soc_enum da7219_alc_env_release_rate =
101*4882a593Smuzhiyun SOC_ENUM_SINGLE(DA7219_ALC_CTRL3, DA7219_ALC_INTEG_RELEASE_SHIFT,
102*4882a593Smuzhiyun DA7219_ALC_INTEG_MAX, da7219_alc_env_rate_txt);
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun static const char * const da7219_alc_anticlip_step_txt[] = {
105*4882a593Smuzhiyun "0.034dB/fs", "0.068dB/fs", "0.136dB/fs", "0.272dB/fs"
106*4882a593Smuzhiyun };
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun static const struct soc_enum da7219_alc_anticlip_step =
109*4882a593Smuzhiyun SOC_ENUM_SINGLE(DA7219_ALC_ANTICLIP_CTRL,
110*4882a593Smuzhiyun DA7219_ALC_ANTICLIP_STEP_SHIFT,
111*4882a593Smuzhiyun DA7219_ALC_ANTICLIP_STEP_MAX,
112*4882a593Smuzhiyun da7219_alc_anticlip_step_txt);
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun /* Input/Output Enums */
115*4882a593Smuzhiyun static const char * const da7219_gain_ramp_rate_txt[] = {
116*4882a593Smuzhiyun "Nominal Rate * 8", "Nominal Rate", "Nominal Rate / 8",
117*4882a593Smuzhiyun "Nominal Rate / 16"
118*4882a593Smuzhiyun };
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun static const struct soc_enum da7219_gain_ramp_rate =
121*4882a593Smuzhiyun SOC_ENUM_SINGLE(DA7219_GAIN_RAMP_CTRL, DA7219_GAIN_RAMP_RATE_SHIFT,
122*4882a593Smuzhiyun DA7219_GAIN_RAMP_RATE_MAX, da7219_gain_ramp_rate_txt);
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun static const char * const da7219_hpf_mode_txt[] = {
125*4882a593Smuzhiyun "Disabled", "Audio", "Voice"
126*4882a593Smuzhiyun };
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun static const unsigned int da7219_hpf_mode_val[] = {
129*4882a593Smuzhiyun DA7219_HPF_DISABLED, DA7219_HPF_AUDIO_EN, DA7219_HPF_VOICE_EN,
130*4882a593Smuzhiyun };
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun static const struct soc_enum da7219_adc_hpf_mode =
133*4882a593Smuzhiyun SOC_VALUE_ENUM_SINGLE(DA7219_ADC_FILTERS1, DA7219_HPF_MODE_SHIFT,
134*4882a593Smuzhiyun DA7219_HPF_MODE_MASK, DA7219_HPF_MODE_MAX,
135*4882a593Smuzhiyun da7219_hpf_mode_txt, da7219_hpf_mode_val);
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun static const struct soc_enum da7219_dac_hpf_mode =
138*4882a593Smuzhiyun SOC_VALUE_ENUM_SINGLE(DA7219_DAC_FILTERS1, DA7219_HPF_MODE_SHIFT,
139*4882a593Smuzhiyun DA7219_HPF_MODE_MASK, DA7219_HPF_MODE_MAX,
140*4882a593Smuzhiyun da7219_hpf_mode_txt, da7219_hpf_mode_val);
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun static const char * const da7219_audio_hpf_corner_txt[] = {
143*4882a593Smuzhiyun "2Hz", "4Hz", "8Hz", "16Hz"
144*4882a593Smuzhiyun };
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun static const struct soc_enum da7219_adc_audio_hpf_corner =
147*4882a593Smuzhiyun SOC_ENUM_SINGLE(DA7219_ADC_FILTERS1,
148*4882a593Smuzhiyun DA7219_ADC_AUDIO_HPF_CORNER_SHIFT,
149*4882a593Smuzhiyun DA7219_AUDIO_HPF_CORNER_MAX,
150*4882a593Smuzhiyun da7219_audio_hpf_corner_txt);
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun static const struct soc_enum da7219_dac_audio_hpf_corner =
153*4882a593Smuzhiyun SOC_ENUM_SINGLE(DA7219_DAC_FILTERS1,
154*4882a593Smuzhiyun DA7219_DAC_AUDIO_HPF_CORNER_SHIFT,
155*4882a593Smuzhiyun DA7219_AUDIO_HPF_CORNER_MAX,
156*4882a593Smuzhiyun da7219_audio_hpf_corner_txt);
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun static const char * const da7219_voice_hpf_corner_txt[] = {
159*4882a593Smuzhiyun "2.5Hz", "25Hz", "50Hz", "100Hz", "150Hz", "200Hz", "300Hz", "400Hz"
160*4882a593Smuzhiyun };
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun static const struct soc_enum da7219_adc_voice_hpf_corner =
163*4882a593Smuzhiyun SOC_ENUM_SINGLE(DA7219_ADC_FILTERS1,
164*4882a593Smuzhiyun DA7219_ADC_VOICE_HPF_CORNER_SHIFT,
165*4882a593Smuzhiyun DA7219_VOICE_HPF_CORNER_MAX,
166*4882a593Smuzhiyun da7219_voice_hpf_corner_txt);
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun static const struct soc_enum da7219_dac_voice_hpf_corner =
169*4882a593Smuzhiyun SOC_ENUM_SINGLE(DA7219_DAC_FILTERS1,
170*4882a593Smuzhiyun DA7219_DAC_VOICE_HPF_CORNER_SHIFT,
171*4882a593Smuzhiyun DA7219_VOICE_HPF_CORNER_MAX,
172*4882a593Smuzhiyun da7219_voice_hpf_corner_txt);
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun static const char * const da7219_tonegen_dtmf_key_txt[] = {
175*4882a593Smuzhiyun "0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "A", "B", "C", "D",
176*4882a593Smuzhiyun "*", "#"
177*4882a593Smuzhiyun };
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun static const struct soc_enum da7219_tonegen_dtmf_key =
180*4882a593Smuzhiyun SOC_ENUM_SINGLE(DA7219_TONE_GEN_CFG1, DA7219_DTMF_REG_SHIFT,
181*4882a593Smuzhiyun DA7219_DTMF_REG_MAX, da7219_tonegen_dtmf_key_txt);
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun static const char * const da7219_tonegen_swg_sel_txt[] = {
184*4882a593Smuzhiyun "Sum", "SWG1", "SWG2", "SWG1_1-Cos"
185*4882a593Smuzhiyun };
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun static const struct soc_enum da7219_tonegen_swg_sel =
188*4882a593Smuzhiyun SOC_ENUM_SINGLE(DA7219_TONE_GEN_CFG2, DA7219_SWG_SEL_SHIFT,
189*4882a593Smuzhiyun DA7219_SWG_SEL_MAX, da7219_tonegen_swg_sel_txt);
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun /* Output Enums */
192*4882a593Smuzhiyun static const char * const da7219_dac_softmute_rate_txt[] = {
193*4882a593Smuzhiyun "1 Sample", "2 Samples", "4 Samples", "8 Samples", "16 Samples",
194*4882a593Smuzhiyun "32 Samples", "64 Samples"
195*4882a593Smuzhiyun };
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun static const struct soc_enum da7219_dac_softmute_rate =
198*4882a593Smuzhiyun SOC_ENUM_SINGLE(DA7219_DAC_FILTERS5, DA7219_DAC_SOFTMUTE_RATE_SHIFT,
199*4882a593Smuzhiyun DA7219_DAC_SOFTMUTE_RATE_MAX,
200*4882a593Smuzhiyun da7219_dac_softmute_rate_txt);
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun static const char * const da7219_dac_ng_setup_time_txt[] = {
203*4882a593Smuzhiyun "256 Samples", "512 Samples", "1024 Samples", "2048 Samples"
204*4882a593Smuzhiyun };
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun static const struct soc_enum da7219_dac_ng_setup_time =
207*4882a593Smuzhiyun SOC_ENUM_SINGLE(DA7219_DAC_NG_SETUP_TIME,
208*4882a593Smuzhiyun DA7219_DAC_NG_SETUP_TIME_SHIFT,
209*4882a593Smuzhiyun DA7219_DAC_NG_SETUP_TIME_MAX,
210*4882a593Smuzhiyun da7219_dac_ng_setup_time_txt);
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun static const char * const da7219_dac_ng_rampup_txt[] = {
213*4882a593Smuzhiyun "0.22ms/dB", "0.0138ms/dB"
214*4882a593Smuzhiyun };
215*4882a593Smuzhiyun
216*4882a593Smuzhiyun static const struct soc_enum da7219_dac_ng_rampup_rate =
217*4882a593Smuzhiyun SOC_ENUM_SINGLE(DA7219_DAC_NG_SETUP_TIME,
218*4882a593Smuzhiyun DA7219_DAC_NG_RAMPUP_RATE_SHIFT,
219*4882a593Smuzhiyun DA7219_DAC_NG_RAMP_RATE_MAX,
220*4882a593Smuzhiyun da7219_dac_ng_rampup_txt);
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun static const char * const da7219_dac_ng_rampdown_txt[] = {
223*4882a593Smuzhiyun "0.88ms/dB", "14.08ms/dB"
224*4882a593Smuzhiyun };
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun static const struct soc_enum da7219_dac_ng_rampdown_rate =
227*4882a593Smuzhiyun SOC_ENUM_SINGLE(DA7219_DAC_NG_SETUP_TIME,
228*4882a593Smuzhiyun DA7219_DAC_NG_RAMPDN_RATE_SHIFT,
229*4882a593Smuzhiyun DA7219_DAC_NG_RAMP_RATE_MAX,
230*4882a593Smuzhiyun da7219_dac_ng_rampdown_txt);
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun static const char * const da7219_cp_track_mode_txt[] = {
234*4882a593Smuzhiyun "Largest Volume", "DAC Volume", "Signal Magnitude"
235*4882a593Smuzhiyun };
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun static const unsigned int da7219_cp_track_mode_val[] = {
238*4882a593Smuzhiyun DA7219_CP_MCHANGE_LARGEST_VOL, DA7219_CP_MCHANGE_DAC_VOL,
239*4882a593Smuzhiyun DA7219_CP_MCHANGE_SIG_MAG
240*4882a593Smuzhiyun };
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun static const struct soc_enum da7219_cp_track_mode =
243*4882a593Smuzhiyun SOC_VALUE_ENUM_SINGLE(DA7219_CP_CTRL, DA7219_CP_MCHANGE_SHIFT,
244*4882a593Smuzhiyun DA7219_CP_MCHANGE_REL_MASK, DA7219_CP_MCHANGE_MAX,
245*4882a593Smuzhiyun da7219_cp_track_mode_txt,
246*4882a593Smuzhiyun da7219_cp_track_mode_val);
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun /*
250*4882a593Smuzhiyun * Control Functions
251*4882a593Smuzhiyun */
252*4882a593Smuzhiyun
253*4882a593Smuzhiyun /* Locked Kcontrol calls */
da7219_volsw_locked_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)254*4882a593Smuzhiyun static int da7219_volsw_locked_get(struct snd_kcontrol *kcontrol,
255*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
256*4882a593Smuzhiyun {
257*4882a593Smuzhiyun struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
258*4882a593Smuzhiyun struct da7219_priv *da7219 = snd_soc_component_get_drvdata(component);
259*4882a593Smuzhiyun int ret;
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun mutex_lock(&da7219->ctrl_lock);
262*4882a593Smuzhiyun ret = snd_soc_get_volsw(kcontrol, ucontrol);
263*4882a593Smuzhiyun mutex_unlock(&da7219->ctrl_lock);
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun return ret;
266*4882a593Smuzhiyun }
267*4882a593Smuzhiyun
da7219_volsw_locked_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)268*4882a593Smuzhiyun static int da7219_volsw_locked_put(struct snd_kcontrol *kcontrol,
269*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
270*4882a593Smuzhiyun {
271*4882a593Smuzhiyun struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
272*4882a593Smuzhiyun struct da7219_priv *da7219 = snd_soc_component_get_drvdata(component);
273*4882a593Smuzhiyun int ret;
274*4882a593Smuzhiyun
275*4882a593Smuzhiyun mutex_lock(&da7219->ctrl_lock);
276*4882a593Smuzhiyun ret = snd_soc_put_volsw(kcontrol, ucontrol);
277*4882a593Smuzhiyun mutex_unlock(&da7219->ctrl_lock);
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun return ret;
280*4882a593Smuzhiyun }
281*4882a593Smuzhiyun
da7219_enum_locked_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)282*4882a593Smuzhiyun static int da7219_enum_locked_get(struct snd_kcontrol *kcontrol,
283*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
284*4882a593Smuzhiyun {
285*4882a593Smuzhiyun struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
286*4882a593Smuzhiyun struct da7219_priv *da7219 = snd_soc_component_get_drvdata(component);
287*4882a593Smuzhiyun int ret;
288*4882a593Smuzhiyun
289*4882a593Smuzhiyun mutex_lock(&da7219->ctrl_lock);
290*4882a593Smuzhiyun ret = snd_soc_get_enum_double(kcontrol, ucontrol);
291*4882a593Smuzhiyun mutex_unlock(&da7219->ctrl_lock);
292*4882a593Smuzhiyun
293*4882a593Smuzhiyun return ret;
294*4882a593Smuzhiyun }
295*4882a593Smuzhiyun
da7219_enum_locked_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)296*4882a593Smuzhiyun static int da7219_enum_locked_put(struct snd_kcontrol *kcontrol,
297*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
298*4882a593Smuzhiyun {
299*4882a593Smuzhiyun struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
300*4882a593Smuzhiyun struct da7219_priv *da7219 = snd_soc_component_get_drvdata(component);
301*4882a593Smuzhiyun int ret;
302*4882a593Smuzhiyun
303*4882a593Smuzhiyun mutex_lock(&da7219->ctrl_lock);
304*4882a593Smuzhiyun ret = snd_soc_put_enum_double(kcontrol, ucontrol);
305*4882a593Smuzhiyun mutex_unlock(&da7219->ctrl_lock);
306*4882a593Smuzhiyun
307*4882a593Smuzhiyun return ret;
308*4882a593Smuzhiyun }
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun /* ALC */
da7219_alc_calib(struct snd_soc_component * component)311*4882a593Smuzhiyun static void da7219_alc_calib(struct snd_soc_component *component)
312*4882a593Smuzhiyun {
313*4882a593Smuzhiyun u8 mic_ctrl, mixin_ctrl, adc_ctrl, calib_ctrl;
314*4882a593Smuzhiyun
315*4882a593Smuzhiyun /* Save current state of mic control register */
316*4882a593Smuzhiyun mic_ctrl = snd_soc_component_read(component, DA7219_MIC_1_CTRL);
317*4882a593Smuzhiyun
318*4882a593Smuzhiyun /* Save current state of input mixer control register */
319*4882a593Smuzhiyun mixin_ctrl = snd_soc_component_read(component, DA7219_MIXIN_L_CTRL);
320*4882a593Smuzhiyun
321*4882a593Smuzhiyun /* Save current state of input ADC control register */
322*4882a593Smuzhiyun adc_ctrl = snd_soc_component_read(component, DA7219_ADC_L_CTRL);
323*4882a593Smuzhiyun
324*4882a593Smuzhiyun /* Enable then Mute MIC PGAs */
325*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7219_MIC_1_CTRL, DA7219_MIC_1_AMP_EN_MASK,
326*4882a593Smuzhiyun DA7219_MIC_1_AMP_EN_MASK);
327*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7219_MIC_1_CTRL,
328*4882a593Smuzhiyun DA7219_MIC_1_AMP_MUTE_EN_MASK,
329*4882a593Smuzhiyun DA7219_MIC_1_AMP_MUTE_EN_MASK);
330*4882a593Smuzhiyun
331*4882a593Smuzhiyun /* Enable input mixers unmuted */
332*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7219_MIXIN_L_CTRL,
333*4882a593Smuzhiyun DA7219_MIXIN_L_AMP_EN_MASK |
334*4882a593Smuzhiyun DA7219_MIXIN_L_AMP_MUTE_EN_MASK,
335*4882a593Smuzhiyun DA7219_MIXIN_L_AMP_EN_MASK);
336*4882a593Smuzhiyun
337*4882a593Smuzhiyun /* Enable input filters unmuted */
338*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7219_ADC_L_CTRL,
339*4882a593Smuzhiyun DA7219_ADC_L_MUTE_EN_MASK | DA7219_ADC_L_EN_MASK,
340*4882a593Smuzhiyun DA7219_ADC_L_EN_MASK);
341*4882a593Smuzhiyun
342*4882a593Smuzhiyun /* Perform auto calibration */
343*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7219_ALC_CTRL1,
344*4882a593Smuzhiyun DA7219_ALC_AUTO_CALIB_EN_MASK,
345*4882a593Smuzhiyun DA7219_ALC_AUTO_CALIB_EN_MASK);
346*4882a593Smuzhiyun do {
347*4882a593Smuzhiyun calib_ctrl = snd_soc_component_read(component, DA7219_ALC_CTRL1);
348*4882a593Smuzhiyun } while (calib_ctrl & DA7219_ALC_AUTO_CALIB_EN_MASK);
349*4882a593Smuzhiyun
350*4882a593Smuzhiyun /* If auto calibration fails, disable DC offset, hybrid ALC */
351*4882a593Smuzhiyun if (calib_ctrl & DA7219_ALC_CALIB_OVERFLOW_MASK) {
352*4882a593Smuzhiyun dev_warn(component->dev,
353*4882a593Smuzhiyun "ALC auto calibration failed with overflow\n");
354*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7219_ALC_CTRL1,
355*4882a593Smuzhiyun DA7219_ALC_OFFSET_EN_MASK |
356*4882a593Smuzhiyun DA7219_ALC_SYNC_MODE_MASK, 0);
357*4882a593Smuzhiyun } else {
358*4882a593Smuzhiyun /* Enable DC offset cancellation, hybrid mode */
359*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7219_ALC_CTRL1,
360*4882a593Smuzhiyun DA7219_ALC_OFFSET_EN_MASK |
361*4882a593Smuzhiyun DA7219_ALC_SYNC_MODE_MASK,
362*4882a593Smuzhiyun DA7219_ALC_OFFSET_EN_MASK |
363*4882a593Smuzhiyun DA7219_ALC_SYNC_MODE_MASK);
364*4882a593Smuzhiyun }
365*4882a593Smuzhiyun
366*4882a593Smuzhiyun /* Restore input filter control register to original state */
367*4882a593Smuzhiyun snd_soc_component_write(component, DA7219_ADC_L_CTRL, adc_ctrl);
368*4882a593Smuzhiyun
369*4882a593Smuzhiyun /* Restore input mixer control registers to original state */
370*4882a593Smuzhiyun snd_soc_component_write(component, DA7219_MIXIN_L_CTRL, mixin_ctrl);
371*4882a593Smuzhiyun
372*4882a593Smuzhiyun /* Restore MIC control registers to original states */
373*4882a593Smuzhiyun snd_soc_component_write(component, DA7219_MIC_1_CTRL, mic_ctrl);
374*4882a593Smuzhiyun }
375*4882a593Smuzhiyun
da7219_mixin_gain_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)376*4882a593Smuzhiyun static int da7219_mixin_gain_put(struct snd_kcontrol *kcontrol,
377*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
378*4882a593Smuzhiyun {
379*4882a593Smuzhiyun struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
380*4882a593Smuzhiyun struct da7219_priv *da7219 = snd_soc_component_get_drvdata(component);
381*4882a593Smuzhiyun int ret;
382*4882a593Smuzhiyun
383*4882a593Smuzhiyun ret = snd_soc_put_volsw(kcontrol, ucontrol);
384*4882a593Smuzhiyun
385*4882a593Smuzhiyun /*
386*4882a593Smuzhiyun * If ALC in operation and value of control has been updated,
387*4882a593Smuzhiyun * make sure calibrated offsets are updated.
388*4882a593Smuzhiyun */
389*4882a593Smuzhiyun if ((ret == 1) && (da7219->alc_en))
390*4882a593Smuzhiyun da7219_alc_calib(component);
391*4882a593Smuzhiyun
392*4882a593Smuzhiyun return ret;
393*4882a593Smuzhiyun }
394*4882a593Smuzhiyun
da7219_alc_sw_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)395*4882a593Smuzhiyun static int da7219_alc_sw_put(struct snd_kcontrol *kcontrol,
396*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
397*4882a593Smuzhiyun {
398*4882a593Smuzhiyun struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
399*4882a593Smuzhiyun struct da7219_priv *da7219 = snd_soc_component_get_drvdata(component);
400*4882a593Smuzhiyun
401*4882a593Smuzhiyun
402*4882a593Smuzhiyun /* Force ALC offset calibration if enabling ALC */
403*4882a593Smuzhiyun if ((ucontrol->value.integer.value[0]) && (!da7219->alc_en)) {
404*4882a593Smuzhiyun da7219_alc_calib(component);
405*4882a593Smuzhiyun da7219->alc_en = true;
406*4882a593Smuzhiyun } else {
407*4882a593Smuzhiyun da7219->alc_en = false;
408*4882a593Smuzhiyun }
409*4882a593Smuzhiyun
410*4882a593Smuzhiyun return snd_soc_put_volsw(kcontrol, ucontrol);
411*4882a593Smuzhiyun }
412*4882a593Smuzhiyun
413*4882a593Smuzhiyun /* ToneGen */
da7219_tonegen_freq_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)414*4882a593Smuzhiyun static int da7219_tonegen_freq_get(struct snd_kcontrol *kcontrol,
415*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
416*4882a593Smuzhiyun {
417*4882a593Smuzhiyun struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
418*4882a593Smuzhiyun struct da7219_priv *da7219 = snd_soc_component_get_drvdata(component);
419*4882a593Smuzhiyun struct soc_mixer_control *mixer_ctrl =
420*4882a593Smuzhiyun (struct soc_mixer_control *) kcontrol->private_value;
421*4882a593Smuzhiyun unsigned int reg = mixer_ctrl->reg;
422*4882a593Smuzhiyun __le16 val;
423*4882a593Smuzhiyun int ret;
424*4882a593Smuzhiyun
425*4882a593Smuzhiyun mutex_lock(&da7219->ctrl_lock);
426*4882a593Smuzhiyun ret = regmap_raw_read(da7219->regmap, reg, &val, sizeof(val));
427*4882a593Smuzhiyun mutex_unlock(&da7219->ctrl_lock);
428*4882a593Smuzhiyun
429*4882a593Smuzhiyun if (ret)
430*4882a593Smuzhiyun return ret;
431*4882a593Smuzhiyun
432*4882a593Smuzhiyun /*
433*4882a593Smuzhiyun * Frequency value spans two 8-bit registers, lower then upper byte.
434*4882a593Smuzhiyun * Therefore we need to convert to host endianness here.
435*4882a593Smuzhiyun */
436*4882a593Smuzhiyun ucontrol->value.integer.value[0] = le16_to_cpu(val);
437*4882a593Smuzhiyun
438*4882a593Smuzhiyun return 0;
439*4882a593Smuzhiyun }
440*4882a593Smuzhiyun
da7219_tonegen_freq_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)441*4882a593Smuzhiyun static int da7219_tonegen_freq_put(struct snd_kcontrol *kcontrol,
442*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
443*4882a593Smuzhiyun {
444*4882a593Smuzhiyun struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
445*4882a593Smuzhiyun struct da7219_priv *da7219 = snd_soc_component_get_drvdata(component);
446*4882a593Smuzhiyun struct soc_mixer_control *mixer_ctrl =
447*4882a593Smuzhiyun (struct soc_mixer_control *) kcontrol->private_value;
448*4882a593Smuzhiyun unsigned int reg = mixer_ctrl->reg;
449*4882a593Smuzhiyun __le16 val_new, val_old;
450*4882a593Smuzhiyun int ret;
451*4882a593Smuzhiyun
452*4882a593Smuzhiyun /*
453*4882a593Smuzhiyun * Frequency value spans two 8-bit registers, lower then upper byte.
454*4882a593Smuzhiyun * Therefore we need to convert to little endian here to align with
455*4882a593Smuzhiyun * HW registers.
456*4882a593Smuzhiyun */
457*4882a593Smuzhiyun val_new = cpu_to_le16(ucontrol->value.integer.value[0]);
458*4882a593Smuzhiyun
459*4882a593Smuzhiyun mutex_lock(&da7219->ctrl_lock);
460*4882a593Smuzhiyun ret = regmap_raw_read(da7219->regmap, reg, &val_old, sizeof(val_old));
461*4882a593Smuzhiyun if (ret == 0 && (val_old != val_new))
462*4882a593Smuzhiyun ret = regmap_raw_write(da7219->regmap, reg,
463*4882a593Smuzhiyun &val_new, sizeof(val_new));
464*4882a593Smuzhiyun mutex_unlock(&da7219->ctrl_lock);
465*4882a593Smuzhiyun
466*4882a593Smuzhiyun if (ret < 0)
467*4882a593Smuzhiyun return ret;
468*4882a593Smuzhiyun
469*4882a593Smuzhiyun return val_old != val_new;
470*4882a593Smuzhiyun }
471*4882a593Smuzhiyun
472*4882a593Smuzhiyun
473*4882a593Smuzhiyun /*
474*4882a593Smuzhiyun * KControls
475*4882a593Smuzhiyun */
476*4882a593Smuzhiyun
477*4882a593Smuzhiyun static const struct snd_kcontrol_new da7219_snd_controls[] = {
478*4882a593Smuzhiyun /* Mics */
479*4882a593Smuzhiyun SOC_SINGLE_TLV("Mic Volume", DA7219_MIC_1_GAIN,
480*4882a593Smuzhiyun DA7219_MIC_1_AMP_GAIN_SHIFT, DA7219_MIC_1_AMP_GAIN_MAX,
481*4882a593Smuzhiyun DA7219_NO_INVERT, da7219_mic_gain_tlv),
482*4882a593Smuzhiyun SOC_SINGLE("Mic Switch", DA7219_MIC_1_CTRL,
483*4882a593Smuzhiyun DA7219_MIC_1_AMP_MUTE_EN_SHIFT, DA7219_SWITCH_EN_MAX,
484*4882a593Smuzhiyun DA7219_INVERT),
485*4882a593Smuzhiyun
486*4882a593Smuzhiyun /* Mixer Input */
487*4882a593Smuzhiyun SOC_SINGLE_EXT_TLV("Mixin Volume", DA7219_MIXIN_L_GAIN,
488*4882a593Smuzhiyun DA7219_MIXIN_L_AMP_GAIN_SHIFT,
489*4882a593Smuzhiyun DA7219_MIXIN_L_AMP_GAIN_MAX, DA7219_NO_INVERT,
490*4882a593Smuzhiyun snd_soc_get_volsw, da7219_mixin_gain_put,
491*4882a593Smuzhiyun da7219_mixin_gain_tlv),
492*4882a593Smuzhiyun SOC_SINGLE("Mixin Switch", DA7219_MIXIN_L_CTRL,
493*4882a593Smuzhiyun DA7219_MIXIN_L_AMP_MUTE_EN_SHIFT, DA7219_SWITCH_EN_MAX,
494*4882a593Smuzhiyun DA7219_INVERT),
495*4882a593Smuzhiyun SOC_SINGLE("Mixin Gain Ramp Switch", DA7219_MIXIN_L_CTRL,
496*4882a593Smuzhiyun DA7219_MIXIN_L_AMP_RAMP_EN_SHIFT, DA7219_SWITCH_EN_MAX,
497*4882a593Smuzhiyun DA7219_NO_INVERT),
498*4882a593Smuzhiyun SOC_SINGLE("Mixin ZC Gain Switch", DA7219_MIXIN_L_CTRL,
499*4882a593Smuzhiyun DA7219_MIXIN_L_AMP_ZC_EN_SHIFT, DA7219_SWITCH_EN_MAX,
500*4882a593Smuzhiyun DA7219_NO_INVERT),
501*4882a593Smuzhiyun
502*4882a593Smuzhiyun /* ADC */
503*4882a593Smuzhiyun SOC_SINGLE_TLV("Capture Digital Volume", DA7219_ADC_L_GAIN,
504*4882a593Smuzhiyun DA7219_ADC_L_DIGITAL_GAIN_SHIFT,
505*4882a593Smuzhiyun DA7219_ADC_L_DIGITAL_GAIN_MAX, DA7219_NO_INVERT,
506*4882a593Smuzhiyun da7219_adc_dig_gain_tlv),
507*4882a593Smuzhiyun SOC_SINGLE("Capture Digital Switch", DA7219_ADC_L_CTRL,
508*4882a593Smuzhiyun DA7219_ADC_L_MUTE_EN_SHIFT, DA7219_SWITCH_EN_MAX,
509*4882a593Smuzhiyun DA7219_INVERT),
510*4882a593Smuzhiyun SOC_SINGLE("Capture Digital Gain Ramp Switch", DA7219_ADC_L_CTRL,
511*4882a593Smuzhiyun DA7219_ADC_L_RAMP_EN_SHIFT, DA7219_SWITCH_EN_MAX,
512*4882a593Smuzhiyun DA7219_NO_INVERT),
513*4882a593Smuzhiyun
514*4882a593Smuzhiyun /* ALC */
515*4882a593Smuzhiyun SOC_ENUM("ALC Attack Rate", da7219_alc_attack_rate),
516*4882a593Smuzhiyun SOC_ENUM("ALC Release Rate", da7219_alc_release_rate),
517*4882a593Smuzhiyun SOC_ENUM("ALC Hold Time", da7219_alc_hold_time),
518*4882a593Smuzhiyun SOC_ENUM("ALC Envelope Attack Rate", da7219_alc_env_attack_rate),
519*4882a593Smuzhiyun SOC_ENUM("ALC Envelope Release Rate", da7219_alc_env_release_rate),
520*4882a593Smuzhiyun SOC_SINGLE_TLV("ALC Noise Threshold", DA7219_ALC_NOISE,
521*4882a593Smuzhiyun DA7219_ALC_NOISE_SHIFT, DA7219_ALC_THRESHOLD_MAX,
522*4882a593Smuzhiyun DA7219_INVERT, da7219_alc_threshold_tlv),
523*4882a593Smuzhiyun SOC_SINGLE_TLV("ALC Min Threshold", DA7219_ALC_TARGET_MIN,
524*4882a593Smuzhiyun DA7219_ALC_THRESHOLD_MIN_SHIFT, DA7219_ALC_THRESHOLD_MAX,
525*4882a593Smuzhiyun DA7219_INVERT, da7219_alc_threshold_tlv),
526*4882a593Smuzhiyun SOC_SINGLE_TLV("ALC Max Threshold", DA7219_ALC_TARGET_MAX,
527*4882a593Smuzhiyun DA7219_ALC_THRESHOLD_MAX_SHIFT, DA7219_ALC_THRESHOLD_MAX,
528*4882a593Smuzhiyun DA7219_INVERT, da7219_alc_threshold_tlv),
529*4882a593Smuzhiyun SOC_SINGLE_TLV("ALC Max Attenuation", DA7219_ALC_GAIN_LIMITS,
530*4882a593Smuzhiyun DA7219_ALC_ATTEN_MAX_SHIFT, DA7219_ALC_ATTEN_GAIN_MAX,
531*4882a593Smuzhiyun DA7219_NO_INVERT, da7219_alc_gain_tlv),
532*4882a593Smuzhiyun SOC_SINGLE_TLV("ALC Max Volume", DA7219_ALC_GAIN_LIMITS,
533*4882a593Smuzhiyun DA7219_ALC_GAIN_MAX_SHIFT, DA7219_ALC_ATTEN_GAIN_MAX,
534*4882a593Smuzhiyun DA7219_NO_INVERT, da7219_alc_gain_tlv),
535*4882a593Smuzhiyun SOC_SINGLE_RANGE_TLV("ALC Min Analog Volume", DA7219_ALC_ANA_GAIN_LIMITS,
536*4882a593Smuzhiyun DA7219_ALC_ANA_GAIN_MIN_SHIFT,
537*4882a593Smuzhiyun DA7219_ALC_ANA_GAIN_MIN, DA7219_ALC_ANA_GAIN_MAX,
538*4882a593Smuzhiyun DA7219_NO_INVERT, da7219_alc_ana_gain_tlv),
539*4882a593Smuzhiyun SOC_SINGLE_RANGE_TLV("ALC Max Analog Volume", DA7219_ALC_ANA_GAIN_LIMITS,
540*4882a593Smuzhiyun DA7219_ALC_ANA_GAIN_MAX_SHIFT,
541*4882a593Smuzhiyun DA7219_ALC_ANA_GAIN_MIN, DA7219_ALC_ANA_GAIN_MAX,
542*4882a593Smuzhiyun DA7219_NO_INVERT, da7219_alc_ana_gain_tlv),
543*4882a593Smuzhiyun SOC_ENUM("ALC Anticlip Step", da7219_alc_anticlip_step),
544*4882a593Smuzhiyun SOC_SINGLE("ALC Anticlip Switch", DA7219_ALC_ANTICLIP_CTRL,
545*4882a593Smuzhiyun DA7219_ALC_ANTIPCLIP_EN_SHIFT, DA7219_SWITCH_EN_MAX,
546*4882a593Smuzhiyun DA7219_NO_INVERT),
547*4882a593Smuzhiyun SOC_SINGLE_EXT("ALC Switch", DA7219_ALC_CTRL1, DA7219_ALC_EN_SHIFT,
548*4882a593Smuzhiyun DA7219_SWITCH_EN_MAX, DA7219_NO_INVERT,
549*4882a593Smuzhiyun snd_soc_get_volsw, da7219_alc_sw_put),
550*4882a593Smuzhiyun
551*4882a593Smuzhiyun /* Input High-Pass Filters */
552*4882a593Smuzhiyun SOC_ENUM("ADC HPF Mode", da7219_adc_hpf_mode),
553*4882a593Smuzhiyun SOC_ENUM("ADC HPF Corner Audio", da7219_adc_audio_hpf_corner),
554*4882a593Smuzhiyun SOC_ENUM("ADC HPF Corner Voice", da7219_adc_voice_hpf_corner),
555*4882a593Smuzhiyun
556*4882a593Smuzhiyun /* Sidetone Filter */
557*4882a593Smuzhiyun SOC_SINGLE_TLV("Sidetone Volume", DA7219_SIDETONE_GAIN,
558*4882a593Smuzhiyun DA7219_SIDETONE_GAIN_SHIFT, DA7219_SIDETONE_GAIN_MAX,
559*4882a593Smuzhiyun DA7219_NO_INVERT, da7219_sidetone_gain_tlv),
560*4882a593Smuzhiyun SOC_SINGLE("Sidetone Switch", DA7219_SIDETONE_CTRL,
561*4882a593Smuzhiyun DA7219_SIDETONE_MUTE_EN_SHIFT, DA7219_SWITCH_EN_MAX,
562*4882a593Smuzhiyun DA7219_INVERT),
563*4882a593Smuzhiyun
564*4882a593Smuzhiyun /* Tone Generator */
565*4882a593Smuzhiyun SOC_SINGLE_EXT_TLV("ToneGen Volume", DA7219_TONE_GEN_CFG2,
566*4882a593Smuzhiyun DA7219_TONE_GEN_GAIN_SHIFT, DA7219_TONE_GEN_GAIN_MAX,
567*4882a593Smuzhiyun DA7219_NO_INVERT, da7219_volsw_locked_get,
568*4882a593Smuzhiyun da7219_volsw_locked_put, da7219_tonegen_gain_tlv),
569*4882a593Smuzhiyun SOC_ENUM_EXT("ToneGen DTMF Key", da7219_tonegen_dtmf_key,
570*4882a593Smuzhiyun da7219_enum_locked_get, da7219_enum_locked_put),
571*4882a593Smuzhiyun SOC_SINGLE_EXT("ToneGen DTMF Switch", DA7219_TONE_GEN_CFG1,
572*4882a593Smuzhiyun DA7219_DTMF_EN_SHIFT, DA7219_SWITCH_EN_MAX,
573*4882a593Smuzhiyun DA7219_NO_INVERT, da7219_volsw_locked_get,
574*4882a593Smuzhiyun da7219_volsw_locked_put),
575*4882a593Smuzhiyun SOC_ENUM_EXT("ToneGen Sinewave Gen Type", da7219_tonegen_swg_sel,
576*4882a593Smuzhiyun da7219_enum_locked_get, da7219_enum_locked_put),
577*4882a593Smuzhiyun SOC_SINGLE_EXT("ToneGen Sinewave1 Freq", DA7219_TONE_GEN_FREQ1_L,
578*4882a593Smuzhiyun DA7219_FREQ1_L_SHIFT, DA7219_FREQ_MAX, DA7219_NO_INVERT,
579*4882a593Smuzhiyun da7219_tonegen_freq_get, da7219_tonegen_freq_put),
580*4882a593Smuzhiyun SOC_SINGLE_EXT("ToneGen Sinewave2 Freq", DA7219_TONE_GEN_FREQ2_L,
581*4882a593Smuzhiyun DA7219_FREQ2_L_SHIFT, DA7219_FREQ_MAX, DA7219_NO_INVERT,
582*4882a593Smuzhiyun da7219_tonegen_freq_get, da7219_tonegen_freq_put),
583*4882a593Smuzhiyun SOC_SINGLE_EXT("ToneGen On Time", DA7219_TONE_GEN_ON_PER,
584*4882a593Smuzhiyun DA7219_BEEP_ON_PER_SHIFT, DA7219_BEEP_ON_OFF_MAX,
585*4882a593Smuzhiyun DA7219_NO_INVERT, da7219_volsw_locked_get,
586*4882a593Smuzhiyun da7219_volsw_locked_put),
587*4882a593Smuzhiyun SOC_SINGLE("ToneGen Off Time", DA7219_TONE_GEN_OFF_PER,
588*4882a593Smuzhiyun DA7219_BEEP_OFF_PER_SHIFT, DA7219_BEEP_ON_OFF_MAX,
589*4882a593Smuzhiyun DA7219_NO_INVERT),
590*4882a593Smuzhiyun
591*4882a593Smuzhiyun /* Gain ramping */
592*4882a593Smuzhiyun SOC_ENUM("Gain Ramp Rate", da7219_gain_ramp_rate),
593*4882a593Smuzhiyun
594*4882a593Smuzhiyun /* DAC High-Pass Filter */
595*4882a593Smuzhiyun SOC_ENUM_EXT("DAC HPF Mode", da7219_dac_hpf_mode,
596*4882a593Smuzhiyun da7219_enum_locked_get, da7219_enum_locked_put),
597*4882a593Smuzhiyun SOC_ENUM("DAC HPF Corner Audio", da7219_dac_audio_hpf_corner),
598*4882a593Smuzhiyun SOC_ENUM("DAC HPF Corner Voice", da7219_dac_voice_hpf_corner),
599*4882a593Smuzhiyun
600*4882a593Smuzhiyun /* DAC 5-Band Equaliser */
601*4882a593Smuzhiyun SOC_SINGLE_TLV("DAC EQ Band1 Volume", DA7219_DAC_FILTERS2,
602*4882a593Smuzhiyun DA7219_DAC_EQ_BAND1_SHIFT, DA7219_DAC_EQ_BAND_MAX,
603*4882a593Smuzhiyun DA7219_NO_INVERT, da7219_dac_eq_band_tlv),
604*4882a593Smuzhiyun SOC_SINGLE_TLV("DAC EQ Band2 Volume", DA7219_DAC_FILTERS2,
605*4882a593Smuzhiyun DA7219_DAC_EQ_BAND2_SHIFT, DA7219_DAC_EQ_BAND_MAX,
606*4882a593Smuzhiyun DA7219_NO_INVERT, da7219_dac_eq_band_tlv),
607*4882a593Smuzhiyun SOC_SINGLE_TLV("DAC EQ Band3 Volume", DA7219_DAC_FILTERS3,
608*4882a593Smuzhiyun DA7219_DAC_EQ_BAND3_SHIFT, DA7219_DAC_EQ_BAND_MAX,
609*4882a593Smuzhiyun DA7219_NO_INVERT, da7219_dac_eq_band_tlv),
610*4882a593Smuzhiyun SOC_SINGLE_TLV("DAC EQ Band4 Volume", DA7219_DAC_FILTERS3,
611*4882a593Smuzhiyun DA7219_DAC_EQ_BAND4_SHIFT, DA7219_DAC_EQ_BAND_MAX,
612*4882a593Smuzhiyun DA7219_NO_INVERT, da7219_dac_eq_band_tlv),
613*4882a593Smuzhiyun SOC_SINGLE_TLV("DAC EQ Band5 Volume", DA7219_DAC_FILTERS4,
614*4882a593Smuzhiyun DA7219_DAC_EQ_BAND5_SHIFT, DA7219_DAC_EQ_BAND_MAX,
615*4882a593Smuzhiyun DA7219_NO_INVERT, da7219_dac_eq_band_tlv),
616*4882a593Smuzhiyun SOC_SINGLE_EXT("DAC EQ Switch", DA7219_DAC_FILTERS4,
617*4882a593Smuzhiyun DA7219_DAC_EQ_EN_SHIFT, DA7219_SWITCH_EN_MAX,
618*4882a593Smuzhiyun DA7219_NO_INVERT, da7219_volsw_locked_get,
619*4882a593Smuzhiyun da7219_volsw_locked_put),
620*4882a593Smuzhiyun
621*4882a593Smuzhiyun /* DAC Softmute */
622*4882a593Smuzhiyun SOC_ENUM("DAC Soft Mute Rate", da7219_dac_softmute_rate),
623*4882a593Smuzhiyun SOC_SINGLE_EXT("DAC Soft Mute Switch", DA7219_DAC_FILTERS5,
624*4882a593Smuzhiyun DA7219_DAC_SOFTMUTE_EN_SHIFT, DA7219_SWITCH_EN_MAX,
625*4882a593Smuzhiyun DA7219_NO_INVERT, da7219_volsw_locked_get,
626*4882a593Smuzhiyun da7219_volsw_locked_put),
627*4882a593Smuzhiyun
628*4882a593Smuzhiyun /* DAC Noise Gate */
629*4882a593Smuzhiyun SOC_ENUM("DAC NG Setup Time", da7219_dac_ng_setup_time),
630*4882a593Smuzhiyun SOC_ENUM("DAC NG Rampup Rate", da7219_dac_ng_rampup_rate),
631*4882a593Smuzhiyun SOC_ENUM("DAC NG Rampdown Rate", da7219_dac_ng_rampdown_rate),
632*4882a593Smuzhiyun SOC_SINGLE_TLV("DAC NG Off Threshold", DA7219_DAC_NG_OFF_THRESH,
633*4882a593Smuzhiyun DA7219_DAC_NG_OFF_THRESHOLD_SHIFT,
634*4882a593Smuzhiyun DA7219_DAC_NG_THRESHOLD_MAX, DA7219_NO_INVERT,
635*4882a593Smuzhiyun da7219_dac_ng_threshold_tlv),
636*4882a593Smuzhiyun SOC_SINGLE_TLV("DAC NG On Threshold", DA7219_DAC_NG_ON_THRESH,
637*4882a593Smuzhiyun DA7219_DAC_NG_ON_THRESHOLD_SHIFT,
638*4882a593Smuzhiyun DA7219_DAC_NG_THRESHOLD_MAX, DA7219_NO_INVERT,
639*4882a593Smuzhiyun da7219_dac_ng_threshold_tlv),
640*4882a593Smuzhiyun SOC_SINGLE("DAC NG Switch", DA7219_DAC_NG_CTRL, DA7219_DAC_NG_EN_SHIFT,
641*4882a593Smuzhiyun DA7219_SWITCH_EN_MAX, DA7219_NO_INVERT),
642*4882a593Smuzhiyun
643*4882a593Smuzhiyun /* DACs */
644*4882a593Smuzhiyun SOC_DOUBLE_R_EXT_TLV("Playback Digital Volume", DA7219_DAC_L_GAIN,
645*4882a593Smuzhiyun DA7219_DAC_R_GAIN, DA7219_DAC_L_DIGITAL_GAIN_SHIFT,
646*4882a593Smuzhiyun DA7219_DAC_DIGITAL_GAIN_MAX, DA7219_NO_INVERT,
647*4882a593Smuzhiyun da7219_volsw_locked_get, da7219_volsw_locked_put,
648*4882a593Smuzhiyun da7219_dac_dig_gain_tlv),
649*4882a593Smuzhiyun SOC_DOUBLE_R_EXT("Playback Digital Switch", DA7219_DAC_L_CTRL,
650*4882a593Smuzhiyun DA7219_DAC_R_CTRL, DA7219_DAC_L_MUTE_EN_SHIFT,
651*4882a593Smuzhiyun DA7219_SWITCH_EN_MAX, DA7219_INVERT,
652*4882a593Smuzhiyun da7219_volsw_locked_get, da7219_volsw_locked_put),
653*4882a593Smuzhiyun SOC_DOUBLE_R("Playback Digital Gain Ramp Switch", DA7219_DAC_L_CTRL,
654*4882a593Smuzhiyun DA7219_DAC_R_CTRL, DA7219_DAC_L_RAMP_EN_SHIFT,
655*4882a593Smuzhiyun DA7219_SWITCH_EN_MAX, DA7219_NO_INVERT),
656*4882a593Smuzhiyun
657*4882a593Smuzhiyun /* CP */
658*4882a593Smuzhiyun SOC_ENUM("Charge Pump Track Mode", da7219_cp_track_mode),
659*4882a593Smuzhiyun SOC_SINGLE("Charge Pump Threshold", DA7219_CP_VOL_THRESHOLD1,
660*4882a593Smuzhiyun DA7219_CP_THRESH_VDD2_SHIFT, DA7219_CP_THRESH_VDD2_MAX,
661*4882a593Smuzhiyun DA7219_NO_INVERT),
662*4882a593Smuzhiyun
663*4882a593Smuzhiyun /* Headphones */
664*4882a593Smuzhiyun SOC_DOUBLE_R_EXT_TLV("Headphone Volume", DA7219_HP_L_GAIN,
665*4882a593Smuzhiyun DA7219_HP_R_GAIN, DA7219_HP_L_AMP_GAIN_SHIFT,
666*4882a593Smuzhiyun DA7219_HP_AMP_GAIN_MAX, DA7219_NO_INVERT,
667*4882a593Smuzhiyun da7219_volsw_locked_get, da7219_volsw_locked_put,
668*4882a593Smuzhiyun da7219_hp_gain_tlv),
669*4882a593Smuzhiyun SOC_DOUBLE_R_EXT("Headphone Switch", DA7219_HP_L_CTRL, DA7219_HP_R_CTRL,
670*4882a593Smuzhiyun DA7219_HP_L_AMP_MUTE_EN_SHIFT, DA7219_SWITCH_EN_MAX,
671*4882a593Smuzhiyun DA7219_INVERT, da7219_volsw_locked_get,
672*4882a593Smuzhiyun da7219_volsw_locked_put),
673*4882a593Smuzhiyun SOC_DOUBLE_R("Headphone Gain Ramp Switch", DA7219_HP_L_CTRL,
674*4882a593Smuzhiyun DA7219_HP_R_CTRL, DA7219_HP_L_AMP_RAMP_EN_SHIFT,
675*4882a593Smuzhiyun DA7219_SWITCH_EN_MAX, DA7219_NO_INVERT),
676*4882a593Smuzhiyun SOC_DOUBLE_R("Headphone ZC Gain Switch", DA7219_HP_L_CTRL,
677*4882a593Smuzhiyun DA7219_HP_R_CTRL, DA7219_HP_L_AMP_ZC_EN_SHIFT,
678*4882a593Smuzhiyun DA7219_SWITCH_EN_MAX, DA7219_NO_INVERT),
679*4882a593Smuzhiyun };
680*4882a593Smuzhiyun
681*4882a593Smuzhiyun
682*4882a593Smuzhiyun /*
683*4882a593Smuzhiyun * DAPM Mux Controls
684*4882a593Smuzhiyun */
685*4882a593Smuzhiyun
686*4882a593Smuzhiyun static const char * const da7219_out_sel_txt[] = {
687*4882a593Smuzhiyun "ADC", "Tone Generator", "DAIL", "DAIR"
688*4882a593Smuzhiyun };
689*4882a593Smuzhiyun
690*4882a593Smuzhiyun static const struct soc_enum da7219_out_dail_sel =
691*4882a593Smuzhiyun SOC_ENUM_SINGLE(DA7219_DIG_ROUTING_DAI,
692*4882a593Smuzhiyun DA7219_DAI_L_SRC_SHIFT,
693*4882a593Smuzhiyun DA7219_OUT_SRC_MAX,
694*4882a593Smuzhiyun da7219_out_sel_txt);
695*4882a593Smuzhiyun
696*4882a593Smuzhiyun static const struct snd_kcontrol_new da7219_out_dail_sel_mux =
697*4882a593Smuzhiyun SOC_DAPM_ENUM("Out DAIL Mux", da7219_out_dail_sel);
698*4882a593Smuzhiyun
699*4882a593Smuzhiyun static const struct soc_enum da7219_out_dair_sel =
700*4882a593Smuzhiyun SOC_ENUM_SINGLE(DA7219_DIG_ROUTING_DAI,
701*4882a593Smuzhiyun DA7219_DAI_R_SRC_SHIFT,
702*4882a593Smuzhiyun DA7219_OUT_SRC_MAX,
703*4882a593Smuzhiyun da7219_out_sel_txt);
704*4882a593Smuzhiyun
705*4882a593Smuzhiyun static const struct snd_kcontrol_new da7219_out_dair_sel_mux =
706*4882a593Smuzhiyun SOC_DAPM_ENUM("Out DAIR Mux", da7219_out_dair_sel);
707*4882a593Smuzhiyun
708*4882a593Smuzhiyun static const struct soc_enum da7219_out_dacl_sel =
709*4882a593Smuzhiyun SOC_ENUM_SINGLE(DA7219_DIG_ROUTING_DAC,
710*4882a593Smuzhiyun DA7219_DAC_L_SRC_SHIFT,
711*4882a593Smuzhiyun DA7219_OUT_SRC_MAX,
712*4882a593Smuzhiyun da7219_out_sel_txt);
713*4882a593Smuzhiyun
714*4882a593Smuzhiyun static const struct snd_kcontrol_new da7219_out_dacl_sel_mux =
715*4882a593Smuzhiyun SOC_DAPM_ENUM("Out DACL Mux", da7219_out_dacl_sel);
716*4882a593Smuzhiyun
717*4882a593Smuzhiyun static const struct soc_enum da7219_out_dacr_sel =
718*4882a593Smuzhiyun SOC_ENUM_SINGLE(DA7219_DIG_ROUTING_DAC,
719*4882a593Smuzhiyun DA7219_DAC_R_SRC_SHIFT,
720*4882a593Smuzhiyun DA7219_OUT_SRC_MAX,
721*4882a593Smuzhiyun da7219_out_sel_txt);
722*4882a593Smuzhiyun
723*4882a593Smuzhiyun static const struct snd_kcontrol_new da7219_out_dacr_sel_mux =
724*4882a593Smuzhiyun SOC_DAPM_ENUM("Out DACR Mux", da7219_out_dacr_sel);
725*4882a593Smuzhiyun
726*4882a593Smuzhiyun
727*4882a593Smuzhiyun /*
728*4882a593Smuzhiyun * DAPM Mixer Controls
729*4882a593Smuzhiyun */
730*4882a593Smuzhiyun
731*4882a593Smuzhiyun static const struct snd_kcontrol_new da7219_mixin_controls[] = {
732*4882a593Smuzhiyun SOC_DAPM_SINGLE("Mic Switch", DA7219_MIXIN_L_SELECT,
733*4882a593Smuzhiyun DA7219_MIXIN_L_MIX_SELECT_SHIFT,
734*4882a593Smuzhiyun DA7219_SWITCH_EN_MAX, DA7219_NO_INVERT),
735*4882a593Smuzhiyun };
736*4882a593Smuzhiyun
737*4882a593Smuzhiyun static const struct snd_kcontrol_new da7219_mixout_l_controls[] = {
738*4882a593Smuzhiyun SOC_DAPM_SINGLE("DACL Switch", DA7219_MIXOUT_L_SELECT,
739*4882a593Smuzhiyun DA7219_MIXOUT_L_MIX_SELECT_SHIFT,
740*4882a593Smuzhiyun DA7219_SWITCH_EN_MAX, DA7219_NO_INVERT),
741*4882a593Smuzhiyun };
742*4882a593Smuzhiyun
743*4882a593Smuzhiyun static const struct snd_kcontrol_new da7219_mixout_r_controls[] = {
744*4882a593Smuzhiyun SOC_DAPM_SINGLE("DACR Switch", DA7219_MIXOUT_R_SELECT,
745*4882a593Smuzhiyun DA7219_MIXOUT_R_MIX_SELECT_SHIFT,
746*4882a593Smuzhiyun DA7219_SWITCH_EN_MAX, DA7219_NO_INVERT),
747*4882a593Smuzhiyun };
748*4882a593Smuzhiyun
749*4882a593Smuzhiyun #define DA7219_DMIX_ST_CTRLS(reg) \
750*4882a593Smuzhiyun SOC_DAPM_SINGLE("Out FilterL Switch", reg, \
751*4882a593Smuzhiyun DA7219_DMIX_ST_SRC_OUTFILT1L_SHIFT, \
752*4882a593Smuzhiyun DA7219_SWITCH_EN_MAX, DA7219_NO_INVERT), \
753*4882a593Smuzhiyun SOC_DAPM_SINGLE("Out FilterR Switch", reg, \
754*4882a593Smuzhiyun DA7219_DMIX_ST_SRC_OUTFILT1R_SHIFT, \
755*4882a593Smuzhiyun DA7219_SWITCH_EN_MAX, DA7219_NO_INVERT), \
756*4882a593Smuzhiyun SOC_DAPM_SINGLE("Sidetone Switch", reg, \
757*4882a593Smuzhiyun DA7219_DMIX_ST_SRC_SIDETONE_SHIFT, \
758*4882a593Smuzhiyun DA7219_SWITCH_EN_MAX, DA7219_NO_INVERT) \
759*4882a593Smuzhiyun
760*4882a593Smuzhiyun static const struct snd_kcontrol_new da7219_st_out_filtl_mix_controls[] = {
761*4882a593Smuzhiyun DA7219_DMIX_ST_CTRLS(DA7219_DROUTING_ST_OUTFILT_1L),
762*4882a593Smuzhiyun };
763*4882a593Smuzhiyun
764*4882a593Smuzhiyun static const struct snd_kcontrol_new da7219_st_out_filtr_mix_controls[] = {
765*4882a593Smuzhiyun DA7219_DMIX_ST_CTRLS(DA7219_DROUTING_ST_OUTFILT_1R),
766*4882a593Smuzhiyun };
767*4882a593Smuzhiyun
768*4882a593Smuzhiyun
769*4882a593Smuzhiyun /*
770*4882a593Smuzhiyun * DAPM Events
771*4882a593Smuzhiyun */
772*4882a593Smuzhiyun
da7219_mic_pga_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)773*4882a593Smuzhiyun static int da7219_mic_pga_event(struct snd_soc_dapm_widget *w,
774*4882a593Smuzhiyun struct snd_kcontrol *kcontrol, int event)
775*4882a593Smuzhiyun {
776*4882a593Smuzhiyun struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
777*4882a593Smuzhiyun struct da7219_priv *da7219 = snd_soc_component_get_drvdata(component);
778*4882a593Smuzhiyun
779*4882a593Smuzhiyun switch (event) {
780*4882a593Smuzhiyun case SND_SOC_DAPM_POST_PMU:
781*4882a593Smuzhiyun if (da7219->micbias_on_event) {
782*4882a593Smuzhiyun /*
783*4882a593Smuzhiyun * Delay only for first capture after bias enabled to
784*4882a593Smuzhiyun * avoid possible DC offset related noise.
785*4882a593Smuzhiyun */
786*4882a593Smuzhiyun da7219->micbias_on_event = false;
787*4882a593Smuzhiyun msleep(da7219->mic_pga_delay);
788*4882a593Smuzhiyun }
789*4882a593Smuzhiyun break;
790*4882a593Smuzhiyun default:
791*4882a593Smuzhiyun break;
792*4882a593Smuzhiyun }
793*4882a593Smuzhiyun
794*4882a593Smuzhiyun return 0;
795*4882a593Smuzhiyun }
796*4882a593Smuzhiyun
da7219_dai_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)797*4882a593Smuzhiyun static int da7219_dai_event(struct snd_soc_dapm_widget *w,
798*4882a593Smuzhiyun struct snd_kcontrol *kcontrol, int event)
799*4882a593Smuzhiyun {
800*4882a593Smuzhiyun struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
801*4882a593Smuzhiyun struct da7219_priv *da7219 = snd_soc_component_get_drvdata(component);
802*4882a593Smuzhiyun struct clk *bclk = da7219->dai_clks[DA7219_DAI_BCLK_IDX];
803*4882a593Smuzhiyun u8 pll_ctrl, pll_status;
804*4882a593Smuzhiyun int i = 0, ret;
805*4882a593Smuzhiyun bool srm_lock = false;
806*4882a593Smuzhiyun
807*4882a593Smuzhiyun switch (event) {
808*4882a593Smuzhiyun case SND_SOC_DAPM_PRE_PMU:
809*4882a593Smuzhiyun if (da7219->master) {
810*4882a593Smuzhiyun /* Enable DAI clks for master mode */
811*4882a593Smuzhiyun if (bclk) {
812*4882a593Smuzhiyun ret = clk_prepare_enable(bclk);
813*4882a593Smuzhiyun if (ret) {
814*4882a593Smuzhiyun dev_err(component->dev,
815*4882a593Smuzhiyun "Failed to enable DAI clks\n");
816*4882a593Smuzhiyun return ret;
817*4882a593Smuzhiyun }
818*4882a593Smuzhiyun } else {
819*4882a593Smuzhiyun snd_soc_component_update_bits(component,
820*4882a593Smuzhiyun DA7219_DAI_CLK_MODE,
821*4882a593Smuzhiyun DA7219_DAI_CLK_EN_MASK,
822*4882a593Smuzhiyun DA7219_DAI_CLK_EN_MASK);
823*4882a593Smuzhiyun }
824*4882a593Smuzhiyun }
825*4882a593Smuzhiyun
826*4882a593Smuzhiyun /* PC synchronised to DAI */
827*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7219_PC_COUNT,
828*4882a593Smuzhiyun DA7219_PC_FREERUN_MASK, 0);
829*4882a593Smuzhiyun
830*4882a593Smuzhiyun /* Slave mode, if SRM not enabled no need for status checks */
831*4882a593Smuzhiyun pll_ctrl = snd_soc_component_read(component, DA7219_PLL_CTRL);
832*4882a593Smuzhiyun if ((pll_ctrl & DA7219_PLL_MODE_MASK) != DA7219_PLL_MODE_SRM)
833*4882a593Smuzhiyun return 0;
834*4882a593Smuzhiyun
835*4882a593Smuzhiyun /* Check SRM has locked */
836*4882a593Smuzhiyun do {
837*4882a593Smuzhiyun pll_status = snd_soc_component_read(component, DA7219_PLL_SRM_STS);
838*4882a593Smuzhiyun if (pll_status & DA7219_PLL_SRM_STS_SRM_LOCK) {
839*4882a593Smuzhiyun srm_lock = true;
840*4882a593Smuzhiyun } else {
841*4882a593Smuzhiyun ++i;
842*4882a593Smuzhiyun msleep(50);
843*4882a593Smuzhiyun }
844*4882a593Smuzhiyun } while ((i < DA7219_SRM_CHECK_RETRIES) && (!srm_lock));
845*4882a593Smuzhiyun
846*4882a593Smuzhiyun if (!srm_lock)
847*4882a593Smuzhiyun dev_warn(component->dev, "SRM failed to lock\n");
848*4882a593Smuzhiyun
849*4882a593Smuzhiyun return 0;
850*4882a593Smuzhiyun case SND_SOC_DAPM_POST_PMD:
851*4882a593Smuzhiyun /* PC free-running */
852*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7219_PC_COUNT,
853*4882a593Smuzhiyun DA7219_PC_FREERUN_MASK,
854*4882a593Smuzhiyun DA7219_PC_FREERUN_MASK);
855*4882a593Smuzhiyun
856*4882a593Smuzhiyun /* Disable DAI clks if in master mode */
857*4882a593Smuzhiyun if (da7219->master) {
858*4882a593Smuzhiyun if (bclk)
859*4882a593Smuzhiyun clk_disable_unprepare(bclk);
860*4882a593Smuzhiyun else
861*4882a593Smuzhiyun snd_soc_component_update_bits(component,
862*4882a593Smuzhiyun DA7219_DAI_CLK_MODE,
863*4882a593Smuzhiyun DA7219_DAI_CLK_EN_MASK,
864*4882a593Smuzhiyun 0);
865*4882a593Smuzhiyun }
866*4882a593Smuzhiyun
867*4882a593Smuzhiyun return 0;
868*4882a593Smuzhiyun default:
869*4882a593Smuzhiyun return -EINVAL;
870*4882a593Smuzhiyun }
871*4882a593Smuzhiyun }
872*4882a593Smuzhiyun
da7219_settling_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)873*4882a593Smuzhiyun static int da7219_settling_event(struct snd_soc_dapm_widget *w,
874*4882a593Smuzhiyun struct snd_kcontrol *kcontrol, int event)
875*4882a593Smuzhiyun {
876*4882a593Smuzhiyun switch (event) {
877*4882a593Smuzhiyun case SND_SOC_DAPM_POST_PMU:
878*4882a593Smuzhiyun case SND_SOC_DAPM_POST_PMD:
879*4882a593Smuzhiyun msleep(DA7219_SETTLING_DELAY);
880*4882a593Smuzhiyun break;
881*4882a593Smuzhiyun default:
882*4882a593Smuzhiyun break;
883*4882a593Smuzhiyun }
884*4882a593Smuzhiyun
885*4882a593Smuzhiyun return 0;
886*4882a593Smuzhiyun }
887*4882a593Smuzhiyun
da7219_mixout_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)888*4882a593Smuzhiyun static int da7219_mixout_event(struct snd_soc_dapm_widget *w,
889*4882a593Smuzhiyun struct snd_kcontrol *kcontrol, int event)
890*4882a593Smuzhiyun {
891*4882a593Smuzhiyun struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
892*4882a593Smuzhiyun u8 hp_ctrl, min_gain_mask;
893*4882a593Smuzhiyun
894*4882a593Smuzhiyun switch (w->reg) {
895*4882a593Smuzhiyun case DA7219_MIXOUT_L_CTRL:
896*4882a593Smuzhiyun hp_ctrl = DA7219_HP_L_CTRL;
897*4882a593Smuzhiyun min_gain_mask = DA7219_HP_L_AMP_MIN_GAIN_EN_MASK;
898*4882a593Smuzhiyun break;
899*4882a593Smuzhiyun case DA7219_MIXOUT_R_CTRL:
900*4882a593Smuzhiyun hp_ctrl = DA7219_HP_R_CTRL;
901*4882a593Smuzhiyun min_gain_mask = DA7219_HP_R_AMP_MIN_GAIN_EN_MASK;
902*4882a593Smuzhiyun break;
903*4882a593Smuzhiyun default:
904*4882a593Smuzhiyun return -EINVAL;
905*4882a593Smuzhiyun }
906*4882a593Smuzhiyun
907*4882a593Smuzhiyun switch (event) {
908*4882a593Smuzhiyun case SND_SOC_DAPM_PRE_PMD:
909*4882a593Smuzhiyun /* Enable minimum gain on HP to avoid pops */
910*4882a593Smuzhiyun snd_soc_component_update_bits(component, hp_ctrl, min_gain_mask,
911*4882a593Smuzhiyun min_gain_mask);
912*4882a593Smuzhiyun
913*4882a593Smuzhiyun msleep(DA7219_MIN_GAIN_DELAY);
914*4882a593Smuzhiyun
915*4882a593Smuzhiyun break;
916*4882a593Smuzhiyun case SND_SOC_DAPM_POST_PMU:
917*4882a593Smuzhiyun /* Remove minimum gain on HP */
918*4882a593Smuzhiyun snd_soc_component_update_bits(component, hp_ctrl, min_gain_mask, 0);
919*4882a593Smuzhiyun
920*4882a593Smuzhiyun break;
921*4882a593Smuzhiyun }
922*4882a593Smuzhiyun
923*4882a593Smuzhiyun return 0;
924*4882a593Smuzhiyun }
925*4882a593Smuzhiyun
da7219_gain_ramp_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)926*4882a593Smuzhiyun static int da7219_gain_ramp_event(struct snd_soc_dapm_widget *w,
927*4882a593Smuzhiyun struct snd_kcontrol *kcontrol, int event)
928*4882a593Smuzhiyun {
929*4882a593Smuzhiyun struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
930*4882a593Smuzhiyun struct da7219_priv *da7219 = snd_soc_component_get_drvdata(component);
931*4882a593Smuzhiyun
932*4882a593Smuzhiyun switch (event) {
933*4882a593Smuzhiyun case SND_SOC_DAPM_PRE_PMU:
934*4882a593Smuzhiyun case SND_SOC_DAPM_PRE_PMD:
935*4882a593Smuzhiyun /* Ensure nominal gain ramping for DAPM sequence */
936*4882a593Smuzhiyun da7219->gain_ramp_ctrl =
937*4882a593Smuzhiyun snd_soc_component_read(component, DA7219_GAIN_RAMP_CTRL);
938*4882a593Smuzhiyun snd_soc_component_write(component, DA7219_GAIN_RAMP_CTRL,
939*4882a593Smuzhiyun DA7219_GAIN_RAMP_RATE_NOMINAL);
940*4882a593Smuzhiyun break;
941*4882a593Smuzhiyun case SND_SOC_DAPM_POST_PMU:
942*4882a593Smuzhiyun case SND_SOC_DAPM_POST_PMD:
943*4882a593Smuzhiyun /* Restore previous gain ramp settings */
944*4882a593Smuzhiyun snd_soc_component_write(component, DA7219_GAIN_RAMP_CTRL,
945*4882a593Smuzhiyun da7219->gain_ramp_ctrl);
946*4882a593Smuzhiyun break;
947*4882a593Smuzhiyun }
948*4882a593Smuzhiyun
949*4882a593Smuzhiyun return 0;
950*4882a593Smuzhiyun }
951*4882a593Smuzhiyun
952*4882a593Smuzhiyun
953*4882a593Smuzhiyun /*
954*4882a593Smuzhiyun * DAPM Widgets
955*4882a593Smuzhiyun */
956*4882a593Smuzhiyun
957*4882a593Smuzhiyun static const struct snd_soc_dapm_widget da7219_dapm_widgets[] = {
958*4882a593Smuzhiyun /* Input Supplies */
959*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("Mic Bias", DA7219_MICBIAS_CTRL,
960*4882a593Smuzhiyun DA7219_MICBIAS1_EN_SHIFT, DA7219_NO_INVERT,
961*4882a593Smuzhiyun NULL, 0),
962*4882a593Smuzhiyun
963*4882a593Smuzhiyun /* Inputs */
964*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("MIC"),
965*4882a593Smuzhiyun
966*4882a593Smuzhiyun /* Input PGAs */
967*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("Mic PGA", DA7219_MIC_1_CTRL,
968*4882a593Smuzhiyun DA7219_MIC_1_AMP_EN_SHIFT, DA7219_NO_INVERT,
969*4882a593Smuzhiyun NULL, 0, da7219_mic_pga_event, SND_SOC_DAPM_POST_PMU),
970*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("Mixin PGA", DA7219_MIXIN_L_CTRL,
971*4882a593Smuzhiyun DA7219_MIXIN_L_AMP_EN_SHIFT, DA7219_NO_INVERT,
972*4882a593Smuzhiyun NULL, 0, da7219_settling_event, SND_SOC_DAPM_POST_PMU),
973*4882a593Smuzhiyun
974*4882a593Smuzhiyun /* Input Filters */
975*4882a593Smuzhiyun SND_SOC_DAPM_ADC("ADC", NULL, DA7219_ADC_L_CTRL, DA7219_ADC_L_EN_SHIFT,
976*4882a593Smuzhiyun DA7219_NO_INVERT),
977*4882a593Smuzhiyun
978*4882a593Smuzhiyun /* Tone Generator */
979*4882a593Smuzhiyun SND_SOC_DAPM_SIGGEN("TONE"),
980*4882a593Smuzhiyun SND_SOC_DAPM_PGA("Tone Generator", DA7219_TONE_GEN_CFG1,
981*4882a593Smuzhiyun DA7219_START_STOPN_SHIFT, DA7219_NO_INVERT, NULL, 0),
982*4882a593Smuzhiyun
983*4882a593Smuzhiyun /* Sidetone Input */
984*4882a593Smuzhiyun SND_SOC_DAPM_ADC("Sidetone Filter", NULL, DA7219_SIDETONE_CTRL,
985*4882a593Smuzhiyun DA7219_SIDETONE_EN_SHIFT, DA7219_NO_INVERT),
986*4882a593Smuzhiyun
987*4882a593Smuzhiyun /* Input Mixer Supply */
988*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("Mixer In Supply", DA7219_MIXIN_L_CTRL,
989*4882a593Smuzhiyun DA7219_MIXIN_L_MIX_EN_SHIFT, DA7219_NO_INVERT,
990*4882a593Smuzhiyun NULL, 0),
991*4882a593Smuzhiyun
992*4882a593Smuzhiyun /* Input Mixer */
993*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("Mixer In", SND_SOC_NOPM, 0, 0,
994*4882a593Smuzhiyun da7219_mixin_controls,
995*4882a593Smuzhiyun ARRAY_SIZE(da7219_mixin_controls)),
996*4882a593Smuzhiyun
997*4882a593Smuzhiyun /* Input Muxes */
998*4882a593Smuzhiyun SND_SOC_DAPM_MUX("Out DAIL Mux", SND_SOC_NOPM, 0, 0,
999*4882a593Smuzhiyun &da7219_out_dail_sel_mux),
1000*4882a593Smuzhiyun SND_SOC_DAPM_MUX("Out DAIR Mux", SND_SOC_NOPM, 0, 0,
1001*4882a593Smuzhiyun &da7219_out_dair_sel_mux),
1002*4882a593Smuzhiyun
1003*4882a593Smuzhiyun /* DAI Supply */
1004*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("DAI", DA7219_DAI_CTRL, DA7219_DAI_EN_SHIFT,
1005*4882a593Smuzhiyun DA7219_NO_INVERT, da7219_dai_event,
1006*4882a593Smuzhiyun SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1007*4882a593Smuzhiyun
1008*4882a593Smuzhiyun /* DAI */
1009*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("DAIOUT", "Capture", 0, DA7219_DAI_TDM_CTRL,
1010*4882a593Smuzhiyun DA7219_DAI_OE_SHIFT, DA7219_NO_INVERT),
1011*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("DAIIN", "Playback", 0, SND_SOC_NOPM, 0, 0),
1012*4882a593Smuzhiyun
1013*4882a593Smuzhiyun /* Output Muxes */
1014*4882a593Smuzhiyun SND_SOC_DAPM_MUX("Out DACL Mux", SND_SOC_NOPM, 0, 0,
1015*4882a593Smuzhiyun &da7219_out_dacl_sel_mux),
1016*4882a593Smuzhiyun SND_SOC_DAPM_MUX("Out DACR Mux", SND_SOC_NOPM, 0, 0,
1017*4882a593Smuzhiyun &da7219_out_dacr_sel_mux),
1018*4882a593Smuzhiyun
1019*4882a593Smuzhiyun /* Output Mixers */
1020*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("Mixer Out FilterL", SND_SOC_NOPM, 0, 0,
1021*4882a593Smuzhiyun da7219_mixout_l_controls,
1022*4882a593Smuzhiyun ARRAY_SIZE(da7219_mixout_l_controls)),
1023*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("Mixer Out FilterR", SND_SOC_NOPM, 0, 0,
1024*4882a593Smuzhiyun da7219_mixout_r_controls,
1025*4882a593Smuzhiyun ARRAY_SIZE(da7219_mixout_r_controls)),
1026*4882a593Smuzhiyun
1027*4882a593Smuzhiyun /* Sidetone Mixers */
1028*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("ST Mixer Out FilterL", SND_SOC_NOPM, 0, 0,
1029*4882a593Smuzhiyun da7219_st_out_filtl_mix_controls,
1030*4882a593Smuzhiyun ARRAY_SIZE(da7219_st_out_filtl_mix_controls)),
1031*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("ST Mixer Out FilterR", SND_SOC_NOPM, 0,
1032*4882a593Smuzhiyun 0, da7219_st_out_filtr_mix_controls,
1033*4882a593Smuzhiyun ARRAY_SIZE(da7219_st_out_filtr_mix_controls)),
1034*4882a593Smuzhiyun
1035*4882a593Smuzhiyun /* DACs */
1036*4882a593Smuzhiyun SND_SOC_DAPM_DAC_E("DACL", NULL, DA7219_DAC_L_CTRL,
1037*4882a593Smuzhiyun DA7219_DAC_L_EN_SHIFT, DA7219_NO_INVERT,
1038*4882a593Smuzhiyun da7219_settling_event,
1039*4882a593Smuzhiyun SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1040*4882a593Smuzhiyun SND_SOC_DAPM_DAC_E("DACR", NULL, DA7219_DAC_R_CTRL,
1041*4882a593Smuzhiyun DA7219_DAC_R_EN_SHIFT, DA7219_NO_INVERT,
1042*4882a593Smuzhiyun da7219_settling_event,
1043*4882a593Smuzhiyun SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1044*4882a593Smuzhiyun
1045*4882a593Smuzhiyun /* Output PGAs */
1046*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("Mixout Left PGA", DA7219_MIXOUT_L_CTRL,
1047*4882a593Smuzhiyun DA7219_MIXOUT_L_AMP_EN_SHIFT, DA7219_NO_INVERT,
1048*4882a593Smuzhiyun NULL, 0, da7219_mixout_event,
1049*4882a593Smuzhiyun SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1050*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("Mixout Right PGA", DA7219_MIXOUT_R_CTRL,
1051*4882a593Smuzhiyun DA7219_MIXOUT_R_AMP_EN_SHIFT, DA7219_NO_INVERT,
1052*4882a593Smuzhiyun NULL, 0, da7219_mixout_event,
1053*4882a593Smuzhiyun SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1054*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY_S("Headphone Left PGA", 1, DA7219_HP_L_CTRL,
1055*4882a593Smuzhiyun DA7219_HP_L_AMP_EN_SHIFT, DA7219_NO_INVERT,
1056*4882a593Smuzhiyun da7219_settling_event,
1057*4882a593Smuzhiyun SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1058*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY_S("Headphone Right PGA", 1, DA7219_HP_R_CTRL,
1059*4882a593Smuzhiyun DA7219_HP_R_AMP_EN_SHIFT, DA7219_NO_INVERT,
1060*4882a593Smuzhiyun da7219_settling_event,
1061*4882a593Smuzhiyun SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1062*4882a593Smuzhiyun
1063*4882a593Smuzhiyun /* Output Supplies */
1064*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY_S("Charge Pump", 0, DA7219_CP_CTRL,
1065*4882a593Smuzhiyun DA7219_CP_EN_SHIFT, DA7219_NO_INVERT,
1066*4882a593Smuzhiyun da7219_settling_event,
1067*4882a593Smuzhiyun SND_SOC_DAPM_POST_PMU),
1068*4882a593Smuzhiyun
1069*4882a593Smuzhiyun /* Outputs */
1070*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("HPL"),
1071*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("HPR"),
1072*4882a593Smuzhiyun
1073*4882a593Smuzhiyun /* Pre/Post Power */
1074*4882a593Smuzhiyun SND_SOC_DAPM_PRE("Pre Power Gain Ramp", da7219_gain_ramp_event),
1075*4882a593Smuzhiyun SND_SOC_DAPM_POST("Post Power Gain Ramp", da7219_gain_ramp_event),
1076*4882a593Smuzhiyun };
1077*4882a593Smuzhiyun
1078*4882a593Smuzhiyun
1079*4882a593Smuzhiyun /*
1080*4882a593Smuzhiyun * DAPM Mux Routes
1081*4882a593Smuzhiyun */
1082*4882a593Smuzhiyun
1083*4882a593Smuzhiyun #define DA7219_OUT_DAI_MUX_ROUTES(name) \
1084*4882a593Smuzhiyun {name, "ADC", "Mixer In"}, \
1085*4882a593Smuzhiyun {name, "Tone Generator", "Tone Generator"}, \
1086*4882a593Smuzhiyun {name, "DAIL", "DAIOUT"}, \
1087*4882a593Smuzhiyun {name, "DAIR", "DAIOUT"}
1088*4882a593Smuzhiyun
1089*4882a593Smuzhiyun #define DA7219_OUT_DAC_MUX_ROUTES(name) \
1090*4882a593Smuzhiyun {name, "ADC", "Mixer In"}, \
1091*4882a593Smuzhiyun {name, "Tone Generator", "Tone Generator"}, \
1092*4882a593Smuzhiyun {name, "DAIL", "DAIIN"}, \
1093*4882a593Smuzhiyun {name, "DAIR", "DAIIN"}
1094*4882a593Smuzhiyun
1095*4882a593Smuzhiyun /*
1096*4882a593Smuzhiyun * DAPM Mixer Routes
1097*4882a593Smuzhiyun */
1098*4882a593Smuzhiyun
1099*4882a593Smuzhiyun #define DA7219_DMIX_ST_ROUTES(name) \
1100*4882a593Smuzhiyun {name, "Out FilterL Switch", "Mixer Out FilterL"}, \
1101*4882a593Smuzhiyun {name, "Out FilterR Switch", "Mixer Out FilterR"}, \
1102*4882a593Smuzhiyun {name, "Sidetone Switch", "Sidetone Filter"}
1103*4882a593Smuzhiyun
1104*4882a593Smuzhiyun
1105*4882a593Smuzhiyun /*
1106*4882a593Smuzhiyun * DAPM audio route definition
1107*4882a593Smuzhiyun */
1108*4882a593Smuzhiyun
1109*4882a593Smuzhiyun static const struct snd_soc_dapm_route da7219_audio_map[] = {
1110*4882a593Smuzhiyun /* Input paths */
1111*4882a593Smuzhiyun {"MIC", NULL, "Mic Bias"},
1112*4882a593Smuzhiyun {"Mic PGA", NULL, "MIC"},
1113*4882a593Smuzhiyun {"Mixin PGA", NULL, "Mic PGA"},
1114*4882a593Smuzhiyun {"ADC", NULL, "Mixin PGA"},
1115*4882a593Smuzhiyun
1116*4882a593Smuzhiyun {"Mixer In", NULL, "Mixer In Supply"},
1117*4882a593Smuzhiyun {"Mixer In", "Mic Switch", "ADC"},
1118*4882a593Smuzhiyun
1119*4882a593Smuzhiyun {"Sidetone Filter", NULL, "Mixer In"},
1120*4882a593Smuzhiyun
1121*4882a593Smuzhiyun {"Tone Generator", NULL, "TONE"},
1122*4882a593Smuzhiyun
1123*4882a593Smuzhiyun DA7219_OUT_DAI_MUX_ROUTES("Out DAIL Mux"),
1124*4882a593Smuzhiyun DA7219_OUT_DAI_MUX_ROUTES("Out DAIR Mux"),
1125*4882a593Smuzhiyun
1126*4882a593Smuzhiyun {"DAIOUT", NULL, "Out DAIL Mux"},
1127*4882a593Smuzhiyun {"DAIOUT", NULL, "Out DAIR Mux"},
1128*4882a593Smuzhiyun {"DAIOUT", NULL, "DAI"},
1129*4882a593Smuzhiyun
1130*4882a593Smuzhiyun /* Output paths */
1131*4882a593Smuzhiyun {"DAIIN", NULL, "DAI"},
1132*4882a593Smuzhiyun
1133*4882a593Smuzhiyun DA7219_OUT_DAC_MUX_ROUTES("Out DACL Mux"),
1134*4882a593Smuzhiyun DA7219_OUT_DAC_MUX_ROUTES("Out DACR Mux"),
1135*4882a593Smuzhiyun
1136*4882a593Smuzhiyun {"Mixer Out FilterL", "DACL Switch", "Out DACL Mux"},
1137*4882a593Smuzhiyun {"Mixer Out FilterR", "DACR Switch", "Out DACR Mux"},
1138*4882a593Smuzhiyun
1139*4882a593Smuzhiyun DA7219_DMIX_ST_ROUTES("ST Mixer Out FilterL"),
1140*4882a593Smuzhiyun DA7219_DMIX_ST_ROUTES("ST Mixer Out FilterR"),
1141*4882a593Smuzhiyun
1142*4882a593Smuzhiyun {"DACL", NULL, "ST Mixer Out FilterL"},
1143*4882a593Smuzhiyun {"DACR", NULL, "ST Mixer Out FilterR"},
1144*4882a593Smuzhiyun
1145*4882a593Smuzhiyun {"Mixout Left PGA", NULL, "DACL"},
1146*4882a593Smuzhiyun {"Mixout Right PGA", NULL, "DACR"},
1147*4882a593Smuzhiyun
1148*4882a593Smuzhiyun {"HPL", NULL, "Mixout Left PGA"},
1149*4882a593Smuzhiyun {"HPR", NULL, "Mixout Right PGA"},
1150*4882a593Smuzhiyun
1151*4882a593Smuzhiyun {"HPL", NULL, "Headphone Left PGA"},
1152*4882a593Smuzhiyun {"HPR", NULL, "Headphone Right PGA"},
1153*4882a593Smuzhiyun
1154*4882a593Smuzhiyun {"HPL", NULL, "Charge Pump"},
1155*4882a593Smuzhiyun {"HPR", NULL, "Charge Pump"},
1156*4882a593Smuzhiyun };
1157*4882a593Smuzhiyun
1158*4882a593Smuzhiyun
1159*4882a593Smuzhiyun /*
1160*4882a593Smuzhiyun * DAI operations
1161*4882a593Smuzhiyun */
1162*4882a593Smuzhiyun
da7219_set_dai_sysclk(struct snd_soc_dai * codec_dai,int clk_id,unsigned int freq,int dir)1163*4882a593Smuzhiyun static int da7219_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1164*4882a593Smuzhiyun int clk_id, unsigned int freq, int dir)
1165*4882a593Smuzhiyun {
1166*4882a593Smuzhiyun struct snd_soc_component *component = codec_dai->component;
1167*4882a593Smuzhiyun struct da7219_priv *da7219 = snd_soc_component_get_drvdata(component);
1168*4882a593Smuzhiyun int ret = 0;
1169*4882a593Smuzhiyun
1170*4882a593Smuzhiyun if ((da7219->clk_src == clk_id) && (da7219->mclk_rate == freq))
1171*4882a593Smuzhiyun return 0;
1172*4882a593Smuzhiyun
1173*4882a593Smuzhiyun if ((freq < 2000000) || (freq > 54000000)) {
1174*4882a593Smuzhiyun dev_err(codec_dai->dev, "Unsupported MCLK value %d\n",
1175*4882a593Smuzhiyun freq);
1176*4882a593Smuzhiyun return -EINVAL;
1177*4882a593Smuzhiyun }
1178*4882a593Smuzhiyun
1179*4882a593Smuzhiyun mutex_lock(&da7219->pll_lock);
1180*4882a593Smuzhiyun
1181*4882a593Smuzhiyun switch (clk_id) {
1182*4882a593Smuzhiyun case DA7219_CLKSRC_MCLK_SQR:
1183*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7219_PLL_CTRL,
1184*4882a593Smuzhiyun DA7219_PLL_MCLK_SQR_EN_MASK,
1185*4882a593Smuzhiyun DA7219_PLL_MCLK_SQR_EN_MASK);
1186*4882a593Smuzhiyun break;
1187*4882a593Smuzhiyun case DA7219_CLKSRC_MCLK:
1188*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7219_PLL_CTRL,
1189*4882a593Smuzhiyun DA7219_PLL_MCLK_SQR_EN_MASK, 0);
1190*4882a593Smuzhiyun break;
1191*4882a593Smuzhiyun default:
1192*4882a593Smuzhiyun dev_err(codec_dai->dev, "Unknown clock source %d\n", clk_id);
1193*4882a593Smuzhiyun mutex_unlock(&da7219->pll_lock);
1194*4882a593Smuzhiyun return -EINVAL;
1195*4882a593Smuzhiyun }
1196*4882a593Smuzhiyun
1197*4882a593Smuzhiyun da7219->clk_src = clk_id;
1198*4882a593Smuzhiyun
1199*4882a593Smuzhiyun if (da7219->mclk) {
1200*4882a593Smuzhiyun freq = clk_round_rate(da7219->mclk, freq);
1201*4882a593Smuzhiyun ret = clk_set_rate(da7219->mclk, freq);
1202*4882a593Smuzhiyun if (ret) {
1203*4882a593Smuzhiyun dev_err(codec_dai->dev, "Failed to set clock rate %d\n",
1204*4882a593Smuzhiyun freq);
1205*4882a593Smuzhiyun mutex_unlock(&da7219->pll_lock);
1206*4882a593Smuzhiyun return ret;
1207*4882a593Smuzhiyun }
1208*4882a593Smuzhiyun }
1209*4882a593Smuzhiyun
1210*4882a593Smuzhiyun da7219->mclk_rate = freq;
1211*4882a593Smuzhiyun
1212*4882a593Smuzhiyun mutex_unlock(&da7219->pll_lock);
1213*4882a593Smuzhiyun
1214*4882a593Smuzhiyun return 0;
1215*4882a593Smuzhiyun }
1216*4882a593Smuzhiyun
da7219_set_pll(struct snd_soc_component * component,int source,unsigned int fout)1217*4882a593Smuzhiyun int da7219_set_pll(struct snd_soc_component *component, int source, unsigned int fout)
1218*4882a593Smuzhiyun {
1219*4882a593Smuzhiyun struct da7219_priv *da7219 = snd_soc_component_get_drvdata(component);
1220*4882a593Smuzhiyun
1221*4882a593Smuzhiyun u8 pll_ctrl, indiv_bits, indiv;
1222*4882a593Smuzhiyun u8 pll_frac_top, pll_frac_bot, pll_integer;
1223*4882a593Smuzhiyun u32 freq_ref;
1224*4882a593Smuzhiyun u64 frac_div;
1225*4882a593Smuzhiyun
1226*4882a593Smuzhiyun /* Verify 2MHz - 54MHz MCLK provided, and set input divider */
1227*4882a593Smuzhiyun if (da7219->mclk_rate < 2000000) {
1228*4882a593Smuzhiyun dev_err(component->dev, "PLL input clock %d below valid range\n",
1229*4882a593Smuzhiyun da7219->mclk_rate);
1230*4882a593Smuzhiyun return -EINVAL;
1231*4882a593Smuzhiyun } else if (da7219->mclk_rate <= 4500000) {
1232*4882a593Smuzhiyun indiv_bits = DA7219_PLL_INDIV_2_TO_4_5_MHZ;
1233*4882a593Smuzhiyun indiv = DA7219_PLL_INDIV_2_TO_4_5_MHZ_VAL;
1234*4882a593Smuzhiyun } else if (da7219->mclk_rate <= 9000000) {
1235*4882a593Smuzhiyun indiv_bits = DA7219_PLL_INDIV_4_5_TO_9_MHZ;
1236*4882a593Smuzhiyun indiv = DA7219_PLL_INDIV_4_5_TO_9_MHZ_VAL;
1237*4882a593Smuzhiyun } else if (da7219->mclk_rate <= 18000000) {
1238*4882a593Smuzhiyun indiv_bits = DA7219_PLL_INDIV_9_TO_18_MHZ;
1239*4882a593Smuzhiyun indiv = DA7219_PLL_INDIV_9_TO_18_MHZ_VAL;
1240*4882a593Smuzhiyun } else if (da7219->mclk_rate <= 36000000) {
1241*4882a593Smuzhiyun indiv_bits = DA7219_PLL_INDIV_18_TO_36_MHZ;
1242*4882a593Smuzhiyun indiv = DA7219_PLL_INDIV_18_TO_36_MHZ_VAL;
1243*4882a593Smuzhiyun } else if (da7219->mclk_rate <= 54000000) {
1244*4882a593Smuzhiyun indiv_bits = DA7219_PLL_INDIV_36_TO_54_MHZ;
1245*4882a593Smuzhiyun indiv = DA7219_PLL_INDIV_36_TO_54_MHZ_VAL;
1246*4882a593Smuzhiyun } else {
1247*4882a593Smuzhiyun dev_err(component->dev, "PLL input clock %d above valid range\n",
1248*4882a593Smuzhiyun da7219->mclk_rate);
1249*4882a593Smuzhiyun return -EINVAL;
1250*4882a593Smuzhiyun }
1251*4882a593Smuzhiyun freq_ref = (da7219->mclk_rate / indiv);
1252*4882a593Smuzhiyun pll_ctrl = indiv_bits;
1253*4882a593Smuzhiyun
1254*4882a593Smuzhiyun /* Configure PLL */
1255*4882a593Smuzhiyun switch (source) {
1256*4882a593Smuzhiyun case DA7219_SYSCLK_MCLK:
1257*4882a593Smuzhiyun pll_ctrl |= DA7219_PLL_MODE_BYPASS;
1258*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7219_PLL_CTRL,
1259*4882a593Smuzhiyun DA7219_PLL_INDIV_MASK |
1260*4882a593Smuzhiyun DA7219_PLL_MODE_MASK, pll_ctrl);
1261*4882a593Smuzhiyun return 0;
1262*4882a593Smuzhiyun case DA7219_SYSCLK_PLL:
1263*4882a593Smuzhiyun pll_ctrl |= DA7219_PLL_MODE_NORMAL;
1264*4882a593Smuzhiyun break;
1265*4882a593Smuzhiyun case DA7219_SYSCLK_PLL_SRM:
1266*4882a593Smuzhiyun pll_ctrl |= DA7219_PLL_MODE_SRM;
1267*4882a593Smuzhiyun break;
1268*4882a593Smuzhiyun default:
1269*4882a593Smuzhiyun dev_err(component->dev, "Invalid PLL config\n");
1270*4882a593Smuzhiyun return -EINVAL;
1271*4882a593Smuzhiyun }
1272*4882a593Smuzhiyun
1273*4882a593Smuzhiyun /* Calculate dividers for PLL */
1274*4882a593Smuzhiyun pll_integer = fout / freq_ref;
1275*4882a593Smuzhiyun frac_div = (u64)(fout % freq_ref) * 8192ULL;
1276*4882a593Smuzhiyun do_div(frac_div, freq_ref);
1277*4882a593Smuzhiyun pll_frac_top = (frac_div >> DA7219_BYTE_SHIFT) & DA7219_BYTE_MASK;
1278*4882a593Smuzhiyun pll_frac_bot = (frac_div) & DA7219_BYTE_MASK;
1279*4882a593Smuzhiyun
1280*4882a593Smuzhiyun /* Write PLL config & dividers */
1281*4882a593Smuzhiyun snd_soc_component_write(component, DA7219_PLL_FRAC_TOP, pll_frac_top);
1282*4882a593Smuzhiyun snd_soc_component_write(component, DA7219_PLL_FRAC_BOT, pll_frac_bot);
1283*4882a593Smuzhiyun snd_soc_component_write(component, DA7219_PLL_INTEGER, pll_integer);
1284*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7219_PLL_CTRL,
1285*4882a593Smuzhiyun DA7219_PLL_INDIV_MASK | DA7219_PLL_MODE_MASK,
1286*4882a593Smuzhiyun pll_ctrl);
1287*4882a593Smuzhiyun
1288*4882a593Smuzhiyun return 0;
1289*4882a593Smuzhiyun }
1290*4882a593Smuzhiyun
da7219_set_dai_pll(struct snd_soc_dai * codec_dai,int pll_id,int source,unsigned int fref,unsigned int fout)1291*4882a593Smuzhiyun static int da7219_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
1292*4882a593Smuzhiyun int source, unsigned int fref, unsigned int fout)
1293*4882a593Smuzhiyun {
1294*4882a593Smuzhiyun struct snd_soc_component *component = codec_dai->component;
1295*4882a593Smuzhiyun struct da7219_priv *da7219 = snd_soc_component_get_drvdata(component);
1296*4882a593Smuzhiyun int ret;
1297*4882a593Smuzhiyun
1298*4882a593Smuzhiyun mutex_lock(&da7219->pll_lock);
1299*4882a593Smuzhiyun ret = da7219_set_pll(component, source, fout);
1300*4882a593Smuzhiyun mutex_unlock(&da7219->pll_lock);
1301*4882a593Smuzhiyun
1302*4882a593Smuzhiyun return ret;
1303*4882a593Smuzhiyun }
1304*4882a593Smuzhiyun
da7219_set_dai_fmt(struct snd_soc_dai * codec_dai,unsigned int fmt)1305*4882a593Smuzhiyun static int da7219_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
1306*4882a593Smuzhiyun {
1307*4882a593Smuzhiyun struct snd_soc_component *component = codec_dai->component;
1308*4882a593Smuzhiyun struct da7219_priv *da7219 = snd_soc_component_get_drvdata(component);
1309*4882a593Smuzhiyun u8 dai_clk_mode = 0, dai_ctrl = 0;
1310*4882a593Smuzhiyun
1311*4882a593Smuzhiyun switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1312*4882a593Smuzhiyun case SND_SOC_DAIFMT_CBM_CFM:
1313*4882a593Smuzhiyun da7219->master = true;
1314*4882a593Smuzhiyun break;
1315*4882a593Smuzhiyun case SND_SOC_DAIFMT_CBS_CFS:
1316*4882a593Smuzhiyun da7219->master = false;
1317*4882a593Smuzhiyun break;
1318*4882a593Smuzhiyun default:
1319*4882a593Smuzhiyun return -EINVAL;
1320*4882a593Smuzhiyun }
1321*4882a593Smuzhiyun
1322*4882a593Smuzhiyun switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1323*4882a593Smuzhiyun case SND_SOC_DAIFMT_I2S:
1324*4882a593Smuzhiyun case SND_SOC_DAIFMT_LEFT_J:
1325*4882a593Smuzhiyun case SND_SOC_DAIFMT_RIGHT_J:
1326*4882a593Smuzhiyun switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1327*4882a593Smuzhiyun case SND_SOC_DAIFMT_NB_NF:
1328*4882a593Smuzhiyun break;
1329*4882a593Smuzhiyun case SND_SOC_DAIFMT_NB_IF:
1330*4882a593Smuzhiyun dai_clk_mode |= DA7219_DAI_WCLK_POL_INV;
1331*4882a593Smuzhiyun break;
1332*4882a593Smuzhiyun case SND_SOC_DAIFMT_IB_NF:
1333*4882a593Smuzhiyun dai_clk_mode |= DA7219_DAI_CLK_POL_INV;
1334*4882a593Smuzhiyun break;
1335*4882a593Smuzhiyun case SND_SOC_DAIFMT_IB_IF:
1336*4882a593Smuzhiyun dai_clk_mode |= DA7219_DAI_WCLK_POL_INV |
1337*4882a593Smuzhiyun DA7219_DAI_CLK_POL_INV;
1338*4882a593Smuzhiyun break;
1339*4882a593Smuzhiyun default:
1340*4882a593Smuzhiyun return -EINVAL;
1341*4882a593Smuzhiyun }
1342*4882a593Smuzhiyun break;
1343*4882a593Smuzhiyun case SND_SOC_DAIFMT_DSP_B:
1344*4882a593Smuzhiyun switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1345*4882a593Smuzhiyun case SND_SOC_DAIFMT_NB_NF:
1346*4882a593Smuzhiyun dai_clk_mode |= DA7219_DAI_CLK_POL_INV;
1347*4882a593Smuzhiyun break;
1348*4882a593Smuzhiyun case SND_SOC_DAIFMT_NB_IF:
1349*4882a593Smuzhiyun dai_clk_mode |= DA7219_DAI_WCLK_POL_INV |
1350*4882a593Smuzhiyun DA7219_DAI_CLK_POL_INV;
1351*4882a593Smuzhiyun break;
1352*4882a593Smuzhiyun case SND_SOC_DAIFMT_IB_NF:
1353*4882a593Smuzhiyun break;
1354*4882a593Smuzhiyun case SND_SOC_DAIFMT_IB_IF:
1355*4882a593Smuzhiyun dai_clk_mode |= DA7219_DAI_WCLK_POL_INV;
1356*4882a593Smuzhiyun break;
1357*4882a593Smuzhiyun default:
1358*4882a593Smuzhiyun return -EINVAL;
1359*4882a593Smuzhiyun }
1360*4882a593Smuzhiyun break;
1361*4882a593Smuzhiyun default:
1362*4882a593Smuzhiyun return -EINVAL;
1363*4882a593Smuzhiyun }
1364*4882a593Smuzhiyun
1365*4882a593Smuzhiyun switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1366*4882a593Smuzhiyun case SND_SOC_DAIFMT_I2S:
1367*4882a593Smuzhiyun dai_ctrl |= DA7219_DAI_FORMAT_I2S;
1368*4882a593Smuzhiyun break;
1369*4882a593Smuzhiyun case SND_SOC_DAIFMT_LEFT_J:
1370*4882a593Smuzhiyun dai_ctrl |= DA7219_DAI_FORMAT_LEFT_J;
1371*4882a593Smuzhiyun break;
1372*4882a593Smuzhiyun case SND_SOC_DAIFMT_RIGHT_J:
1373*4882a593Smuzhiyun dai_ctrl |= DA7219_DAI_FORMAT_RIGHT_J;
1374*4882a593Smuzhiyun break;
1375*4882a593Smuzhiyun case SND_SOC_DAIFMT_DSP_B:
1376*4882a593Smuzhiyun dai_ctrl |= DA7219_DAI_FORMAT_DSP;
1377*4882a593Smuzhiyun break;
1378*4882a593Smuzhiyun default:
1379*4882a593Smuzhiyun return -EINVAL;
1380*4882a593Smuzhiyun }
1381*4882a593Smuzhiyun
1382*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7219_DAI_CLK_MODE,
1383*4882a593Smuzhiyun DA7219_DAI_CLK_POL_MASK | DA7219_DAI_WCLK_POL_MASK,
1384*4882a593Smuzhiyun dai_clk_mode);
1385*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7219_DAI_CTRL, DA7219_DAI_FORMAT_MASK,
1386*4882a593Smuzhiyun dai_ctrl);
1387*4882a593Smuzhiyun
1388*4882a593Smuzhiyun return 0;
1389*4882a593Smuzhiyun }
1390*4882a593Smuzhiyun
da7219_set_bclks_per_wclk(struct snd_soc_component * component,unsigned long factor)1391*4882a593Smuzhiyun static int da7219_set_bclks_per_wclk(struct snd_soc_component *component,
1392*4882a593Smuzhiyun unsigned long factor)
1393*4882a593Smuzhiyun {
1394*4882a593Smuzhiyun u8 bclks_per_wclk;
1395*4882a593Smuzhiyun
1396*4882a593Smuzhiyun switch (factor) {
1397*4882a593Smuzhiyun case 32:
1398*4882a593Smuzhiyun bclks_per_wclk = DA7219_DAI_BCLKS_PER_WCLK_32;
1399*4882a593Smuzhiyun break;
1400*4882a593Smuzhiyun case 64:
1401*4882a593Smuzhiyun bclks_per_wclk = DA7219_DAI_BCLKS_PER_WCLK_64;
1402*4882a593Smuzhiyun break;
1403*4882a593Smuzhiyun case 128:
1404*4882a593Smuzhiyun bclks_per_wclk = DA7219_DAI_BCLKS_PER_WCLK_128;
1405*4882a593Smuzhiyun break;
1406*4882a593Smuzhiyun case 256:
1407*4882a593Smuzhiyun bclks_per_wclk = DA7219_DAI_BCLKS_PER_WCLK_256;
1408*4882a593Smuzhiyun break;
1409*4882a593Smuzhiyun default:
1410*4882a593Smuzhiyun return -EINVAL;
1411*4882a593Smuzhiyun }
1412*4882a593Smuzhiyun
1413*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7219_DAI_CLK_MODE,
1414*4882a593Smuzhiyun DA7219_DAI_BCLKS_PER_WCLK_MASK,
1415*4882a593Smuzhiyun bclks_per_wclk);
1416*4882a593Smuzhiyun
1417*4882a593Smuzhiyun return 0;
1418*4882a593Smuzhiyun }
1419*4882a593Smuzhiyun
da7219_set_dai_tdm_slot(struct snd_soc_dai * dai,unsigned int tx_mask,unsigned int rx_mask,int slots,int slot_width)1420*4882a593Smuzhiyun static int da7219_set_dai_tdm_slot(struct snd_soc_dai *dai,
1421*4882a593Smuzhiyun unsigned int tx_mask, unsigned int rx_mask,
1422*4882a593Smuzhiyun int slots, int slot_width)
1423*4882a593Smuzhiyun {
1424*4882a593Smuzhiyun struct snd_soc_component *component = dai->component;
1425*4882a593Smuzhiyun struct da7219_priv *da7219 = snd_soc_component_get_drvdata(component);
1426*4882a593Smuzhiyun struct clk *wclk = da7219->dai_clks[DA7219_DAI_WCLK_IDX];
1427*4882a593Smuzhiyun struct clk *bclk = da7219->dai_clks[DA7219_DAI_BCLK_IDX];
1428*4882a593Smuzhiyun unsigned int ch_mask;
1429*4882a593Smuzhiyun unsigned long sr, bclk_rate;
1430*4882a593Smuzhiyun u8 slot_offset;
1431*4882a593Smuzhiyun u16 offset;
1432*4882a593Smuzhiyun __le16 dai_offset;
1433*4882a593Smuzhiyun u32 frame_size;
1434*4882a593Smuzhiyun int ret;
1435*4882a593Smuzhiyun
1436*4882a593Smuzhiyun /* No channels enabled so disable TDM */
1437*4882a593Smuzhiyun if (!tx_mask) {
1438*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7219_DAI_TDM_CTRL,
1439*4882a593Smuzhiyun DA7219_DAI_TDM_CH_EN_MASK |
1440*4882a593Smuzhiyun DA7219_DAI_TDM_MODE_EN_MASK, 0);
1441*4882a593Smuzhiyun da7219->tdm_en = false;
1442*4882a593Smuzhiyun return 0;
1443*4882a593Smuzhiyun }
1444*4882a593Smuzhiyun
1445*4882a593Smuzhiyun /* Check we have valid slots */
1446*4882a593Smuzhiyun slot_offset = ffs(tx_mask) - 1;
1447*4882a593Smuzhiyun ch_mask = (tx_mask >> slot_offset);
1448*4882a593Smuzhiyun if (fls(ch_mask) > DA7219_DAI_TDM_MAX_SLOTS) {
1449*4882a593Smuzhiyun dev_err(component->dev,
1450*4882a593Smuzhiyun "Invalid number of slots, max = %d\n",
1451*4882a593Smuzhiyun DA7219_DAI_TDM_MAX_SLOTS);
1452*4882a593Smuzhiyun return -EINVAL;
1453*4882a593Smuzhiyun }
1454*4882a593Smuzhiyun
1455*4882a593Smuzhiyun /*
1456*4882a593Smuzhiyun * Ensure we have a valid offset into the frame, based on slot width
1457*4882a593Smuzhiyun * and slot offset of first slot we're interested in.
1458*4882a593Smuzhiyun */
1459*4882a593Smuzhiyun offset = slot_offset * slot_width;
1460*4882a593Smuzhiyun if (offset > DA7219_DAI_OFFSET_MAX) {
1461*4882a593Smuzhiyun dev_err(component->dev, "Invalid frame offset %d\n", offset);
1462*4882a593Smuzhiyun return -EINVAL;
1463*4882a593Smuzhiyun }
1464*4882a593Smuzhiyun
1465*4882a593Smuzhiyun /*
1466*4882a593Smuzhiyun * If we're master, calculate & validate frame size based on slot info
1467*4882a593Smuzhiyun * provided as we have a limited set of rates available.
1468*4882a593Smuzhiyun */
1469*4882a593Smuzhiyun if (da7219->master) {
1470*4882a593Smuzhiyun frame_size = slots * slot_width;
1471*4882a593Smuzhiyun
1472*4882a593Smuzhiyun if (bclk) {
1473*4882a593Smuzhiyun sr = clk_get_rate(wclk);
1474*4882a593Smuzhiyun bclk_rate = sr * frame_size;
1475*4882a593Smuzhiyun ret = clk_set_rate(bclk, bclk_rate);
1476*4882a593Smuzhiyun if (ret) {
1477*4882a593Smuzhiyun dev_err(component->dev,
1478*4882a593Smuzhiyun "Failed to set TDM BCLK rate %lu: %d\n",
1479*4882a593Smuzhiyun bclk_rate, ret);
1480*4882a593Smuzhiyun return ret;
1481*4882a593Smuzhiyun }
1482*4882a593Smuzhiyun } else {
1483*4882a593Smuzhiyun ret = da7219_set_bclks_per_wclk(component, frame_size);
1484*4882a593Smuzhiyun if (ret) {
1485*4882a593Smuzhiyun dev_err(component->dev,
1486*4882a593Smuzhiyun "Failed to set TDM BCLKs per WCLK %d: %d\n",
1487*4882a593Smuzhiyun frame_size, ret);
1488*4882a593Smuzhiyun return ret;
1489*4882a593Smuzhiyun }
1490*4882a593Smuzhiyun }
1491*4882a593Smuzhiyun }
1492*4882a593Smuzhiyun
1493*4882a593Smuzhiyun dai_offset = cpu_to_le16(offset);
1494*4882a593Smuzhiyun regmap_bulk_write(da7219->regmap, DA7219_DAI_OFFSET_LOWER,
1495*4882a593Smuzhiyun &dai_offset, sizeof(dai_offset));
1496*4882a593Smuzhiyun
1497*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7219_DAI_TDM_CTRL,
1498*4882a593Smuzhiyun DA7219_DAI_TDM_CH_EN_MASK |
1499*4882a593Smuzhiyun DA7219_DAI_TDM_MODE_EN_MASK,
1500*4882a593Smuzhiyun (ch_mask << DA7219_DAI_TDM_CH_EN_SHIFT) |
1501*4882a593Smuzhiyun DA7219_DAI_TDM_MODE_EN_MASK);
1502*4882a593Smuzhiyun
1503*4882a593Smuzhiyun da7219->tdm_en = true;
1504*4882a593Smuzhiyun
1505*4882a593Smuzhiyun return 0;
1506*4882a593Smuzhiyun }
1507*4882a593Smuzhiyun
da7219_set_sr(struct snd_soc_component * component,unsigned long rate)1508*4882a593Smuzhiyun static int da7219_set_sr(struct snd_soc_component *component,
1509*4882a593Smuzhiyun unsigned long rate)
1510*4882a593Smuzhiyun {
1511*4882a593Smuzhiyun u8 fs;
1512*4882a593Smuzhiyun
1513*4882a593Smuzhiyun switch (rate) {
1514*4882a593Smuzhiyun case 8000:
1515*4882a593Smuzhiyun fs = DA7219_SR_8000;
1516*4882a593Smuzhiyun break;
1517*4882a593Smuzhiyun case 11025:
1518*4882a593Smuzhiyun fs = DA7219_SR_11025;
1519*4882a593Smuzhiyun break;
1520*4882a593Smuzhiyun case 12000:
1521*4882a593Smuzhiyun fs = DA7219_SR_12000;
1522*4882a593Smuzhiyun break;
1523*4882a593Smuzhiyun case 16000:
1524*4882a593Smuzhiyun fs = DA7219_SR_16000;
1525*4882a593Smuzhiyun break;
1526*4882a593Smuzhiyun case 22050:
1527*4882a593Smuzhiyun fs = DA7219_SR_22050;
1528*4882a593Smuzhiyun break;
1529*4882a593Smuzhiyun case 24000:
1530*4882a593Smuzhiyun fs = DA7219_SR_24000;
1531*4882a593Smuzhiyun break;
1532*4882a593Smuzhiyun case 32000:
1533*4882a593Smuzhiyun fs = DA7219_SR_32000;
1534*4882a593Smuzhiyun break;
1535*4882a593Smuzhiyun case 44100:
1536*4882a593Smuzhiyun fs = DA7219_SR_44100;
1537*4882a593Smuzhiyun break;
1538*4882a593Smuzhiyun case 48000:
1539*4882a593Smuzhiyun fs = DA7219_SR_48000;
1540*4882a593Smuzhiyun break;
1541*4882a593Smuzhiyun case 88200:
1542*4882a593Smuzhiyun fs = DA7219_SR_88200;
1543*4882a593Smuzhiyun break;
1544*4882a593Smuzhiyun case 96000:
1545*4882a593Smuzhiyun fs = DA7219_SR_96000;
1546*4882a593Smuzhiyun break;
1547*4882a593Smuzhiyun default:
1548*4882a593Smuzhiyun return -EINVAL;
1549*4882a593Smuzhiyun }
1550*4882a593Smuzhiyun
1551*4882a593Smuzhiyun snd_soc_component_write(component, DA7219_SR, fs);
1552*4882a593Smuzhiyun
1553*4882a593Smuzhiyun return 0;
1554*4882a593Smuzhiyun }
1555*4882a593Smuzhiyun
da7219_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)1556*4882a593Smuzhiyun static int da7219_hw_params(struct snd_pcm_substream *substream,
1557*4882a593Smuzhiyun struct snd_pcm_hw_params *params,
1558*4882a593Smuzhiyun struct snd_soc_dai *dai)
1559*4882a593Smuzhiyun {
1560*4882a593Smuzhiyun struct snd_soc_component *component = dai->component;
1561*4882a593Smuzhiyun struct da7219_priv *da7219 = snd_soc_component_get_drvdata(component);
1562*4882a593Smuzhiyun struct clk *wclk = da7219->dai_clks[DA7219_DAI_WCLK_IDX];
1563*4882a593Smuzhiyun struct clk *bclk = da7219->dai_clks[DA7219_DAI_BCLK_IDX];
1564*4882a593Smuzhiyun u8 dai_ctrl = 0;
1565*4882a593Smuzhiyun unsigned int channels;
1566*4882a593Smuzhiyun unsigned long sr, bclk_rate;
1567*4882a593Smuzhiyun int word_len = params_width(params);
1568*4882a593Smuzhiyun int frame_size, ret;
1569*4882a593Smuzhiyun
1570*4882a593Smuzhiyun switch (word_len) {
1571*4882a593Smuzhiyun case 16:
1572*4882a593Smuzhiyun dai_ctrl |= DA7219_DAI_WORD_LENGTH_S16_LE;
1573*4882a593Smuzhiyun break;
1574*4882a593Smuzhiyun case 20:
1575*4882a593Smuzhiyun dai_ctrl |= DA7219_DAI_WORD_LENGTH_S20_LE;
1576*4882a593Smuzhiyun break;
1577*4882a593Smuzhiyun case 24:
1578*4882a593Smuzhiyun dai_ctrl |= DA7219_DAI_WORD_LENGTH_S24_LE;
1579*4882a593Smuzhiyun break;
1580*4882a593Smuzhiyun case 32:
1581*4882a593Smuzhiyun dai_ctrl |= DA7219_DAI_WORD_LENGTH_S32_LE;
1582*4882a593Smuzhiyun break;
1583*4882a593Smuzhiyun default:
1584*4882a593Smuzhiyun return -EINVAL;
1585*4882a593Smuzhiyun }
1586*4882a593Smuzhiyun
1587*4882a593Smuzhiyun channels = params_channels(params);
1588*4882a593Smuzhiyun if ((channels < 1) || (channels > DA7219_DAI_CH_NUM_MAX)) {
1589*4882a593Smuzhiyun dev_err(component->dev,
1590*4882a593Smuzhiyun "Invalid number of channels, only 1 to %d supported\n",
1591*4882a593Smuzhiyun DA7219_DAI_CH_NUM_MAX);
1592*4882a593Smuzhiyun return -EINVAL;
1593*4882a593Smuzhiyun }
1594*4882a593Smuzhiyun dai_ctrl |= channels << DA7219_DAI_CH_NUM_SHIFT;
1595*4882a593Smuzhiyun
1596*4882a593Smuzhiyun sr = params_rate(params);
1597*4882a593Smuzhiyun if (da7219->master && wclk) {
1598*4882a593Smuzhiyun ret = clk_set_rate(wclk, sr);
1599*4882a593Smuzhiyun if (ret) {
1600*4882a593Smuzhiyun dev_err(component->dev,
1601*4882a593Smuzhiyun "Failed to set WCLK SR %lu: %d\n", sr, ret);
1602*4882a593Smuzhiyun return ret;
1603*4882a593Smuzhiyun }
1604*4882a593Smuzhiyun } else {
1605*4882a593Smuzhiyun ret = da7219_set_sr(component, sr);
1606*4882a593Smuzhiyun if (ret) {
1607*4882a593Smuzhiyun dev_err(component->dev,
1608*4882a593Smuzhiyun "Failed to set SR %lu: %d\n", sr, ret);
1609*4882a593Smuzhiyun return ret;
1610*4882a593Smuzhiyun }
1611*4882a593Smuzhiyun }
1612*4882a593Smuzhiyun
1613*4882a593Smuzhiyun /*
1614*4882a593Smuzhiyun * If we're master, then we have a limited set of BCLK rates we
1615*4882a593Smuzhiyun * support. For slave mode this isn't the case and the codec can detect
1616*4882a593Smuzhiyun * the BCLK rate automatically.
1617*4882a593Smuzhiyun */
1618*4882a593Smuzhiyun if (da7219->master && !da7219->tdm_en) {
1619*4882a593Smuzhiyun if ((word_len * DA7219_DAI_CH_NUM_MAX) <= 32)
1620*4882a593Smuzhiyun frame_size = 32;
1621*4882a593Smuzhiyun else
1622*4882a593Smuzhiyun frame_size = 64;
1623*4882a593Smuzhiyun
1624*4882a593Smuzhiyun if (bclk) {
1625*4882a593Smuzhiyun bclk_rate = frame_size * sr;
1626*4882a593Smuzhiyun /*
1627*4882a593Smuzhiyun * Rounding the rate here avoids failure trying to set a
1628*4882a593Smuzhiyun * new rate on an already enabled bclk. In that
1629*4882a593Smuzhiyun * instance this will just set the same rate as is
1630*4882a593Smuzhiyun * currently in use, and so should continue without
1631*4882a593Smuzhiyun * problem, as long as the BCLK rate is suitable for the
1632*4882a593Smuzhiyun * desired frame size.
1633*4882a593Smuzhiyun */
1634*4882a593Smuzhiyun bclk_rate = clk_round_rate(bclk, bclk_rate);
1635*4882a593Smuzhiyun if ((bclk_rate / sr) < frame_size) {
1636*4882a593Smuzhiyun dev_err(component->dev,
1637*4882a593Smuzhiyun "BCLK rate mismatch against frame size");
1638*4882a593Smuzhiyun return -EINVAL;
1639*4882a593Smuzhiyun }
1640*4882a593Smuzhiyun
1641*4882a593Smuzhiyun ret = clk_set_rate(bclk, bclk_rate);
1642*4882a593Smuzhiyun if (ret) {
1643*4882a593Smuzhiyun dev_err(component->dev,
1644*4882a593Smuzhiyun "Failed to set BCLK rate %lu: %d\n",
1645*4882a593Smuzhiyun bclk_rate, ret);
1646*4882a593Smuzhiyun return ret;
1647*4882a593Smuzhiyun }
1648*4882a593Smuzhiyun } else {
1649*4882a593Smuzhiyun ret = da7219_set_bclks_per_wclk(component, frame_size);
1650*4882a593Smuzhiyun if (ret) {
1651*4882a593Smuzhiyun dev_err(component->dev,
1652*4882a593Smuzhiyun "Failed to set BCLKs per WCLK %d: %d\n",
1653*4882a593Smuzhiyun frame_size, ret);
1654*4882a593Smuzhiyun return ret;
1655*4882a593Smuzhiyun }
1656*4882a593Smuzhiyun }
1657*4882a593Smuzhiyun }
1658*4882a593Smuzhiyun
1659*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7219_DAI_CTRL,
1660*4882a593Smuzhiyun DA7219_DAI_WORD_LENGTH_MASK |
1661*4882a593Smuzhiyun DA7219_DAI_CH_NUM_MASK,
1662*4882a593Smuzhiyun dai_ctrl);
1663*4882a593Smuzhiyun
1664*4882a593Smuzhiyun return 0;
1665*4882a593Smuzhiyun }
1666*4882a593Smuzhiyun
1667*4882a593Smuzhiyun static const struct snd_soc_dai_ops da7219_dai_ops = {
1668*4882a593Smuzhiyun .hw_params = da7219_hw_params,
1669*4882a593Smuzhiyun .set_sysclk = da7219_set_dai_sysclk,
1670*4882a593Smuzhiyun .set_pll = da7219_set_dai_pll,
1671*4882a593Smuzhiyun .set_fmt = da7219_set_dai_fmt,
1672*4882a593Smuzhiyun .set_tdm_slot = da7219_set_dai_tdm_slot,
1673*4882a593Smuzhiyun };
1674*4882a593Smuzhiyun
1675*4882a593Smuzhiyun #define DA7219_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1676*4882a593Smuzhiyun SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1677*4882a593Smuzhiyun
1678*4882a593Smuzhiyun #define DA7219_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
1679*4882a593Smuzhiyun SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\
1680*4882a593Smuzhiyun SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |\
1681*4882a593Smuzhiyun SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |\
1682*4882a593Smuzhiyun SNDRV_PCM_RATE_96000)
1683*4882a593Smuzhiyun
1684*4882a593Smuzhiyun static struct snd_soc_dai_driver da7219_dai = {
1685*4882a593Smuzhiyun .name = "da7219-hifi",
1686*4882a593Smuzhiyun .playback = {
1687*4882a593Smuzhiyun .stream_name = "Playback",
1688*4882a593Smuzhiyun .channels_min = 1,
1689*4882a593Smuzhiyun .channels_max = DA7219_DAI_CH_NUM_MAX,
1690*4882a593Smuzhiyun .rates = DA7219_RATES,
1691*4882a593Smuzhiyun .formats = DA7219_FORMATS,
1692*4882a593Smuzhiyun },
1693*4882a593Smuzhiyun .capture = {
1694*4882a593Smuzhiyun .stream_name = "Capture",
1695*4882a593Smuzhiyun .channels_min = 1,
1696*4882a593Smuzhiyun .channels_max = DA7219_DAI_CH_NUM_MAX,
1697*4882a593Smuzhiyun .rates = DA7219_RATES,
1698*4882a593Smuzhiyun .formats = DA7219_FORMATS,
1699*4882a593Smuzhiyun },
1700*4882a593Smuzhiyun .ops = &da7219_dai_ops,
1701*4882a593Smuzhiyun .symmetric_rates = 1,
1702*4882a593Smuzhiyun .symmetric_channels = 1,
1703*4882a593Smuzhiyun .symmetric_samplebits = 1,
1704*4882a593Smuzhiyun };
1705*4882a593Smuzhiyun
1706*4882a593Smuzhiyun
1707*4882a593Smuzhiyun /*
1708*4882a593Smuzhiyun * DT/ACPI
1709*4882a593Smuzhiyun */
1710*4882a593Smuzhiyun
1711*4882a593Smuzhiyun static const struct of_device_id da7219_of_match[] = {
1712*4882a593Smuzhiyun { .compatible = "dlg,da7219", },
1713*4882a593Smuzhiyun { }
1714*4882a593Smuzhiyun };
1715*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, da7219_of_match);
1716*4882a593Smuzhiyun
1717*4882a593Smuzhiyun #ifdef CONFIG_ACPI
1718*4882a593Smuzhiyun static const struct acpi_device_id da7219_acpi_match[] = {
1719*4882a593Smuzhiyun { .id = "DLGS7219", },
1720*4882a593Smuzhiyun { }
1721*4882a593Smuzhiyun };
1722*4882a593Smuzhiyun MODULE_DEVICE_TABLE(acpi, da7219_acpi_match);
1723*4882a593Smuzhiyun #endif
1724*4882a593Smuzhiyun
1725*4882a593Smuzhiyun static enum da7219_micbias_voltage
da7219_fw_micbias_lvl(struct device * dev,u32 val)1726*4882a593Smuzhiyun da7219_fw_micbias_lvl(struct device *dev, u32 val)
1727*4882a593Smuzhiyun {
1728*4882a593Smuzhiyun switch (val) {
1729*4882a593Smuzhiyun case 1600:
1730*4882a593Smuzhiyun return DA7219_MICBIAS_1_6V;
1731*4882a593Smuzhiyun case 1800:
1732*4882a593Smuzhiyun return DA7219_MICBIAS_1_8V;
1733*4882a593Smuzhiyun case 2000:
1734*4882a593Smuzhiyun return DA7219_MICBIAS_2_0V;
1735*4882a593Smuzhiyun case 2200:
1736*4882a593Smuzhiyun return DA7219_MICBIAS_2_2V;
1737*4882a593Smuzhiyun case 2400:
1738*4882a593Smuzhiyun return DA7219_MICBIAS_2_4V;
1739*4882a593Smuzhiyun case 2600:
1740*4882a593Smuzhiyun return DA7219_MICBIAS_2_6V;
1741*4882a593Smuzhiyun default:
1742*4882a593Smuzhiyun dev_warn(dev, "Invalid micbias level");
1743*4882a593Smuzhiyun return DA7219_MICBIAS_2_2V;
1744*4882a593Smuzhiyun }
1745*4882a593Smuzhiyun }
1746*4882a593Smuzhiyun
1747*4882a593Smuzhiyun static enum da7219_mic_amp_in_sel
da7219_fw_mic_amp_in_sel(struct device * dev,const char * str)1748*4882a593Smuzhiyun da7219_fw_mic_amp_in_sel(struct device *dev, const char *str)
1749*4882a593Smuzhiyun {
1750*4882a593Smuzhiyun if (!strcmp(str, "diff")) {
1751*4882a593Smuzhiyun return DA7219_MIC_AMP_IN_SEL_DIFF;
1752*4882a593Smuzhiyun } else if (!strcmp(str, "se_p")) {
1753*4882a593Smuzhiyun return DA7219_MIC_AMP_IN_SEL_SE_P;
1754*4882a593Smuzhiyun } else if (!strcmp(str, "se_n")) {
1755*4882a593Smuzhiyun return DA7219_MIC_AMP_IN_SEL_SE_N;
1756*4882a593Smuzhiyun } else {
1757*4882a593Smuzhiyun dev_warn(dev, "Invalid mic input type selection");
1758*4882a593Smuzhiyun return DA7219_MIC_AMP_IN_SEL_DIFF;
1759*4882a593Smuzhiyun }
1760*4882a593Smuzhiyun }
1761*4882a593Smuzhiyun
da7219_fw_to_pdata(struct device * dev)1762*4882a593Smuzhiyun static struct da7219_pdata *da7219_fw_to_pdata(struct device *dev)
1763*4882a593Smuzhiyun {
1764*4882a593Smuzhiyun struct da7219_pdata *pdata;
1765*4882a593Smuzhiyun const char *of_str;
1766*4882a593Smuzhiyun u32 of_val32;
1767*4882a593Smuzhiyun
1768*4882a593Smuzhiyun pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
1769*4882a593Smuzhiyun if (!pdata)
1770*4882a593Smuzhiyun return NULL;
1771*4882a593Smuzhiyun
1772*4882a593Smuzhiyun pdata->wakeup_source = device_property_read_bool(dev, "wakeup-source");
1773*4882a593Smuzhiyun
1774*4882a593Smuzhiyun pdata->dai_clk_names[DA7219_DAI_WCLK_IDX] = "da7219-dai-wclk";
1775*4882a593Smuzhiyun pdata->dai_clk_names[DA7219_DAI_BCLK_IDX] = "da7219-dai-bclk";
1776*4882a593Smuzhiyun if (device_property_read_string_array(dev, "clock-output-names",
1777*4882a593Smuzhiyun pdata->dai_clk_names,
1778*4882a593Smuzhiyun DA7219_DAI_NUM_CLKS) < 0)
1779*4882a593Smuzhiyun dev_warn(dev, "Using default DAI clk names: %s, %s\n",
1780*4882a593Smuzhiyun pdata->dai_clk_names[DA7219_DAI_WCLK_IDX],
1781*4882a593Smuzhiyun pdata->dai_clk_names[DA7219_DAI_BCLK_IDX]);
1782*4882a593Smuzhiyun
1783*4882a593Smuzhiyun if (device_property_read_u32(dev, "dlg,micbias-lvl", &of_val32) >= 0)
1784*4882a593Smuzhiyun pdata->micbias_lvl = da7219_fw_micbias_lvl(dev, of_val32);
1785*4882a593Smuzhiyun else
1786*4882a593Smuzhiyun pdata->micbias_lvl = DA7219_MICBIAS_2_2V;
1787*4882a593Smuzhiyun
1788*4882a593Smuzhiyun if (!device_property_read_string(dev, "dlg,mic-amp-in-sel", &of_str))
1789*4882a593Smuzhiyun pdata->mic_amp_in_sel = da7219_fw_mic_amp_in_sel(dev, of_str);
1790*4882a593Smuzhiyun else
1791*4882a593Smuzhiyun pdata->mic_amp_in_sel = DA7219_MIC_AMP_IN_SEL_DIFF;
1792*4882a593Smuzhiyun
1793*4882a593Smuzhiyun return pdata;
1794*4882a593Smuzhiyun }
1795*4882a593Smuzhiyun
1796*4882a593Smuzhiyun
1797*4882a593Smuzhiyun /*
1798*4882a593Smuzhiyun * Codec driver functions
1799*4882a593Smuzhiyun */
1800*4882a593Smuzhiyun
da7219_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)1801*4882a593Smuzhiyun static int da7219_set_bias_level(struct snd_soc_component *component,
1802*4882a593Smuzhiyun enum snd_soc_bias_level level)
1803*4882a593Smuzhiyun {
1804*4882a593Smuzhiyun struct da7219_priv *da7219 = snd_soc_component_get_drvdata(component);
1805*4882a593Smuzhiyun int ret;
1806*4882a593Smuzhiyun
1807*4882a593Smuzhiyun switch (level) {
1808*4882a593Smuzhiyun case SND_SOC_BIAS_ON:
1809*4882a593Smuzhiyun break;
1810*4882a593Smuzhiyun case SND_SOC_BIAS_PREPARE:
1811*4882a593Smuzhiyun /* Enable MCLK for transition to ON state */
1812*4882a593Smuzhiyun if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_STANDBY) {
1813*4882a593Smuzhiyun if (da7219->mclk) {
1814*4882a593Smuzhiyun ret = clk_prepare_enable(da7219->mclk);
1815*4882a593Smuzhiyun if (ret) {
1816*4882a593Smuzhiyun dev_err(component->dev,
1817*4882a593Smuzhiyun "Failed to enable mclk\n");
1818*4882a593Smuzhiyun return ret;
1819*4882a593Smuzhiyun }
1820*4882a593Smuzhiyun }
1821*4882a593Smuzhiyun }
1822*4882a593Smuzhiyun
1823*4882a593Smuzhiyun break;
1824*4882a593Smuzhiyun case SND_SOC_BIAS_STANDBY:
1825*4882a593Smuzhiyun if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
1826*4882a593Smuzhiyun /* Master bias */
1827*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7219_REFERENCES,
1828*4882a593Smuzhiyun DA7219_BIAS_EN_MASK,
1829*4882a593Smuzhiyun DA7219_BIAS_EN_MASK);
1830*4882a593Smuzhiyun
1831*4882a593Smuzhiyun if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_PREPARE) {
1832*4882a593Smuzhiyun /* Remove MCLK */
1833*4882a593Smuzhiyun if (da7219->mclk)
1834*4882a593Smuzhiyun clk_disable_unprepare(da7219->mclk);
1835*4882a593Smuzhiyun }
1836*4882a593Smuzhiyun break;
1837*4882a593Smuzhiyun case SND_SOC_BIAS_OFF:
1838*4882a593Smuzhiyun /* Only disable master bias if we're not a wake-up source */
1839*4882a593Smuzhiyun if (!da7219->wakeup_source)
1840*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7219_REFERENCES,
1841*4882a593Smuzhiyun DA7219_BIAS_EN_MASK, 0);
1842*4882a593Smuzhiyun
1843*4882a593Smuzhiyun break;
1844*4882a593Smuzhiyun }
1845*4882a593Smuzhiyun
1846*4882a593Smuzhiyun return 0;
1847*4882a593Smuzhiyun }
1848*4882a593Smuzhiyun
1849*4882a593Smuzhiyun static const char *da7219_supply_names[DA7219_NUM_SUPPLIES] = {
1850*4882a593Smuzhiyun [DA7219_SUPPLY_VDD] = "VDD",
1851*4882a593Smuzhiyun [DA7219_SUPPLY_VDDMIC] = "VDDMIC",
1852*4882a593Smuzhiyun [DA7219_SUPPLY_VDDIO] = "VDDIO",
1853*4882a593Smuzhiyun };
1854*4882a593Smuzhiyun
da7219_handle_supplies(struct snd_soc_component * component,u8 * io_voltage_lvl)1855*4882a593Smuzhiyun static int da7219_handle_supplies(struct snd_soc_component *component,
1856*4882a593Smuzhiyun u8 *io_voltage_lvl)
1857*4882a593Smuzhiyun {
1858*4882a593Smuzhiyun struct da7219_priv *da7219 = snd_soc_component_get_drvdata(component);
1859*4882a593Smuzhiyun struct regulator *vddio;
1860*4882a593Smuzhiyun int i, ret;
1861*4882a593Smuzhiyun
1862*4882a593Smuzhiyun /* Get required supplies */
1863*4882a593Smuzhiyun for (i = 0; i < DA7219_NUM_SUPPLIES; ++i)
1864*4882a593Smuzhiyun da7219->supplies[i].supply = da7219_supply_names[i];
1865*4882a593Smuzhiyun
1866*4882a593Smuzhiyun ret = regulator_bulk_get(component->dev, DA7219_NUM_SUPPLIES,
1867*4882a593Smuzhiyun da7219->supplies);
1868*4882a593Smuzhiyun if (ret) {
1869*4882a593Smuzhiyun dev_err(component->dev, "Failed to get supplies");
1870*4882a593Smuzhiyun return ret;
1871*4882a593Smuzhiyun }
1872*4882a593Smuzhiyun
1873*4882a593Smuzhiyun /* Default to upper range */
1874*4882a593Smuzhiyun *io_voltage_lvl = DA7219_IO_VOLTAGE_LEVEL_2_5V_3_6V;
1875*4882a593Smuzhiyun
1876*4882a593Smuzhiyun /* Determine VDDIO voltage provided */
1877*4882a593Smuzhiyun vddio = da7219->supplies[DA7219_SUPPLY_VDDIO].consumer;
1878*4882a593Smuzhiyun ret = regulator_get_voltage(vddio);
1879*4882a593Smuzhiyun if (ret < 1200000)
1880*4882a593Smuzhiyun dev_warn(component->dev, "Invalid VDDIO voltage\n");
1881*4882a593Smuzhiyun else if (ret < 2800000)
1882*4882a593Smuzhiyun *io_voltage_lvl = DA7219_IO_VOLTAGE_LEVEL_1_2V_2_8V;
1883*4882a593Smuzhiyun
1884*4882a593Smuzhiyun /* Enable main supplies */
1885*4882a593Smuzhiyun ret = regulator_bulk_enable(DA7219_NUM_SUPPLIES, da7219->supplies);
1886*4882a593Smuzhiyun if (ret) {
1887*4882a593Smuzhiyun dev_err(component->dev, "Failed to enable supplies");
1888*4882a593Smuzhiyun regulator_bulk_free(DA7219_NUM_SUPPLIES, da7219->supplies);
1889*4882a593Smuzhiyun return ret;
1890*4882a593Smuzhiyun }
1891*4882a593Smuzhiyun
1892*4882a593Smuzhiyun return 0;
1893*4882a593Smuzhiyun }
1894*4882a593Smuzhiyun
1895*4882a593Smuzhiyun #ifdef CONFIG_COMMON_CLK
da7219_wclk_prepare(struct clk_hw * hw)1896*4882a593Smuzhiyun static int da7219_wclk_prepare(struct clk_hw *hw)
1897*4882a593Smuzhiyun {
1898*4882a593Smuzhiyun struct da7219_priv *da7219 =
1899*4882a593Smuzhiyun container_of(hw, struct da7219_priv,
1900*4882a593Smuzhiyun dai_clks_hw[DA7219_DAI_WCLK_IDX]);
1901*4882a593Smuzhiyun struct snd_soc_component *component = da7219->component;
1902*4882a593Smuzhiyun
1903*4882a593Smuzhiyun if (!da7219->master)
1904*4882a593Smuzhiyun return -EINVAL;
1905*4882a593Smuzhiyun
1906*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7219_DAI_CLK_MODE,
1907*4882a593Smuzhiyun DA7219_DAI_CLK_EN_MASK,
1908*4882a593Smuzhiyun DA7219_DAI_CLK_EN_MASK);
1909*4882a593Smuzhiyun
1910*4882a593Smuzhiyun return 0;
1911*4882a593Smuzhiyun }
1912*4882a593Smuzhiyun
da7219_wclk_unprepare(struct clk_hw * hw)1913*4882a593Smuzhiyun static void da7219_wclk_unprepare(struct clk_hw *hw)
1914*4882a593Smuzhiyun {
1915*4882a593Smuzhiyun struct da7219_priv *da7219 =
1916*4882a593Smuzhiyun container_of(hw, struct da7219_priv,
1917*4882a593Smuzhiyun dai_clks_hw[DA7219_DAI_WCLK_IDX]);
1918*4882a593Smuzhiyun struct snd_soc_component *component = da7219->component;
1919*4882a593Smuzhiyun
1920*4882a593Smuzhiyun if (!da7219->master)
1921*4882a593Smuzhiyun return;
1922*4882a593Smuzhiyun
1923*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7219_DAI_CLK_MODE,
1924*4882a593Smuzhiyun DA7219_DAI_CLK_EN_MASK, 0);
1925*4882a593Smuzhiyun }
1926*4882a593Smuzhiyun
da7219_wclk_is_prepared(struct clk_hw * hw)1927*4882a593Smuzhiyun static int da7219_wclk_is_prepared(struct clk_hw *hw)
1928*4882a593Smuzhiyun {
1929*4882a593Smuzhiyun struct da7219_priv *da7219 =
1930*4882a593Smuzhiyun container_of(hw, struct da7219_priv,
1931*4882a593Smuzhiyun dai_clks_hw[DA7219_DAI_WCLK_IDX]);
1932*4882a593Smuzhiyun struct snd_soc_component *component = da7219->component;
1933*4882a593Smuzhiyun u8 clk_reg;
1934*4882a593Smuzhiyun
1935*4882a593Smuzhiyun if (!da7219->master)
1936*4882a593Smuzhiyun return -EINVAL;
1937*4882a593Smuzhiyun
1938*4882a593Smuzhiyun clk_reg = snd_soc_component_read(component, DA7219_DAI_CLK_MODE);
1939*4882a593Smuzhiyun
1940*4882a593Smuzhiyun return !!(clk_reg & DA7219_DAI_CLK_EN_MASK);
1941*4882a593Smuzhiyun }
1942*4882a593Smuzhiyun
da7219_wclk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)1943*4882a593Smuzhiyun static unsigned long da7219_wclk_recalc_rate(struct clk_hw *hw,
1944*4882a593Smuzhiyun unsigned long parent_rate)
1945*4882a593Smuzhiyun {
1946*4882a593Smuzhiyun struct da7219_priv *da7219 =
1947*4882a593Smuzhiyun container_of(hw, struct da7219_priv,
1948*4882a593Smuzhiyun dai_clks_hw[DA7219_DAI_WCLK_IDX]);
1949*4882a593Smuzhiyun struct snd_soc_component *component = da7219->component;
1950*4882a593Smuzhiyun u8 fs = snd_soc_component_read(component, DA7219_SR);
1951*4882a593Smuzhiyun
1952*4882a593Smuzhiyun switch (fs & DA7219_SR_MASK) {
1953*4882a593Smuzhiyun case DA7219_SR_8000:
1954*4882a593Smuzhiyun return 8000;
1955*4882a593Smuzhiyun case DA7219_SR_11025:
1956*4882a593Smuzhiyun return 11025;
1957*4882a593Smuzhiyun case DA7219_SR_12000:
1958*4882a593Smuzhiyun return 12000;
1959*4882a593Smuzhiyun case DA7219_SR_16000:
1960*4882a593Smuzhiyun return 16000;
1961*4882a593Smuzhiyun case DA7219_SR_22050:
1962*4882a593Smuzhiyun return 22050;
1963*4882a593Smuzhiyun case DA7219_SR_24000:
1964*4882a593Smuzhiyun return 24000;
1965*4882a593Smuzhiyun case DA7219_SR_32000:
1966*4882a593Smuzhiyun return 32000;
1967*4882a593Smuzhiyun case DA7219_SR_44100:
1968*4882a593Smuzhiyun return 44100;
1969*4882a593Smuzhiyun case DA7219_SR_48000:
1970*4882a593Smuzhiyun return 48000;
1971*4882a593Smuzhiyun case DA7219_SR_88200:
1972*4882a593Smuzhiyun return 88200;
1973*4882a593Smuzhiyun case DA7219_SR_96000:
1974*4882a593Smuzhiyun return 96000;
1975*4882a593Smuzhiyun default:
1976*4882a593Smuzhiyun return 0;
1977*4882a593Smuzhiyun }
1978*4882a593Smuzhiyun }
1979*4882a593Smuzhiyun
da7219_wclk_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * parent_rate)1980*4882a593Smuzhiyun static long da7219_wclk_round_rate(struct clk_hw *hw, unsigned long rate,
1981*4882a593Smuzhiyun unsigned long *parent_rate)
1982*4882a593Smuzhiyun {
1983*4882a593Smuzhiyun struct da7219_priv *da7219 =
1984*4882a593Smuzhiyun container_of(hw, struct da7219_priv,
1985*4882a593Smuzhiyun dai_clks_hw[DA7219_DAI_WCLK_IDX]);
1986*4882a593Smuzhiyun
1987*4882a593Smuzhiyun if (!da7219->master)
1988*4882a593Smuzhiyun return -EINVAL;
1989*4882a593Smuzhiyun
1990*4882a593Smuzhiyun if (rate < 11025)
1991*4882a593Smuzhiyun return 8000;
1992*4882a593Smuzhiyun else if (rate < 12000)
1993*4882a593Smuzhiyun return 11025;
1994*4882a593Smuzhiyun else if (rate < 16000)
1995*4882a593Smuzhiyun return 12000;
1996*4882a593Smuzhiyun else if (rate < 22050)
1997*4882a593Smuzhiyun return 16000;
1998*4882a593Smuzhiyun else if (rate < 24000)
1999*4882a593Smuzhiyun return 22050;
2000*4882a593Smuzhiyun else if (rate < 32000)
2001*4882a593Smuzhiyun return 24000;
2002*4882a593Smuzhiyun else if (rate < 44100)
2003*4882a593Smuzhiyun return 32000;
2004*4882a593Smuzhiyun else if (rate < 48000)
2005*4882a593Smuzhiyun return 44100;
2006*4882a593Smuzhiyun else if (rate < 88200)
2007*4882a593Smuzhiyun return 48000;
2008*4882a593Smuzhiyun else if (rate < 96000)
2009*4882a593Smuzhiyun return 88200;
2010*4882a593Smuzhiyun else
2011*4882a593Smuzhiyun return 96000;
2012*4882a593Smuzhiyun }
2013*4882a593Smuzhiyun
da7219_wclk_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)2014*4882a593Smuzhiyun static int da7219_wclk_set_rate(struct clk_hw *hw, unsigned long rate,
2015*4882a593Smuzhiyun unsigned long parent_rate)
2016*4882a593Smuzhiyun {
2017*4882a593Smuzhiyun struct da7219_priv *da7219 =
2018*4882a593Smuzhiyun container_of(hw, struct da7219_priv,
2019*4882a593Smuzhiyun dai_clks_hw[DA7219_DAI_WCLK_IDX]);
2020*4882a593Smuzhiyun struct snd_soc_component *component = da7219->component;
2021*4882a593Smuzhiyun
2022*4882a593Smuzhiyun if (!da7219->master)
2023*4882a593Smuzhiyun return -EINVAL;
2024*4882a593Smuzhiyun
2025*4882a593Smuzhiyun return da7219_set_sr(component, rate);
2026*4882a593Smuzhiyun }
2027*4882a593Smuzhiyun
da7219_bclk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)2028*4882a593Smuzhiyun static unsigned long da7219_bclk_recalc_rate(struct clk_hw *hw,
2029*4882a593Smuzhiyun unsigned long parent_rate)
2030*4882a593Smuzhiyun {
2031*4882a593Smuzhiyun struct da7219_priv *da7219 =
2032*4882a593Smuzhiyun container_of(hw, struct da7219_priv,
2033*4882a593Smuzhiyun dai_clks_hw[DA7219_DAI_BCLK_IDX]);
2034*4882a593Smuzhiyun struct snd_soc_component *component = da7219->component;
2035*4882a593Smuzhiyun u8 bclks_per_wclk = snd_soc_component_read(component,
2036*4882a593Smuzhiyun DA7219_DAI_CLK_MODE);
2037*4882a593Smuzhiyun
2038*4882a593Smuzhiyun switch (bclks_per_wclk & DA7219_DAI_BCLKS_PER_WCLK_MASK) {
2039*4882a593Smuzhiyun case DA7219_DAI_BCLKS_PER_WCLK_32:
2040*4882a593Smuzhiyun return parent_rate * 32;
2041*4882a593Smuzhiyun case DA7219_DAI_BCLKS_PER_WCLK_64:
2042*4882a593Smuzhiyun return parent_rate * 64;
2043*4882a593Smuzhiyun case DA7219_DAI_BCLKS_PER_WCLK_128:
2044*4882a593Smuzhiyun return parent_rate * 128;
2045*4882a593Smuzhiyun case DA7219_DAI_BCLKS_PER_WCLK_256:
2046*4882a593Smuzhiyun return parent_rate * 256;
2047*4882a593Smuzhiyun default:
2048*4882a593Smuzhiyun return 0;
2049*4882a593Smuzhiyun }
2050*4882a593Smuzhiyun }
2051*4882a593Smuzhiyun
da7219_bclk_get_factor(unsigned long rate,unsigned long parent_rate)2052*4882a593Smuzhiyun static unsigned long da7219_bclk_get_factor(unsigned long rate,
2053*4882a593Smuzhiyun unsigned long parent_rate)
2054*4882a593Smuzhiyun {
2055*4882a593Smuzhiyun unsigned long factor;
2056*4882a593Smuzhiyun
2057*4882a593Smuzhiyun factor = rate / parent_rate;
2058*4882a593Smuzhiyun if (factor < 64)
2059*4882a593Smuzhiyun return 32;
2060*4882a593Smuzhiyun else if (factor < 128)
2061*4882a593Smuzhiyun return 64;
2062*4882a593Smuzhiyun else if (factor < 256)
2063*4882a593Smuzhiyun return 128;
2064*4882a593Smuzhiyun else
2065*4882a593Smuzhiyun return 256;
2066*4882a593Smuzhiyun }
2067*4882a593Smuzhiyun
da7219_bclk_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * parent_rate)2068*4882a593Smuzhiyun static long da7219_bclk_round_rate(struct clk_hw *hw, unsigned long rate,
2069*4882a593Smuzhiyun unsigned long *parent_rate)
2070*4882a593Smuzhiyun {
2071*4882a593Smuzhiyun struct da7219_priv *da7219 =
2072*4882a593Smuzhiyun container_of(hw, struct da7219_priv,
2073*4882a593Smuzhiyun dai_clks_hw[DA7219_DAI_BCLK_IDX]);
2074*4882a593Smuzhiyun unsigned long factor;
2075*4882a593Smuzhiyun
2076*4882a593Smuzhiyun if (!*parent_rate || !da7219->master)
2077*4882a593Smuzhiyun return -EINVAL;
2078*4882a593Smuzhiyun
2079*4882a593Smuzhiyun /*
2080*4882a593Smuzhiyun * We don't allow changing the parent rate as some BCLK rates can be
2081*4882a593Smuzhiyun * derived from multiple parent WCLK rates (BCLK rates are set as a
2082*4882a593Smuzhiyun * multiplier of WCLK in HW). We just do some rounding down based on the
2083*4882a593Smuzhiyun * parent WCLK rate set and find the appropriate multiplier of BCLK to
2084*4882a593Smuzhiyun * get the rounded down BCLK value.
2085*4882a593Smuzhiyun */
2086*4882a593Smuzhiyun factor = da7219_bclk_get_factor(rate, *parent_rate);
2087*4882a593Smuzhiyun
2088*4882a593Smuzhiyun return *parent_rate * factor;
2089*4882a593Smuzhiyun }
2090*4882a593Smuzhiyun
da7219_bclk_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)2091*4882a593Smuzhiyun static int da7219_bclk_set_rate(struct clk_hw *hw, unsigned long rate,
2092*4882a593Smuzhiyun unsigned long parent_rate)
2093*4882a593Smuzhiyun {
2094*4882a593Smuzhiyun struct da7219_priv *da7219 =
2095*4882a593Smuzhiyun container_of(hw, struct da7219_priv,
2096*4882a593Smuzhiyun dai_clks_hw[DA7219_DAI_BCLK_IDX]);
2097*4882a593Smuzhiyun struct snd_soc_component *component = da7219->component;
2098*4882a593Smuzhiyun unsigned long factor;
2099*4882a593Smuzhiyun
2100*4882a593Smuzhiyun if (!da7219->master)
2101*4882a593Smuzhiyun return -EINVAL;
2102*4882a593Smuzhiyun
2103*4882a593Smuzhiyun factor = da7219_bclk_get_factor(rate, parent_rate);
2104*4882a593Smuzhiyun
2105*4882a593Smuzhiyun return da7219_set_bclks_per_wclk(component, factor);
2106*4882a593Smuzhiyun }
2107*4882a593Smuzhiyun
2108*4882a593Smuzhiyun static const struct clk_ops da7219_dai_clk_ops[DA7219_DAI_NUM_CLKS] = {
2109*4882a593Smuzhiyun [DA7219_DAI_WCLK_IDX] = {
2110*4882a593Smuzhiyun .prepare = da7219_wclk_prepare,
2111*4882a593Smuzhiyun .unprepare = da7219_wclk_unprepare,
2112*4882a593Smuzhiyun .is_prepared = da7219_wclk_is_prepared,
2113*4882a593Smuzhiyun .recalc_rate = da7219_wclk_recalc_rate,
2114*4882a593Smuzhiyun .round_rate = da7219_wclk_round_rate,
2115*4882a593Smuzhiyun .set_rate = da7219_wclk_set_rate,
2116*4882a593Smuzhiyun },
2117*4882a593Smuzhiyun [DA7219_DAI_BCLK_IDX] = {
2118*4882a593Smuzhiyun .recalc_rate = da7219_bclk_recalc_rate,
2119*4882a593Smuzhiyun .round_rate = da7219_bclk_round_rate,
2120*4882a593Smuzhiyun .set_rate = da7219_bclk_set_rate,
2121*4882a593Smuzhiyun },
2122*4882a593Smuzhiyun };
2123*4882a593Smuzhiyun
da7219_register_dai_clks(struct snd_soc_component * component)2124*4882a593Smuzhiyun static int da7219_register_dai_clks(struct snd_soc_component *component)
2125*4882a593Smuzhiyun {
2126*4882a593Smuzhiyun struct device *dev = component->dev;
2127*4882a593Smuzhiyun struct device_node *np = dev->of_node;
2128*4882a593Smuzhiyun struct da7219_priv *da7219 = snd_soc_component_get_drvdata(component);
2129*4882a593Smuzhiyun struct da7219_pdata *pdata = da7219->pdata;
2130*4882a593Smuzhiyun const char *parent_name;
2131*4882a593Smuzhiyun struct clk_hw_onecell_data *clk_data;
2132*4882a593Smuzhiyun int i, ret;
2133*4882a593Smuzhiyun
2134*4882a593Smuzhiyun /* For DT platforms allocate onecell data for clock registration */
2135*4882a593Smuzhiyun if (np) {
2136*4882a593Smuzhiyun clk_data = kzalloc(struct_size(clk_data, hws, DA7219_DAI_NUM_CLKS),
2137*4882a593Smuzhiyun GFP_KERNEL);
2138*4882a593Smuzhiyun if (!clk_data)
2139*4882a593Smuzhiyun return -ENOMEM;
2140*4882a593Smuzhiyun
2141*4882a593Smuzhiyun clk_data->num = DA7219_DAI_NUM_CLKS;
2142*4882a593Smuzhiyun da7219->clk_hw_data = clk_data;
2143*4882a593Smuzhiyun }
2144*4882a593Smuzhiyun
2145*4882a593Smuzhiyun for (i = 0; i < DA7219_DAI_NUM_CLKS; ++i) {
2146*4882a593Smuzhiyun struct clk_init_data init = {};
2147*4882a593Smuzhiyun struct clk_lookup *dai_clk_lookup;
2148*4882a593Smuzhiyun struct clk_hw *dai_clk_hw = &da7219->dai_clks_hw[i];
2149*4882a593Smuzhiyun
2150*4882a593Smuzhiyun switch (i) {
2151*4882a593Smuzhiyun case DA7219_DAI_WCLK_IDX:
2152*4882a593Smuzhiyun /*
2153*4882a593Smuzhiyun * If we can, make MCLK the parent of WCLK to ensure
2154*4882a593Smuzhiyun * it's enabled as required.
2155*4882a593Smuzhiyun */
2156*4882a593Smuzhiyun if (da7219->mclk) {
2157*4882a593Smuzhiyun parent_name = __clk_get_name(da7219->mclk);
2158*4882a593Smuzhiyun init.parent_names = &parent_name;
2159*4882a593Smuzhiyun init.num_parents = 1;
2160*4882a593Smuzhiyun } else {
2161*4882a593Smuzhiyun init.parent_names = NULL;
2162*4882a593Smuzhiyun init.num_parents = 0;
2163*4882a593Smuzhiyun }
2164*4882a593Smuzhiyun break;
2165*4882a593Smuzhiyun case DA7219_DAI_BCLK_IDX:
2166*4882a593Smuzhiyun /* Make WCLK the parent of BCLK */
2167*4882a593Smuzhiyun parent_name = __clk_get_name(da7219->dai_clks[DA7219_DAI_WCLK_IDX]);
2168*4882a593Smuzhiyun init.parent_names = &parent_name;
2169*4882a593Smuzhiyun init.num_parents = 1;
2170*4882a593Smuzhiyun break;
2171*4882a593Smuzhiyun default:
2172*4882a593Smuzhiyun dev_err(dev, "Invalid clock index\n");
2173*4882a593Smuzhiyun ret = -EINVAL;
2174*4882a593Smuzhiyun goto err;
2175*4882a593Smuzhiyun }
2176*4882a593Smuzhiyun
2177*4882a593Smuzhiyun init.name = pdata->dai_clk_names[i];
2178*4882a593Smuzhiyun init.ops = &da7219_dai_clk_ops[i];
2179*4882a593Smuzhiyun init.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_GATE;
2180*4882a593Smuzhiyun dai_clk_hw->init = &init;
2181*4882a593Smuzhiyun
2182*4882a593Smuzhiyun ret = clk_hw_register(dev, dai_clk_hw);
2183*4882a593Smuzhiyun if (ret) {
2184*4882a593Smuzhiyun dev_warn(dev, "Failed to register %s: %d\n", init.name,
2185*4882a593Smuzhiyun ret);
2186*4882a593Smuzhiyun goto err;
2187*4882a593Smuzhiyun }
2188*4882a593Smuzhiyun da7219->dai_clks[i] = dai_clk_hw->clk;
2189*4882a593Smuzhiyun
2190*4882a593Smuzhiyun /* For DT setup onecell data, otherwise create lookup */
2191*4882a593Smuzhiyun if (np) {
2192*4882a593Smuzhiyun da7219->clk_hw_data->hws[i] = dai_clk_hw;
2193*4882a593Smuzhiyun } else {
2194*4882a593Smuzhiyun dai_clk_lookup = clkdev_hw_create(dai_clk_hw, init.name,
2195*4882a593Smuzhiyun "%s", dev_name(dev));
2196*4882a593Smuzhiyun if (!dai_clk_lookup) {
2197*4882a593Smuzhiyun clk_hw_unregister(dai_clk_hw);
2198*4882a593Smuzhiyun ret = -ENOMEM;
2199*4882a593Smuzhiyun goto err;
2200*4882a593Smuzhiyun } else {
2201*4882a593Smuzhiyun da7219->dai_clks_lookup[i] = dai_clk_lookup;
2202*4882a593Smuzhiyun }
2203*4882a593Smuzhiyun }
2204*4882a593Smuzhiyun }
2205*4882a593Smuzhiyun
2206*4882a593Smuzhiyun /* If we're using DT, then register as provider accordingly */
2207*4882a593Smuzhiyun if (np) {
2208*4882a593Smuzhiyun ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
2209*4882a593Smuzhiyun da7219->clk_hw_data);
2210*4882a593Smuzhiyun if (ret) {
2211*4882a593Smuzhiyun dev_err(dev, "Failed to register clock provider\n");
2212*4882a593Smuzhiyun goto err;
2213*4882a593Smuzhiyun }
2214*4882a593Smuzhiyun }
2215*4882a593Smuzhiyun
2216*4882a593Smuzhiyun return 0;
2217*4882a593Smuzhiyun
2218*4882a593Smuzhiyun err:
2219*4882a593Smuzhiyun while (--i >= 0) {
2220*4882a593Smuzhiyun if (da7219->dai_clks_lookup[i])
2221*4882a593Smuzhiyun clkdev_drop(da7219->dai_clks_lookup[i]);
2222*4882a593Smuzhiyun
2223*4882a593Smuzhiyun clk_hw_unregister(&da7219->dai_clks_hw[i]);
2224*4882a593Smuzhiyun }
2225*4882a593Smuzhiyun
2226*4882a593Smuzhiyun if (np)
2227*4882a593Smuzhiyun kfree(da7219->clk_hw_data);
2228*4882a593Smuzhiyun
2229*4882a593Smuzhiyun return ret;
2230*4882a593Smuzhiyun }
2231*4882a593Smuzhiyun
da7219_free_dai_clks(struct snd_soc_component * component)2232*4882a593Smuzhiyun static void da7219_free_dai_clks(struct snd_soc_component *component)
2233*4882a593Smuzhiyun {
2234*4882a593Smuzhiyun struct da7219_priv *da7219 = snd_soc_component_get_drvdata(component);
2235*4882a593Smuzhiyun struct device_node *np = component->dev->of_node;
2236*4882a593Smuzhiyun int i;
2237*4882a593Smuzhiyun
2238*4882a593Smuzhiyun if (np)
2239*4882a593Smuzhiyun of_clk_del_provider(np);
2240*4882a593Smuzhiyun
2241*4882a593Smuzhiyun for (i = DA7219_DAI_NUM_CLKS - 1; i >= 0; --i) {
2242*4882a593Smuzhiyun if (da7219->dai_clks_lookup[i])
2243*4882a593Smuzhiyun clkdev_drop(da7219->dai_clks_lookup[i]);
2244*4882a593Smuzhiyun
2245*4882a593Smuzhiyun clk_hw_unregister(&da7219->dai_clks_hw[i]);
2246*4882a593Smuzhiyun }
2247*4882a593Smuzhiyun
2248*4882a593Smuzhiyun if (np)
2249*4882a593Smuzhiyun kfree(da7219->clk_hw_data);
2250*4882a593Smuzhiyun }
2251*4882a593Smuzhiyun #else
da7219_register_dai_clks(struct snd_soc_component * component)2252*4882a593Smuzhiyun static inline int da7219_register_dai_clks(struct snd_soc_component *component)
2253*4882a593Smuzhiyun {
2254*4882a593Smuzhiyun return 0;
2255*4882a593Smuzhiyun }
2256*4882a593Smuzhiyun
da7219_free_dai_clks(struct snd_soc_component * component)2257*4882a593Smuzhiyun static void da7219_free_dai_clks(struct snd_soc_component *component) {}
2258*4882a593Smuzhiyun #endif /* CONFIG_COMMON_CLK */
2259*4882a593Smuzhiyun
da7219_handle_pdata(struct snd_soc_component * component)2260*4882a593Smuzhiyun static void da7219_handle_pdata(struct snd_soc_component *component)
2261*4882a593Smuzhiyun {
2262*4882a593Smuzhiyun struct da7219_priv *da7219 = snd_soc_component_get_drvdata(component);
2263*4882a593Smuzhiyun struct da7219_pdata *pdata = da7219->pdata;
2264*4882a593Smuzhiyun
2265*4882a593Smuzhiyun if (pdata) {
2266*4882a593Smuzhiyun u8 micbias_lvl = 0;
2267*4882a593Smuzhiyun
2268*4882a593Smuzhiyun da7219->wakeup_source = pdata->wakeup_source;
2269*4882a593Smuzhiyun
2270*4882a593Smuzhiyun /* Mic Bias voltages */
2271*4882a593Smuzhiyun switch (pdata->micbias_lvl) {
2272*4882a593Smuzhiyun case DA7219_MICBIAS_1_6V:
2273*4882a593Smuzhiyun case DA7219_MICBIAS_1_8V:
2274*4882a593Smuzhiyun case DA7219_MICBIAS_2_0V:
2275*4882a593Smuzhiyun case DA7219_MICBIAS_2_2V:
2276*4882a593Smuzhiyun case DA7219_MICBIAS_2_4V:
2277*4882a593Smuzhiyun case DA7219_MICBIAS_2_6V:
2278*4882a593Smuzhiyun micbias_lvl |= (pdata->micbias_lvl <<
2279*4882a593Smuzhiyun DA7219_MICBIAS1_LEVEL_SHIFT);
2280*4882a593Smuzhiyun break;
2281*4882a593Smuzhiyun }
2282*4882a593Smuzhiyun
2283*4882a593Smuzhiyun snd_soc_component_write(component, DA7219_MICBIAS_CTRL, micbias_lvl);
2284*4882a593Smuzhiyun
2285*4882a593Smuzhiyun /*
2286*4882a593Smuzhiyun * Calculate delay required to compensate for DC offset in
2287*4882a593Smuzhiyun * Mic PGA, based on Mic Bias voltage.
2288*4882a593Smuzhiyun */
2289*4882a593Smuzhiyun da7219->mic_pga_delay = DA7219_MIC_PGA_BASE_DELAY +
2290*4882a593Smuzhiyun (pdata->micbias_lvl *
2291*4882a593Smuzhiyun DA7219_MIC_PGA_OFFSET_DELAY);
2292*4882a593Smuzhiyun
2293*4882a593Smuzhiyun /* Mic */
2294*4882a593Smuzhiyun switch (pdata->mic_amp_in_sel) {
2295*4882a593Smuzhiyun case DA7219_MIC_AMP_IN_SEL_DIFF:
2296*4882a593Smuzhiyun case DA7219_MIC_AMP_IN_SEL_SE_P:
2297*4882a593Smuzhiyun case DA7219_MIC_AMP_IN_SEL_SE_N:
2298*4882a593Smuzhiyun snd_soc_component_write(component, DA7219_MIC_1_SELECT,
2299*4882a593Smuzhiyun pdata->mic_amp_in_sel);
2300*4882a593Smuzhiyun break;
2301*4882a593Smuzhiyun }
2302*4882a593Smuzhiyun }
2303*4882a593Smuzhiyun }
2304*4882a593Smuzhiyun
2305*4882a593Smuzhiyun
2306*4882a593Smuzhiyun /*
2307*4882a593Smuzhiyun * Regmap configs
2308*4882a593Smuzhiyun */
2309*4882a593Smuzhiyun
2310*4882a593Smuzhiyun static struct reg_default da7219_reg_defaults[] = {
2311*4882a593Smuzhiyun { DA7219_MIC_1_SELECT, 0x00 },
2312*4882a593Smuzhiyun { DA7219_CIF_TIMEOUT_CTRL, 0x01 },
2313*4882a593Smuzhiyun { DA7219_SR_24_48, 0x00 },
2314*4882a593Smuzhiyun { DA7219_SR, 0x0A },
2315*4882a593Smuzhiyun { DA7219_CIF_I2C_ADDR_CFG, 0x02 },
2316*4882a593Smuzhiyun { DA7219_PLL_CTRL, 0x10 },
2317*4882a593Smuzhiyun { DA7219_PLL_FRAC_TOP, 0x00 },
2318*4882a593Smuzhiyun { DA7219_PLL_FRAC_BOT, 0x00 },
2319*4882a593Smuzhiyun { DA7219_PLL_INTEGER, 0x20 },
2320*4882a593Smuzhiyun { DA7219_DIG_ROUTING_DAI, 0x10 },
2321*4882a593Smuzhiyun { DA7219_DAI_CLK_MODE, 0x01 },
2322*4882a593Smuzhiyun { DA7219_DAI_CTRL, 0x28 },
2323*4882a593Smuzhiyun { DA7219_DAI_TDM_CTRL, 0x40 },
2324*4882a593Smuzhiyun { DA7219_DIG_ROUTING_DAC, 0x32 },
2325*4882a593Smuzhiyun { DA7219_DAI_OFFSET_LOWER, 0x00 },
2326*4882a593Smuzhiyun { DA7219_DAI_OFFSET_UPPER, 0x00 },
2327*4882a593Smuzhiyun { DA7219_REFERENCES, 0x08 },
2328*4882a593Smuzhiyun { DA7219_MIXIN_L_SELECT, 0x00 },
2329*4882a593Smuzhiyun { DA7219_MIXIN_L_GAIN, 0x03 },
2330*4882a593Smuzhiyun { DA7219_ADC_L_GAIN, 0x6F },
2331*4882a593Smuzhiyun { DA7219_ADC_FILTERS1, 0x80 },
2332*4882a593Smuzhiyun { DA7219_MIC_1_GAIN, 0x01 },
2333*4882a593Smuzhiyun { DA7219_SIDETONE_CTRL, 0x40 },
2334*4882a593Smuzhiyun { DA7219_SIDETONE_GAIN, 0x0E },
2335*4882a593Smuzhiyun { DA7219_DROUTING_ST_OUTFILT_1L, 0x01 },
2336*4882a593Smuzhiyun { DA7219_DROUTING_ST_OUTFILT_1R, 0x02 },
2337*4882a593Smuzhiyun { DA7219_DAC_FILTERS5, 0x00 },
2338*4882a593Smuzhiyun { DA7219_DAC_FILTERS2, 0x88 },
2339*4882a593Smuzhiyun { DA7219_DAC_FILTERS3, 0x88 },
2340*4882a593Smuzhiyun { DA7219_DAC_FILTERS4, 0x08 },
2341*4882a593Smuzhiyun { DA7219_DAC_FILTERS1, 0x80 },
2342*4882a593Smuzhiyun { DA7219_DAC_L_GAIN, 0x6F },
2343*4882a593Smuzhiyun { DA7219_DAC_R_GAIN, 0x6F },
2344*4882a593Smuzhiyun { DA7219_CP_CTRL, 0x20 },
2345*4882a593Smuzhiyun { DA7219_HP_L_GAIN, 0x39 },
2346*4882a593Smuzhiyun { DA7219_HP_R_GAIN, 0x39 },
2347*4882a593Smuzhiyun { DA7219_MIXOUT_L_SELECT, 0x00 },
2348*4882a593Smuzhiyun { DA7219_MIXOUT_R_SELECT, 0x00 },
2349*4882a593Smuzhiyun { DA7219_MICBIAS_CTRL, 0x03 },
2350*4882a593Smuzhiyun { DA7219_MIC_1_CTRL, 0x40 },
2351*4882a593Smuzhiyun { DA7219_MIXIN_L_CTRL, 0x40 },
2352*4882a593Smuzhiyun { DA7219_ADC_L_CTRL, 0x40 },
2353*4882a593Smuzhiyun { DA7219_DAC_L_CTRL, 0x40 },
2354*4882a593Smuzhiyun { DA7219_DAC_R_CTRL, 0x40 },
2355*4882a593Smuzhiyun { DA7219_HP_L_CTRL, 0x40 },
2356*4882a593Smuzhiyun { DA7219_HP_R_CTRL, 0x40 },
2357*4882a593Smuzhiyun { DA7219_MIXOUT_L_CTRL, 0x10 },
2358*4882a593Smuzhiyun { DA7219_MIXOUT_R_CTRL, 0x10 },
2359*4882a593Smuzhiyun { DA7219_CHIP_ID1, 0x23 },
2360*4882a593Smuzhiyun { DA7219_CHIP_ID2, 0x93 },
2361*4882a593Smuzhiyun { DA7219_IO_CTRL, 0x00 },
2362*4882a593Smuzhiyun { DA7219_GAIN_RAMP_CTRL, 0x00 },
2363*4882a593Smuzhiyun { DA7219_PC_COUNT, 0x02 },
2364*4882a593Smuzhiyun { DA7219_CP_VOL_THRESHOLD1, 0x0E },
2365*4882a593Smuzhiyun { DA7219_DIG_CTRL, 0x00 },
2366*4882a593Smuzhiyun { DA7219_ALC_CTRL2, 0x00 },
2367*4882a593Smuzhiyun { DA7219_ALC_CTRL3, 0x00 },
2368*4882a593Smuzhiyun { DA7219_ALC_NOISE, 0x3F },
2369*4882a593Smuzhiyun { DA7219_ALC_TARGET_MIN, 0x3F },
2370*4882a593Smuzhiyun { DA7219_ALC_TARGET_MAX, 0x00 },
2371*4882a593Smuzhiyun { DA7219_ALC_GAIN_LIMITS, 0xFF },
2372*4882a593Smuzhiyun { DA7219_ALC_ANA_GAIN_LIMITS, 0x71 },
2373*4882a593Smuzhiyun { DA7219_ALC_ANTICLIP_CTRL, 0x00 },
2374*4882a593Smuzhiyun { DA7219_ALC_ANTICLIP_LEVEL, 0x00 },
2375*4882a593Smuzhiyun { DA7219_DAC_NG_SETUP_TIME, 0x00 },
2376*4882a593Smuzhiyun { DA7219_DAC_NG_OFF_THRESH, 0x00 },
2377*4882a593Smuzhiyun { DA7219_DAC_NG_ON_THRESH, 0x00 },
2378*4882a593Smuzhiyun { DA7219_DAC_NG_CTRL, 0x00 },
2379*4882a593Smuzhiyun { DA7219_TONE_GEN_CFG1, 0x00 },
2380*4882a593Smuzhiyun { DA7219_TONE_GEN_CFG2, 0x00 },
2381*4882a593Smuzhiyun { DA7219_TONE_GEN_CYCLES, 0x00 },
2382*4882a593Smuzhiyun { DA7219_TONE_GEN_FREQ1_L, 0x55 },
2383*4882a593Smuzhiyun { DA7219_TONE_GEN_FREQ1_U, 0x15 },
2384*4882a593Smuzhiyun { DA7219_TONE_GEN_FREQ2_L, 0x00 },
2385*4882a593Smuzhiyun { DA7219_TONE_GEN_FREQ2_U, 0x40 },
2386*4882a593Smuzhiyun { DA7219_TONE_GEN_ON_PER, 0x02 },
2387*4882a593Smuzhiyun { DA7219_TONE_GEN_OFF_PER, 0x01 },
2388*4882a593Smuzhiyun { DA7219_ACCDET_IRQ_MASK_A, 0x00 },
2389*4882a593Smuzhiyun { DA7219_ACCDET_IRQ_MASK_B, 0x00 },
2390*4882a593Smuzhiyun { DA7219_ACCDET_CONFIG_1, 0xD6 },
2391*4882a593Smuzhiyun { DA7219_ACCDET_CONFIG_2, 0x34 },
2392*4882a593Smuzhiyun { DA7219_ACCDET_CONFIG_3, 0x0A },
2393*4882a593Smuzhiyun { DA7219_ACCDET_CONFIG_4, 0x16 },
2394*4882a593Smuzhiyun { DA7219_ACCDET_CONFIG_5, 0x21 },
2395*4882a593Smuzhiyun { DA7219_ACCDET_CONFIG_6, 0x3E },
2396*4882a593Smuzhiyun { DA7219_ACCDET_CONFIG_7, 0x01 },
2397*4882a593Smuzhiyun { DA7219_SYSTEM_ACTIVE, 0x00 },
2398*4882a593Smuzhiyun };
2399*4882a593Smuzhiyun
da7219_volatile_register(struct device * dev,unsigned int reg)2400*4882a593Smuzhiyun static bool da7219_volatile_register(struct device *dev, unsigned int reg)
2401*4882a593Smuzhiyun {
2402*4882a593Smuzhiyun switch (reg) {
2403*4882a593Smuzhiyun case DA7219_MIC_1_GAIN_STATUS:
2404*4882a593Smuzhiyun case DA7219_MIXIN_L_GAIN_STATUS:
2405*4882a593Smuzhiyun case DA7219_ADC_L_GAIN_STATUS:
2406*4882a593Smuzhiyun case DA7219_DAC_L_GAIN_STATUS:
2407*4882a593Smuzhiyun case DA7219_DAC_R_GAIN_STATUS:
2408*4882a593Smuzhiyun case DA7219_HP_L_GAIN_STATUS:
2409*4882a593Smuzhiyun case DA7219_HP_R_GAIN_STATUS:
2410*4882a593Smuzhiyun case DA7219_CIF_CTRL:
2411*4882a593Smuzhiyun case DA7219_PLL_SRM_STS:
2412*4882a593Smuzhiyun case DA7219_ALC_CTRL1:
2413*4882a593Smuzhiyun case DA7219_SYSTEM_MODES_INPUT:
2414*4882a593Smuzhiyun case DA7219_SYSTEM_MODES_OUTPUT:
2415*4882a593Smuzhiyun case DA7219_ALC_OFFSET_AUTO_M_L:
2416*4882a593Smuzhiyun case DA7219_ALC_OFFSET_AUTO_U_L:
2417*4882a593Smuzhiyun case DA7219_TONE_GEN_CFG1:
2418*4882a593Smuzhiyun case DA7219_ACCDET_STATUS_A:
2419*4882a593Smuzhiyun case DA7219_ACCDET_STATUS_B:
2420*4882a593Smuzhiyun case DA7219_ACCDET_IRQ_EVENT_A:
2421*4882a593Smuzhiyun case DA7219_ACCDET_IRQ_EVENT_B:
2422*4882a593Smuzhiyun case DA7219_ACCDET_CONFIG_8:
2423*4882a593Smuzhiyun case DA7219_SYSTEM_STATUS:
2424*4882a593Smuzhiyun return true;
2425*4882a593Smuzhiyun default:
2426*4882a593Smuzhiyun return false;
2427*4882a593Smuzhiyun }
2428*4882a593Smuzhiyun }
2429*4882a593Smuzhiyun
2430*4882a593Smuzhiyun static const struct regmap_config da7219_regmap_config = {
2431*4882a593Smuzhiyun .reg_bits = 8,
2432*4882a593Smuzhiyun .val_bits = 8,
2433*4882a593Smuzhiyun
2434*4882a593Smuzhiyun .max_register = DA7219_SYSTEM_ACTIVE,
2435*4882a593Smuzhiyun .reg_defaults = da7219_reg_defaults,
2436*4882a593Smuzhiyun .num_reg_defaults = ARRAY_SIZE(da7219_reg_defaults),
2437*4882a593Smuzhiyun .volatile_reg = da7219_volatile_register,
2438*4882a593Smuzhiyun .cache_type = REGCACHE_RBTREE,
2439*4882a593Smuzhiyun };
2440*4882a593Smuzhiyun
2441*4882a593Smuzhiyun static struct reg_sequence da7219_rev_aa_patch[] = {
2442*4882a593Smuzhiyun { DA7219_REFERENCES, 0x08 },
2443*4882a593Smuzhiyun };
2444*4882a593Smuzhiyun
da7219_probe(struct snd_soc_component * component)2445*4882a593Smuzhiyun static int da7219_probe(struct snd_soc_component *component)
2446*4882a593Smuzhiyun {
2447*4882a593Smuzhiyun struct da7219_priv *da7219 = snd_soc_component_get_drvdata(component);
2448*4882a593Smuzhiyun unsigned int system_active, system_status, rev;
2449*4882a593Smuzhiyun u8 io_voltage_lvl;
2450*4882a593Smuzhiyun int i, ret;
2451*4882a593Smuzhiyun
2452*4882a593Smuzhiyun da7219->component = component;
2453*4882a593Smuzhiyun mutex_init(&da7219->ctrl_lock);
2454*4882a593Smuzhiyun mutex_init(&da7219->pll_lock);
2455*4882a593Smuzhiyun
2456*4882a593Smuzhiyun /* Regulator configuration */
2457*4882a593Smuzhiyun ret = da7219_handle_supplies(component, &io_voltage_lvl);
2458*4882a593Smuzhiyun if (ret)
2459*4882a593Smuzhiyun return ret;
2460*4882a593Smuzhiyun
2461*4882a593Smuzhiyun regcache_cache_bypass(da7219->regmap, true);
2462*4882a593Smuzhiyun
2463*4882a593Smuzhiyun /* Disable audio paths if still active from previous start */
2464*4882a593Smuzhiyun regmap_read(da7219->regmap, DA7219_SYSTEM_ACTIVE, &system_active);
2465*4882a593Smuzhiyun if (system_active) {
2466*4882a593Smuzhiyun regmap_write(da7219->regmap, DA7219_GAIN_RAMP_CTRL,
2467*4882a593Smuzhiyun DA7219_GAIN_RAMP_RATE_NOMINAL);
2468*4882a593Smuzhiyun regmap_write(da7219->regmap, DA7219_SYSTEM_MODES_INPUT, 0x00);
2469*4882a593Smuzhiyun regmap_write(da7219->regmap, DA7219_SYSTEM_MODES_OUTPUT, 0x01);
2470*4882a593Smuzhiyun
2471*4882a593Smuzhiyun for (i = 0; i < DA7219_SYS_STAT_CHECK_RETRIES; ++i) {
2472*4882a593Smuzhiyun regmap_read(da7219->regmap, DA7219_SYSTEM_STATUS,
2473*4882a593Smuzhiyun &system_status);
2474*4882a593Smuzhiyun if (!system_status)
2475*4882a593Smuzhiyun break;
2476*4882a593Smuzhiyun
2477*4882a593Smuzhiyun msleep(DA7219_SYS_STAT_CHECK_DELAY);
2478*4882a593Smuzhiyun }
2479*4882a593Smuzhiyun }
2480*4882a593Smuzhiyun
2481*4882a593Smuzhiyun /* Soft reset component */
2482*4882a593Smuzhiyun regmap_write_bits(da7219->regmap, DA7219_ACCDET_CONFIG_1,
2483*4882a593Smuzhiyun DA7219_ACCDET_EN_MASK, 0);
2484*4882a593Smuzhiyun regmap_write_bits(da7219->regmap, DA7219_CIF_CTRL,
2485*4882a593Smuzhiyun DA7219_CIF_REG_SOFT_RESET_MASK,
2486*4882a593Smuzhiyun DA7219_CIF_REG_SOFT_RESET_MASK);
2487*4882a593Smuzhiyun regmap_write_bits(da7219->regmap, DA7219_SYSTEM_ACTIVE,
2488*4882a593Smuzhiyun DA7219_SYSTEM_ACTIVE_MASK, 0);
2489*4882a593Smuzhiyun regmap_write_bits(da7219->regmap, DA7219_SYSTEM_ACTIVE,
2490*4882a593Smuzhiyun DA7219_SYSTEM_ACTIVE_MASK, 1);
2491*4882a593Smuzhiyun
2492*4882a593Smuzhiyun regcache_cache_bypass(da7219->regmap, false);
2493*4882a593Smuzhiyun regmap_reinit_cache(da7219->regmap, &da7219_regmap_config);
2494*4882a593Smuzhiyun
2495*4882a593Smuzhiyun /* Update IO voltage level range based on supply level */
2496*4882a593Smuzhiyun snd_soc_component_write(component, DA7219_IO_CTRL, io_voltage_lvl);
2497*4882a593Smuzhiyun
2498*4882a593Smuzhiyun ret = regmap_read(da7219->regmap, DA7219_CHIP_REVISION, &rev);
2499*4882a593Smuzhiyun if (ret) {
2500*4882a593Smuzhiyun dev_err(component->dev, "Failed to read chip revision: %d\n", ret);
2501*4882a593Smuzhiyun goto err_disable_reg;
2502*4882a593Smuzhiyun }
2503*4882a593Smuzhiyun
2504*4882a593Smuzhiyun switch (rev & DA7219_CHIP_MINOR_MASK) {
2505*4882a593Smuzhiyun case 0:
2506*4882a593Smuzhiyun ret = regmap_register_patch(da7219->regmap, da7219_rev_aa_patch,
2507*4882a593Smuzhiyun ARRAY_SIZE(da7219_rev_aa_patch));
2508*4882a593Smuzhiyun if (ret) {
2509*4882a593Smuzhiyun dev_err(component->dev, "Failed to register AA patch: %d\n",
2510*4882a593Smuzhiyun ret);
2511*4882a593Smuzhiyun goto err_disable_reg;
2512*4882a593Smuzhiyun }
2513*4882a593Smuzhiyun break;
2514*4882a593Smuzhiyun default:
2515*4882a593Smuzhiyun break;
2516*4882a593Smuzhiyun }
2517*4882a593Smuzhiyun
2518*4882a593Smuzhiyun /* Handle DT/ACPI/Platform data */
2519*4882a593Smuzhiyun da7219_handle_pdata(component);
2520*4882a593Smuzhiyun
2521*4882a593Smuzhiyun /* Check if MCLK provided */
2522*4882a593Smuzhiyun da7219->mclk = clk_get(component->dev, "mclk");
2523*4882a593Smuzhiyun if (IS_ERR(da7219->mclk)) {
2524*4882a593Smuzhiyun if (PTR_ERR(da7219->mclk) != -ENOENT) {
2525*4882a593Smuzhiyun ret = PTR_ERR(da7219->mclk);
2526*4882a593Smuzhiyun goto err_disable_reg;
2527*4882a593Smuzhiyun } else {
2528*4882a593Smuzhiyun da7219->mclk = NULL;
2529*4882a593Smuzhiyun }
2530*4882a593Smuzhiyun }
2531*4882a593Smuzhiyun
2532*4882a593Smuzhiyun /* Register CCF DAI clock control */
2533*4882a593Smuzhiyun ret = da7219_register_dai_clks(component);
2534*4882a593Smuzhiyun if (ret)
2535*4882a593Smuzhiyun goto err_put_clk;
2536*4882a593Smuzhiyun
2537*4882a593Smuzhiyun /* Default PC counter to free-running */
2538*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7219_PC_COUNT, DA7219_PC_FREERUN_MASK,
2539*4882a593Smuzhiyun DA7219_PC_FREERUN_MASK);
2540*4882a593Smuzhiyun
2541*4882a593Smuzhiyun /* Default gain ramping */
2542*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7219_MIXIN_L_CTRL,
2543*4882a593Smuzhiyun DA7219_MIXIN_L_AMP_RAMP_EN_MASK,
2544*4882a593Smuzhiyun DA7219_MIXIN_L_AMP_RAMP_EN_MASK);
2545*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7219_ADC_L_CTRL, DA7219_ADC_L_RAMP_EN_MASK,
2546*4882a593Smuzhiyun DA7219_ADC_L_RAMP_EN_MASK);
2547*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7219_DAC_L_CTRL, DA7219_DAC_L_RAMP_EN_MASK,
2548*4882a593Smuzhiyun DA7219_DAC_L_RAMP_EN_MASK);
2549*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7219_DAC_R_CTRL, DA7219_DAC_R_RAMP_EN_MASK,
2550*4882a593Smuzhiyun DA7219_DAC_R_RAMP_EN_MASK);
2551*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7219_HP_L_CTRL,
2552*4882a593Smuzhiyun DA7219_HP_L_AMP_RAMP_EN_MASK,
2553*4882a593Smuzhiyun DA7219_HP_L_AMP_RAMP_EN_MASK);
2554*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7219_HP_R_CTRL,
2555*4882a593Smuzhiyun DA7219_HP_R_AMP_RAMP_EN_MASK,
2556*4882a593Smuzhiyun DA7219_HP_R_AMP_RAMP_EN_MASK);
2557*4882a593Smuzhiyun
2558*4882a593Smuzhiyun /* Default minimum gain on HP to avoid pops during DAPM sequencing */
2559*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7219_HP_L_CTRL,
2560*4882a593Smuzhiyun DA7219_HP_L_AMP_MIN_GAIN_EN_MASK,
2561*4882a593Smuzhiyun DA7219_HP_L_AMP_MIN_GAIN_EN_MASK);
2562*4882a593Smuzhiyun snd_soc_component_update_bits(component, DA7219_HP_R_CTRL,
2563*4882a593Smuzhiyun DA7219_HP_R_AMP_MIN_GAIN_EN_MASK,
2564*4882a593Smuzhiyun DA7219_HP_R_AMP_MIN_GAIN_EN_MASK);
2565*4882a593Smuzhiyun
2566*4882a593Smuzhiyun /* Default infinite tone gen, start/stop by Kcontrol */
2567*4882a593Smuzhiyun snd_soc_component_write(component, DA7219_TONE_GEN_CYCLES, DA7219_BEEP_CYCLES_MASK);
2568*4882a593Smuzhiyun
2569*4882a593Smuzhiyun /* Initialise AAD block */
2570*4882a593Smuzhiyun ret = da7219_aad_init(component);
2571*4882a593Smuzhiyun if (ret)
2572*4882a593Smuzhiyun goto err_free_dai_clks;
2573*4882a593Smuzhiyun
2574*4882a593Smuzhiyun return 0;
2575*4882a593Smuzhiyun
2576*4882a593Smuzhiyun err_free_dai_clks:
2577*4882a593Smuzhiyun da7219_free_dai_clks(component);
2578*4882a593Smuzhiyun
2579*4882a593Smuzhiyun err_put_clk:
2580*4882a593Smuzhiyun clk_put(da7219->mclk);
2581*4882a593Smuzhiyun
2582*4882a593Smuzhiyun err_disable_reg:
2583*4882a593Smuzhiyun regulator_bulk_disable(DA7219_NUM_SUPPLIES, da7219->supplies);
2584*4882a593Smuzhiyun regulator_bulk_free(DA7219_NUM_SUPPLIES, da7219->supplies);
2585*4882a593Smuzhiyun
2586*4882a593Smuzhiyun return ret;
2587*4882a593Smuzhiyun }
2588*4882a593Smuzhiyun
da7219_remove(struct snd_soc_component * component)2589*4882a593Smuzhiyun static void da7219_remove(struct snd_soc_component *component)
2590*4882a593Smuzhiyun {
2591*4882a593Smuzhiyun struct da7219_priv *da7219 = snd_soc_component_get_drvdata(component);
2592*4882a593Smuzhiyun
2593*4882a593Smuzhiyun da7219_aad_exit(component);
2594*4882a593Smuzhiyun
2595*4882a593Smuzhiyun da7219_free_dai_clks(component);
2596*4882a593Smuzhiyun clk_put(da7219->mclk);
2597*4882a593Smuzhiyun
2598*4882a593Smuzhiyun /* Supplies */
2599*4882a593Smuzhiyun regulator_bulk_disable(DA7219_NUM_SUPPLIES, da7219->supplies);
2600*4882a593Smuzhiyun regulator_bulk_free(DA7219_NUM_SUPPLIES, da7219->supplies);
2601*4882a593Smuzhiyun }
2602*4882a593Smuzhiyun
2603*4882a593Smuzhiyun #ifdef CONFIG_PM
da7219_suspend(struct snd_soc_component * component)2604*4882a593Smuzhiyun static int da7219_suspend(struct snd_soc_component *component)
2605*4882a593Smuzhiyun {
2606*4882a593Smuzhiyun struct da7219_priv *da7219 = snd_soc_component_get_drvdata(component);
2607*4882a593Smuzhiyun
2608*4882a593Smuzhiyun /* Suspend AAD if we're not a wake-up source */
2609*4882a593Smuzhiyun if (!da7219->wakeup_source)
2610*4882a593Smuzhiyun da7219_aad_suspend(component);
2611*4882a593Smuzhiyun
2612*4882a593Smuzhiyun snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
2613*4882a593Smuzhiyun
2614*4882a593Smuzhiyun return 0;
2615*4882a593Smuzhiyun }
2616*4882a593Smuzhiyun
da7219_resume(struct snd_soc_component * component)2617*4882a593Smuzhiyun static int da7219_resume(struct snd_soc_component *component)
2618*4882a593Smuzhiyun {
2619*4882a593Smuzhiyun struct da7219_priv *da7219 = snd_soc_component_get_drvdata(component);
2620*4882a593Smuzhiyun
2621*4882a593Smuzhiyun snd_soc_component_force_bias_level(component, SND_SOC_BIAS_STANDBY);
2622*4882a593Smuzhiyun
2623*4882a593Smuzhiyun /* Resume AAD if previously suspended */
2624*4882a593Smuzhiyun if (!da7219->wakeup_source)
2625*4882a593Smuzhiyun da7219_aad_resume(component);
2626*4882a593Smuzhiyun
2627*4882a593Smuzhiyun return 0;
2628*4882a593Smuzhiyun }
2629*4882a593Smuzhiyun #else
2630*4882a593Smuzhiyun #define da7219_suspend NULL
2631*4882a593Smuzhiyun #define da7219_resume NULL
2632*4882a593Smuzhiyun #endif
2633*4882a593Smuzhiyun
2634*4882a593Smuzhiyun static const struct snd_soc_component_driver soc_component_dev_da7219 = {
2635*4882a593Smuzhiyun .probe = da7219_probe,
2636*4882a593Smuzhiyun .remove = da7219_remove,
2637*4882a593Smuzhiyun .suspend = da7219_suspend,
2638*4882a593Smuzhiyun .resume = da7219_resume,
2639*4882a593Smuzhiyun .set_bias_level = da7219_set_bias_level,
2640*4882a593Smuzhiyun .controls = da7219_snd_controls,
2641*4882a593Smuzhiyun .num_controls = ARRAY_SIZE(da7219_snd_controls),
2642*4882a593Smuzhiyun .dapm_widgets = da7219_dapm_widgets,
2643*4882a593Smuzhiyun .num_dapm_widgets = ARRAY_SIZE(da7219_dapm_widgets),
2644*4882a593Smuzhiyun .dapm_routes = da7219_audio_map,
2645*4882a593Smuzhiyun .num_dapm_routes = ARRAY_SIZE(da7219_audio_map),
2646*4882a593Smuzhiyun .idle_bias_on = 1,
2647*4882a593Smuzhiyun .use_pmdown_time = 1,
2648*4882a593Smuzhiyun .endianness = 1,
2649*4882a593Smuzhiyun .non_legacy_dai_naming = 1,
2650*4882a593Smuzhiyun };
2651*4882a593Smuzhiyun
2652*4882a593Smuzhiyun
2653*4882a593Smuzhiyun /*
2654*4882a593Smuzhiyun * I2C layer
2655*4882a593Smuzhiyun */
2656*4882a593Smuzhiyun
da7219_i2c_probe(struct i2c_client * i2c,const struct i2c_device_id * id)2657*4882a593Smuzhiyun static int da7219_i2c_probe(struct i2c_client *i2c,
2658*4882a593Smuzhiyun const struct i2c_device_id *id)
2659*4882a593Smuzhiyun {
2660*4882a593Smuzhiyun struct device *dev = &i2c->dev;
2661*4882a593Smuzhiyun struct da7219_priv *da7219;
2662*4882a593Smuzhiyun int ret;
2663*4882a593Smuzhiyun
2664*4882a593Smuzhiyun da7219 = devm_kzalloc(dev, sizeof(struct da7219_priv),
2665*4882a593Smuzhiyun GFP_KERNEL);
2666*4882a593Smuzhiyun if (!da7219)
2667*4882a593Smuzhiyun return -ENOMEM;
2668*4882a593Smuzhiyun
2669*4882a593Smuzhiyun i2c_set_clientdata(i2c, da7219);
2670*4882a593Smuzhiyun
2671*4882a593Smuzhiyun da7219->regmap = devm_regmap_init_i2c(i2c, &da7219_regmap_config);
2672*4882a593Smuzhiyun if (IS_ERR(da7219->regmap)) {
2673*4882a593Smuzhiyun ret = PTR_ERR(da7219->regmap);
2674*4882a593Smuzhiyun dev_err(dev, "regmap_init() failed: %d\n", ret);
2675*4882a593Smuzhiyun return ret;
2676*4882a593Smuzhiyun }
2677*4882a593Smuzhiyun
2678*4882a593Smuzhiyun /* Retrieve DT/ACPI/Platform data */
2679*4882a593Smuzhiyun da7219->pdata = dev_get_platdata(dev);
2680*4882a593Smuzhiyun if (!da7219->pdata)
2681*4882a593Smuzhiyun da7219->pdata = da7219_fw_to_pdata(dev);
2682*4882a593Smuzhiyun
2683*4882a593Smuzhiyun /* AAD */
2684*4882a593Smuzhiyun ret = da7219_aad_probe(i2c);
2685*4882a593Smuzhiyun if (ret)
2686*4882a593Smuzhiyun return ret;
2687*4882a593Smuzhiyun
2688*4882a593Smuzhiyun ret = devm_snd_soc_register_component(dev, &soc_component_dev_da7219,
2689*4882a593Smuzhiyun &da7219_dai, 1);
2690*4882a593Smuzhiyun if (ret < 0) {
2691*4882a593Smuzhiyun dev_err(dev, "Failed to register da7219 component: %d\n", ret);
2692*4882a593Smuzhiyun }
2693*4882a593Smuzhiyun return ret;
2694*4882a593Smuzhiyun }
2695*4882a593Smuzhiyun
da7219_i2c_remove(struct i2c_client * client)2696*4882a593Smuzhiyun static int da7219_i2c_remove(struct i2c_client *client)
2697*4882a593Smuzhiyun {
2698*4882a593Smuzhiyun return 0;
2699*4882a593Smuzhiyun }
2700*4882a593Smuzhiyun
2701*4882a593Smuzhiyun static const struct i2c_device_id da7219_i2c_id[] = {
2702*4882a593Smuzhiyun { "da7219", },
2703*4882a593Smuzhiyun { }
2704*4882a593Smuzhiyun };
2705*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, da7219_i2c_id);
2706*4882a593Smuzhiyun
2707*4882a593Smuzhiyun static struct i2c_driver da7219_i2c_driver = {
2708*4882a593Smuzhiyun .driver = {
2709*4882a593Smuzhiyun .name = "da7219",
2710*4882a593Smuzhiyun .of_match_table = of_match_ptr(da7219_of_match),
2711*4882a593Smuzhiyun .acpi_match_table = ACPI_PTR(da7219_acpi_match),
2712*4882a593Smuzhiyun },
2713*4882a593Smuzhiyun .probe = da7219_i2c_probe,
2714*4882a593Smuzhiyun .remove = da7219_i2c_remove,
2715*4882a593Smuzhiyun .id_table = da7219_i2c_id,
2716*4882a593Smuzhiyun };
2717*4882a593Smuzhiyun
2718*4882a593Smuzhiyun module_i2c_driver(da7219_i2c_driver);
2719*4882a593Smuzhiyun
2720*4882a593Smuzhiyun MODULE_DESCRIPTION("ASoC DA7219 Codec Driver");
2721*4882a593Smuzhiyun MODULE_AUTHOR("Adam Thomson <Adam.Thomson.Opensource@diasemi.com>");
2722*4882a593Smuzhiyun MODULE_LICENSE("GPL");
2723