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/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dpicoxcell-pc3x3.dtsi38 compatible = "picochip,pc3x3-gated-clk";
46 compatible = "picochip,pc3x3-gated-clk";
54 compatible = "picochip,pc3x3-gated-clk";
62 compatible = "picochip,pc3x3-gated-clk";
70 compatible = "picochip,pc3x3-gated-clk";
78 compatible = "picochip,pc3x3-gated-clk";
86 compatible = "picochip,pc3x3-gated-clk";
94 compatible = "picochip,pc3x3-gated-clk";
102 compatible = "picochip,pc3x3-gated-clk";
110 compatible = "picochip,pc3x3-gated-clk";
/OK3568_Linux_fs/kernel/drivers/cpuidle/
H A Dcpuidle-cps.c18 STATE_CLOCK_GATED, /* Core clock gated */
19 STATE_POWER_GATED, /* Core power gated */
86 .name = "clock-gated",
87 .desc = "core clock gated",
94 .name = "power-gated",
95 .desc = "core power gated",
/OK3568_Linux_fs/kernel/sound/pci/hda/
H A Dhda_jack.c203 /* If a jack is gated by this one update it. */ in jack_detect_update()
205 struct hda_jack_tbl *gated = in jack_detect_update() local
208 if (gated) { in jack_detect_update()
209 gated->jack_dirty = 1; in jack_detect_update()
210 jack_detect_update(codec, gated); in jack_detect_update()
367 * @gated_nid: gated pin NID
370 * Indicates the gated jack is only valid when the gating jack is plugged.
375 struct hda_jack_tbl *gated = snd_hda_jack_tbl_new(codec, gated_nid, 0); in snd_hda_jack_set_gating_jack() local
381 if (!gated || !gating) in snd_hda_jack_set_gating_jack()
384 gated->gating_jack = gating_nid; in snd_hda_jack_set_gating_jack()
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/radeon/
H A Dvce_v2_0.c38 static void vce_v2_0_set_sw_cg(struct radeon_device *rdev, bool gated) in vce_v2_0_set_sw_cg() argument
42 if (gated) { in vce_v2_0_set_sw_cg()
73 static void vce_v2_0_set_dyn_cg(struct radeon_device *rdev, bool gated) in vce_v2_0_set_dyn_cg() argument
79 if (gated) { in vce_v2_0_set_dyn_cg()
98 if (gated) in vce_v2_0_set_dyn_cg()
/OK3568_Linux_fs/u-boot/doc/device-tree-bindings/clock/
H A Dst,stm32-rcc.txt18 between gated clocks and other clocks and an index specifying the clock to
30 Specifying gated clocks
50 /* Gated clock, AHB1 bit 0 (GPIOA) */
55 /* Gated clock, AHB2 bit 4 (CRYP) */
/OK3568_Linux_fs/kernel/arch/mips/bcm63xx/
H A Dclk.c423 /* gated clocks */
441 /* gated clocks */
453 /* gated clocks */
467 /* gated clocks */
481 /* gated clocks */
497 /* gated clocks */
517 /* gated clocks */
532 /* gated clocks */
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/
H A Dst,stm32-rcc.txt21 between gated clocks and other clocks and an index specifying the clock to
37 Specifying gated clocks
57 /* Gated clock, AHB1 bit 0 (GPIOA) */
62 /* Gated clock, AHB2 bit 4 (CRYP) */
H A Dmaxim,max77686.txt11 (gated/ungated) over I2C. Clocks are defined as preprocessor macros in
16 (gated/ungated) over I2C. Clocks are defined as preprocessor macros in
20 (gated/ungated) over I2C. Clocks are defined as preprocessor macros in
H A Dmaxim,max9485.txt5 - MAX9485_MCLKOUT: A gated, buffered output of the input clock of 27 MHz
8 - MAX9485_CLKOUT[1,2]: Two gated outputs for MAX9485_CLKOUT
H A Dmvebu-gated-clock.txt1 * Gated Clock bindings for Marvell EBU SoCs
4 peripheral clocks to be gated to save some power. The clock consumer
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/pm/inc/
H A Dsmu_v12_0_ppsmc.h42 #define PPSMC_MSG_PowerDownIspByTile 0x9 // ISP is power gated by default
44 #define PPSMC_MSG_PowerDownVcn 0xB // VCN is power gated by default
46 #define PPSMC_MSG_PowerDownSdma 0xD // SDMA is power gated by default
/OK3568_Linux_fs/kernel/tools/perf/pmu-events/arch/arm64/ampere/emag/
H A Dclock.json9 "PublicDescription": "FSU clocking gated off cycle",
12 "BriefDescription": "FSU clocking gated off cycle"
/OK3568_Linux_fs/kernel/drivers/staging/media/atomisp/pci/
H A Datomisp-regs.h64 * If cleared, the high speed clock going to the digital logic is gated when
65 * RCOMP update is happening. The clock is gated for a minimum of 100 nsec.
66 * If this bit is set, then the high speed clock is not gated during the
/OK3568_Linux_fs/kernel/arch/arm/mach-tegra/
H A Dplatsmp.c50 * power-gated via the flow controller). This will have no in tegra20_boot_secondary()
103 * The power status of the cold boot CPU is power gated as in tegra30_boot_secondary()
105 * be un-gated by un-toggling the power gate register in tegra30_boot_secondary()
/OK3568_Linux_fs/kernel/arch/mips/include/asm/
H A Dpm-cps.h26 CPS_PM_CLOCK_GATED, /* Core clock gated */
27 CPS_PM_POWER_GATED, /* Core power gated */
/OK3568_Linux_fs/kernel/drivers/mmc/host/
H A Dtoshsd.h14 #define SD_PCICFG_GATEDCLK 0x41 /* Gated clock */
22 #define SD_PCICFG_EXTGATECLK1 0xf0 /* Could be used for gated clock */
23 #define SD_PCICFG_EXTGATECLK2 0xf1 /* Could be used for gated clock */
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/amdgpu/
H A Dvce_v2_0.c310 static void vce_v2_0_set_sw_cg(struct amdgpu_device *adev, bool gated) in vce_v2_0_set_sw_cg() argument
314 if (gated) { in vce_v2_0_set_sw_cg()
345 static void vce_v2_0_set_dyn_cg(struct amdgpu_device *adev, bool gated) in vce_v2_0_set_dyn_cg() argument
356 if (gated) { in vce_v2_0_set_dyn_cg()
379 if(gated) in vce_v2_0_set_dyn_cg()
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/arm/msm/
H A Dqcom,idle-state.txt26 Retention: Retention is a low power state where the core is clock gated and
50 be flushed, system bus, clocks - lowered, and SoC main XO clock gated and
/OK3568_Linux_fs/kernel/drivers/clk/baikal-t1/
H A Dclk-ccu-pll.c56 * shouldn't be ever gated. SATA and PCIe PLLs are the parents of APB-bus and
57 * DDR controller AXI-bus clocks. If they are gated the system will be
/OK3568_Linux_fs/kernel/drivers/clk/
H A Dclk-gpio.c22 * DOC: basic gpio gated clock which can be enabled and disabled
32 * struct clk_gpio - gpio gated clock
H A Dclk-gemini.c53 * struct gemini_data_data - Gemini gated clocks
103 * not be gated off.
337 * These are the leaf gates, at boot no clocks are gated. in gemini_clk_probe()
/OK3568_Linux_fs/kernel/drivers/staging/rtl8723bs/include/
H A Dhal_pwr_seq.h145 …MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/ \
174 …MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/ \
176 …MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/ \
178 …MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/ \
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8189es/include/
H A DHal8723BPwrSeq.h145 …LL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated*/ \
174 …IO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated*/ \
176 …IO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated*/ \
178 …IO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated*/ \
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8822be/include/
H A DHal8723BPwrSeq.h145 …MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/ \
174 …MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/ \
176 …MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/ \
178 …MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/ \
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8723bu/include/
H A DHal8723BPwrSeq.h145 …LL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated*/ \
174 …IO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated*/ \
176 …IO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated*/ \
178 …IO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated*/ \

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