xref: /OK3568_Linux_fs/kernel/drivers/clk/clk-gpio.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (C) 2013 - 2014 Texas Instruments Incorporated - https://www.ti.com
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Authors:
6*4882a593Smuzhiyun  *    Jyri Sarha <jsarha@ti.com>
7*4882a593Smuzhiyun  *    Sergej Sawazki <ce3a@gmx.de>
8*4882a593Smuzhiyun  *
9*4882a593Smuzhiyun  * Gpio controlled clock implementation
10*4882a593Smuzhiyun  */
11*4882a593Smuzhiyun 
12*4882a593Smuzhiyun #include <linux/clk-provider.h>
13*4882a593Smuzhiyun #include <linux/export.h>
14*4882a593Smuzhiyun #include <linux/slab.h>
15*4882a593Smuzhiyun #include <linux/gpio/consumer.h>
16*4882a593Smuzhiyun #include <linux/err.h>
17*4882a593Smuzhiyun #include <linux/device.h>
18*4882a593Smuzhiyun #include <linux/platform_device.h>
19*4882a593Smuzhiyun #include <linux/of_device.h>
20*4882a593Smuzhiyun 
21*4882a593Smuzhiyun /**
22*4882a593Smuzhiyun  * DOC: basic gpio gated clock which can be enabled and disabled
23*4882a593Smuzhiyun  *      with gpio output
24*4882a593Smuzhiyun  * Traits of this clock:
25*4882a593Smuzhiyun  * prepare - clk_(un)prepare only ensures parent is (un)prepared
26*4882a593Smuzhiyun  * enable - clk_enable and clk_disable are functional & control gpio
27*4882a593Smuzhiyun  * rate - inherits rate from parent.  No clk_set_rate support
28*4882a593Smuzhiyun  * parent - fixed parent.  No clk_set_parent support
29*4882a593Smuzhiyun  */
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun /**
32*4882a593Smuzhiyun  * struct clk_gpio - gpio gated clock
33*4882a593Smuzhiyun  *
34*4882a593Smuzhiyun  * @hw:		handle between common and hardware-specific interfaces
35*4882a593Smuzhiyun  * @gpiod:	gpio descriptor
36*4882a593Smuzhiyun  *
37*4882a593Smuzhiyun  * Clock with a gpio control for enabling and disabling the parent clock
38*4882a593Smuzhiyun  * or switching between two parents by asserting or deasserting the gpio.
39*4882a593Smuzhiyun  *
40*4882a593Smuzhiyun  * Implements .enable, .disable and .is_enabled or
41*4882a593Smuzhiyun  * .get_parent, .set_parent and .determine_rate depending on which clk_ops
42*4882a593Smuzhiyun  * is used.
43*4882a593Smuzhiyun  */
44*4882a593Smuzhiyun struct clk_gpio {
45*4882a593Smuzhiyun 	struct clk_hw	hw;
46*4882a593Smuzhiyun 	struct gpio_desc *gpiod;
47*4882a593Smuzhiyun };
48*4882a593Smuzhiyun 
49*4882a593Smuzhiyun #define to_clk_gpio(_hw) container_of(_hw, struct clk_gpio, hw)
50*4882a593Smuzhiyun 
clk_gpio_gate_enable(struct clk_hw * hw)51*4882a593Smuzhiyun static int clk_gpio_gate_enable(struct clk_hw *hw)
52*4882a593Smuzhiyun {
53*4882a593Smuzhiyun 	struct clk_gpio *clk = to_clk_gpio(hw);
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun 	gpiod_set_value(clk->gpiod, 1);
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun 	return 0;
58*4882a593Smuzhiyun }
59*4882a593Smuzhiyun 
clk_gpio_gate_disable(struct clk_hw * hw)60*4882a593Smuzhiyun static void clk_gpio_gate_disable(struct clk_hw *hw)
61*4882a593Smuzhiyun {
62*4882a593Smuzhiyun 	struct clk_gpio *clk = to_clk_gpio(hw);
63*4882a593Smuzhiyun 
64*4882a593Smuzhiyun 	gpiod_set_value(clk->gpiod, 0);
65*4882a593Smuzhiyun }
66*4882a593Smuzhiyun 
clk_gpio_gate_is_enabled(struct clk_hw * hw)67*4882a593Smuzhiyun static int clk_gpio_gate_is_enabled(struct clk_hw *hw)
68*4882a593Smuzhiyun {
69*4882a593Smuzhiyun 	struct clk_gpio *clk = to_clk_gpio(hw);
70*4882a593Smuzhiyun 
71*4882a593Smuzhiyun 	return gpiod_get_value(clk->gpiod);
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun static const struct clk_ops clk_gpio_gate_ops = {
75*4882a593Smuzhiyun 	.enable = clk_gpio_gate_enable,
76*4882a593Smuzhiyun 	.disable = clk_gpio_gate_disable,
77*4882a593Smuzhiyun 	.is_enabled = clk_gpio_gate_is_enabled,
78*4882a593Smuzhiyun };
79*4882a593Smuzhiyun 
clk_sleeping_gpio_gate_prepare(struct clk_hw * hw)80*4882a593Smuzhiyun static int clk_sleeping_gpio_gate_prepare(struct clk_hw *hw)
81*4882a593Smuzhiyun {
82*4882a593Smuzhiyun 	struct clk_gpio *clk = to_clk_gpio(hw);
83*4882a593Smuzhiyun 
84*4882a593Smuzhiyun 	gpiod_set_value_cansleep(clk->gpiod, 1);
85*4882a593Smuzhiyun 
86*4882a593Smuzhiyun 	return 0;
87*4882a593Smuzhiyun }
88*4882a593Smuzhiyun 
clk_sleeping_gpio_gate_unprepare(struct clk_hw * hw)89*4882a593Smuzhiyun static void clk_sleeping_gpio_gate_unprepare(struct clk_hw *hw)
90*4882a593Smuzhiyun {
91*4882a593Smuzhiyun 	struct clk_gpio *clk = to_clk_gpio(hw);
92*4882a593Smuzhiyun 
93*4882a593Smuzhiyun 	gpiod_set_value_cansleep(clk->gpiod, 0);
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun 
clk_sleeping_gpio_gate_is_prepared(struct clk_hw * hw)96*4882a593Smuzhiyun static int clk_sleeping_gpio_gate_is_prepared(struct clk_hw *hw)
97*4882a593Smuzhiyun {
98*4882a593Smuzhiyun 	struct clk_gpio *clk = to_clk_gpio(hw);
99*4882a593Smuzhiyun 
100*4882a593Smuzhiyun 	return gpiod_get_value_cansleep(clk->gpiod);
101*4882a593Smuzhiyun }
102*4882a593Smuzhiyun 
103*4882a593Smuzhiyun static const struct clk_ops clk_sleeping_gpio_gate_ops = {
104*4882a593Smuzhiyun 	.prepare = clk_sleeping_gpio_gate_prepare,
105*4882a593Smuzhiyun 	.unprepare = clk_sleeping_gpio_gate_unprepare,
106*4882a593Smuzhiyun 	.is_prepared = clk_sleeping_gpio_gate_is_prepared,
107*4882a593Smuzhiyun };
108*4882a593Smuzhiyun 
109*4882a593Smuzhiyun /**
110*4882a593Smuzhiyun  * DOC: basic clock multiplexer which can be controlled with a gpio output
111*4882a593Smuzhiyun  * Traits of this clock:
112*4882a593Smuzhiyun  * prepare - clk_prepare only ensures that parents are prepared
113*4882a593Smuzhiyun  * rate - rate is only affected by parent switching.  No clk_set_rate support
114*4882a593Smuzhiyun  * parent - parent is adjustable through clk_set_parent
115*4882a593Smuzhiyun  */
116*4882a593Smuzhiyun 
clk_gpio_mux_get_parent(struct clk_hw * hw)117*4882a593Smuzhiyun static u8 clk_gpio_mux_get_parent(struct clk_hw *hw)
118*4882a593Smuzhiyun {
119*4882a593Smuzhiyun 	struct clk_gpio *clk = to_clk_gpio(hw);
120*4882a593Smuzhiyun 
121*4882a593Smuzhiyun 	return gpiod_get_value_cansleep(clk->gpiod);
122*4882a593Smuzhiyun }
123*4882a593Smuzhiyun 
clk_gpio_mux_set_parent(struct clk_hw * hw,u8 index)124*4882a593Smuzhiyun static int clk_gpio_mux_set_parent(struct clk_hw *hw, u8 index)
125*4882a593Smuzhiyun {
126*4882a593Smuzhiyun 	struct clk_gpio *clk = to_clk_gpio(hw);
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun 	gpiod_set_value_cansleep(clk->gpiod, index);
129*4882a593Smuzhiyun 
130*4882a593Smuzhiyun 	return 0;
131*4882a593Smuzhiyun }
132*4882a593Smuzhiyun 
133*4882a593Smuzhiyun static const struct clk_ops clk_gpio_mux_ops = {
134*4882a593Smuzhiyun 	.get_parent = clk_gpio_mux_get_parent,
135*4882a593Smuzhiyun 	.set_parent = clk_gpio_mux_set_parent,
136*4882a593Smuzhiyun 	.determine_rate = __clk_mux_determine_rate,
137*4882a593Smuzhiyun };
138*4882a593Smuzhiyun 
clk_register_gpio(struct device * dev,u8 num_parents,struct gpio_desc * gpiod,const struct clk_ops * clk_gpio_ops)139*4882a593Smuzhiyun static struct clk_hw *clk_register_gpio(struct device *dev, u8 num_parents,
140*4882a593Smuzhiyun 					struct gpio_desc *gpiod,
141*4882a593Smuzhiyun 					const struct clk_ops *clk_gpio_ops)
142*4882a593Smuzhiyun {
143*4882a593Smuzhiyun 	struct clk_gpio *clk_gpio;
144*4882a593Smuzhiyun 	struct clk_hw *hw;
145*4882a593Smuzhiyun 	struct clk_init_data init = {};
146*4882a593Smuzhiyun 	int err;
147*4882a593Smuzhiyun 	const struct clk_parent_data gpio_parent_data[] = {
148*4882a593Smuzhiyun 		{ .index = 0 },
149*4882a593Smuzhiyun 		{ .index = 1 },
150*4882a593Smuzhiyun 	};
151*4882a593Smuzhiyun 
152*4882a593Smuzhiyun 	clk_gpio = devm_kzalloc(dev, sizeof(*clk_gpio),	GFP_KERNEL);
153*4882a593Smuzhiyun 	if (!clk_gpio)
154*4882a593Smuzhiyun 		return ERR_PTR(-ENOMEM);
155*4882a593Smuzhiyun 
156*4882a593Smuzhiyun 	init.name = dev->of_node->name;
157*4882a593Smuzhiyun 	init.ops = clk_gpio_ops;
158*4882a593Smuzhiyun 	init.parent_data = gpio_parent_data;
159*4882a593Smuzhiyun 	init.num_parents = num_parents;
160*4882a593Smuzhiyun 	init.flags = CLK_SET_RATE_PARENT;
161*4882a593Smuzhiyun 
162*4882a593Smuzhiyun 	clk_gpio->gpiod = gpiod;
163*4882a593Smuzhiyun 	clk_gpio->hw.init = &init;
164*4882a593Smuzhiyun 
165*4882a593Smuzhiyun 	hw = &clk_gpio->hw;
166*4882a593Smuzhiyun 	err = devm_clk_hw_register(dev, hw);
167*4882a593Smuzhiyun 	if (err)
168*4882a593Smuzhiyun 		return ERR_PTR(err);
169*4882a593Smuzhiyun 
170*4882a593Smuzhiyun 	return hw;
171*4882a593Smuzhiyun }
172*4882a593Smuzhiyun 
clk_hw_register_gpio_gate(struct device * dev,int num_parents,struct gpio_desc * gpiod)173*4882a593Smuzhiyun static struct clk_hw *clk_hw_register_gpio_gate(struct device *dev,
174*4882a593Smuzhiyun 						int num_parents,
175*4882a593Smuzhiyun 						struct gpio_desc *gpiod)
176*4882a593Smuzhiyun {
177*4882a593Smuzhiyun 	const struct clk_ops *ops;
178*4882a593Smuzhiyun 
179*4882a593Smuzhiyun 	if (gpiod_cansleep(gpiod))
180*4882a593Smuzhiyun 		ops = &clk_sleeping_gpio_gate_ops;
181*4882a593Smuzhiyun 	else
182*4882a593Smuzhiyun 		ops = &clk_gpio_gate_ops;
183*4882a593Smuzhiyun 
184*4882a593Smuzhiyun 	return clk_register_gpio(dev, num_parents, gpiod, ops);
185*4882a593Smuzhiyun }
186*4882a593Smuzhiyun 
clk_hw_register_gpio_mux(struct device * dev,struct gpio_desc * gpiod)187*4882a593Smuzhiyun static struct clk_hw *clk_hw_register_gpio_mux(struct device *dev,
188*4882a593Smuzhiyun 					       struct gpio_desc *gpiod)
189*4882a593Smuzhiyun {
190*4882a593Smuzhiyun 	return clk_register_gpio(dev, 2, gpiod, &clk_gpio_mux_ops);
191*4882a593Smuzhiyun }
192*4882a593Smuzhiyun 
gpio_clk_driver_probe(struct platform_device * pdev)193*4882a593Smuzhiyun static int gpio_clk_driver_probe(struct platform_device *pdev)
194*4882a593Smuzhiyun {
195*4882a593Smuzhiyun 	struct device *dev = &pdev->dev;
196*4882a593Smuzhiyun 	struct device_node *node = dev->of_node;
197*4882a593Smuzhiyun 	const char *gpio_name;
198*4882a593Smuzhiyun 	unsigned int num_parents;
199*4882a593Smuzhiyun 	struct gpio_desc *gpiod;
200*4882a593Smuzhiyun 	struct clk_hw *hw;
201*4882a593Smuzhiyun 	bool is_mux;
202*4882a593Smuzhiyun 	int ret;
203*4882a593Smuzhiyun 
204*4882a593Smuzhiyun 	is_mux = of_device_is_compatible(node, "gpio-mux-clock");
205*4882a593Smuzhiyun 
206*4882a593Smuzhiyun 	num_parents = of_clk_get_parent_count(node);
207*4882a593Smuzhiyun 	if (is_mux && num_parents != 2) {
208*4882a593Smuzhiyun 		dev_err(dev, "mux-clock must have 2 parents\n");
209*4882a593Smuzhiyun 		return -EINVAL;
210*4882a593Smuzhiyun 	}
211*4882a593Smuzhiyun 
212*4882a593Smuzhiyun 	gpio_name = is_mux ? "select" : "enable";
213*4882a593Smuzhiyun 	gpiod = devm_gpiod_get(dev, gpio_name, GPIOD_OUT_LOW);
214*4882a593Smuzhiyun 	if (IS_ERR(gpiod)) {
215*4882a593Smuzhiyun 		ret = PTR_ERR(gpiod);
216*4882a593Smuzhiyun 		if (ret == -EPROBE_DEFER)
217*4882a593Smuzhiyun 			pr_debug("%pOFn: %s: GPIOs not yet available, retry later\n",
218*4882a593Smuzhiyun 					node, __func__);
219*4882a593Smuzhiyun 		else
220*4882a593Smuzhiyun 			pr_err("%pOFn: %s: Can't get '%s' named GPIO property\n",
221*4882a593Smuzhiyun 					node, __func__,
222*4882a593Smuzhiyun 					gpio_name);
223*4882a593Smuzhiyun 		return ret;
224*4882a593Smuzhiyun 	}
225*4882a593Smuzhiyun 
226*4882a593Smuzhiyun 	if (is_mux)
227*4882a593Smuzhiyun 		hw = clk_hw_register_gpio_mux(dev, gpiod);
228*4882a593Smuzhiyun 	else
229*4882a593Smuzhiyun 		hw = clk_hw_register_gpio_gate(dev, num_parents, gpiod);
230*4882a593Smuzhiyun 	if (IS_ERR(hw))
231*4882a593Smuzhiyun 		return PTR_ERR(hw);
232*4882a593Smuzhiyun 
233*4882a593Smuzhiyun 	return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
234*4882a593Smuzhiyun }
235*4882a593Smuzhiyun 
236*4882a593Smuzhiyun static const struct of_device_id gpio_clk_match_table[] = {
237*4882a593Smuzhiyun 	{ .compatible = "gpio-mux-clock" },
238*4882a593Smuzhiyun 	{ .compatible = "gpio-gate-clock" },
239*4882a593Smuzhiyun 	{ }
240*4882a593Smuzhiyun };
241*4882a593Smuzhiyun 
242*4882a593Smuzhiyun static struct platform_driver gpio_clk_driver = {
243*4882a593Smuzhiyun 	.probe		= gpio_clk_driver_probe,
244*4882a593Smuzhiyun 	.driver		= {
245*4882a593Smuzhiyun 		.name	= "gpio-clk",
246*4882a593Smuzhiyun 		.of_match_table = gpio_clk_match_table,
247*4882a593Smuzhiyun 	},
248*4882a593Smuzhiyun };
249*4882a593Smuzhiyun builtin_platform_driver(gpio_clk_driver);
250