1*4882a593SmuzhiyunQCOM Idle States for cpuidle driver 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunARM provides idle-state node to define the cpuidle states, as defined in [1]. 4*4882a593Smuzhiyuncpuidle-qcom is the cpuidle driver for Qualcomm SoCs and uses these idle 5*4882a593Smuzhiyunstates. Idle states have different enter/exit latency and residency values. 6*4882a593SmuzhiyunThe idle states supported by the QCOM SoC are defined as - 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun * Standby 9*4882a593Smuzhiyun * Retention 10*4882a593Smuzhiyun * Standalone Power Collapse (Standalone PC or SPC) 11*4882a593Smuzhiyun * Power Collapse (PC) 12*4882a593Smuzhiyun 13*4882a593SmuzhiyunStandby: Standby does a little more in addition to architectural clock gating. 14*4882a593SmuzhiyunWhen the WFI instruction is executed the ARM core would gate its internal 15*4882a593Smuzhiyunclocks. In addition to gating the clocks, QCOM cpus use this instruction as a 16*4882a593Smuzhiyuntrigger to execute the SPM state machine. The SPM state machine waits for the 17*4882a593Smuzhiyuninterrupt to trigger the core back in to active. This triggers the cache 18*4882a593Smuzhiyunhierarchy to enter standby states, when all cpus are idle. An interrupt brings 19*4882a593Smuzhiyunthe SPM state machine out of its wait, the next step is to ensure that the 20*4882a593Smuzhiyuncache hierarchy is also out of standby, and then the cpu is allowed to resume 21*4882a593Smuzhiyunexecution. This state is defined as a generic ARM WFI state by the ARM cpuidle 22*4882a593Smuzhiyundriver and is not defined in the DT. The SPM state machine should be 23*4882a593Smuzhiyunconfigured to execute this state by default and after executing every other 24*4882a593Smuzhiyunstate below. 25*4882a593Smuzhiyun 26*4882a593SmuzhiyunRetention: Retention is a low power state where the core is clock gated and 27*4882a593Smuzhiyunthe memory and the registers associated with the core are retained. The 28*4882a593Smuzhiyunvoltage may be reduced to the minimum value needed to keep the processor 29*4882a593Smuzhiyunregisters active. The SPM should be configured to execute the retention 30*4882a593Smuzhiyunsequence and would wait for interrupt, before restoring the cpu to execution 31*4882a593Smuzhiyunstate. Retention may have a slightly higher latency than Standby. 32*4882a593Smuzhiyun 33*4882a593SmuzhiyunStandalone PC: A cpu can power down and warmboot if there is a sufficient time 34*4882a593Smuzhiyunbetween the time it enters idle and the next known wake up. SPC mode is used 35*4882a593Smuzhiyunto indicate a core entering a power down state without consulting any other 36*4882a593Smuzhiyuncpu or the system resources. This helps save power only on that core. The SPM 37*4882a593Smuzhiyunsequence for this idle state is programmed to power down the supply to the 38*4882a593Smuzhiyuncore, wait for the interrupt, restore power to the core, and ensure the 39*4882a593Smuzhiyunsystem state including cache hierarchy is ready before allowing core to 40*4882a593Smuzhiyunresume. Applying power and resetting the core causes the core to warmboot 41*4882a593Smuzhiyunback into Elevation Level (EL) which trampolines the control back to the 42*4882a593Smuzhiyunkernel. Entering a power down state for the cpu, needs to be done by trapping 43*4882a593Smuzhiyuninto a EL. Failing to do so, would result in a crash enforced by the warm boot 44*4882a593Smuzhiyuncode in the EL for the SoC. On SoCs with write-back L1 cache, the cache has to 45*4882a593Smuzhiyunbe flushed in s/w, before powering down the core. 46*4882a593Smuzhiyun 47*4882a593SmuzhiyunPower Collapse: This state is similar to the SPC mode, but distinguishes 48*4882a593Smuzhiyunitself in that the cpu acknowledges and permits the SoC to enter deeper sleep 49*4882a593Smuzhiyunmodes. In a hierarchical power domain SoC, this means L2 and other caches can 50*4882a593Smuzhiyunbe flushed, system bus, clocks - lowered, and SoC main XO clock gated and 51*4882a593Smuzhiyunvoltages reduced, provided all cpus enter this state. Since the span of low 52*4882a593Smuzhiyunpower modes possible at this state is vast, the exit latency and the residency 53*4882a593Smuzhiyunof this low power mode would be considered high even though at a cpu level, 54*4882a593Smuzhiyunthis essentially is cpu power down. The SPM in this state also may handshake 55*4882a593Smuzhiyunwith the Resource power manager (RPM) processor in the SoC to indicate a 56*4882a593Smuzhiyuncomplete application processor subsystem shut down. 57*4882a593Smuzhiyun 58*4882a593SmuzhiyunThe idle-state for QCOM SoCs are distinguished by the compatible property of 59*4882a593Smuzhiyunthe idle-states device node. 60*4882a593Smuzhiyun 61*4882a593SmuzhiyunThe devicetree representation of the idle state should be - 62*4882a593Smuzhiyun 63*4882a593SmuzhiyunRequired properties: 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun- compatible: Must be one of - 66*4882a593Smuzhiyun "qcom,idle-state-ret", 67*4882a593Smuzhiyun "qcom,idle-state-spc", 68*4882a593Smuzhiyun "qcom,idle-state-pc", 69*4882a593Smuzhiyun and "arm,idle-state". 70*4882a593Smuzhiyun 71*4882a593SmuzhiyunOther required and optional properties are specified in [1]. 72*4882a593Smuzhiyun 73*4882a593SmuzhiyunExample: 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun idle-states { 76*4882a593Smuzhiyun CPU_SPC: spc { 77*4882a593Smuzhiyun compatible = "qcom,idle-state-spc", "arm,idle-state"; 78*4882a593Smuzhiyun entry-latency-us = <150>; 79*4882a593Smuzhiyun exit-latency-us = <200>; 80*4882a593Smuzhiyun min-residency-us = <2000>; 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun }; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun[1]. Documentation/devicetree/bindings/arm/idle-states.yaml 85