| /rk3399_rockchip-uboot/arch/powerpc/cpu/mpc83xx/ |
| H A D | serdes.c | 75 /* Configure SRDSCR0 */ in fsl_setup_serdes()
80 /* Configure SRDSCR1 */ in fsl_setup_serdes()
85 /* Configure SRDSCR2 */ in fsl_setup_serdes()
91 /* Configure SRDSCR3 */ in fsl_setup_serdes()
97 /* Configure SRDSCR4 */ in fsl_setup_serdes()
103 /* Configure SRDSCR1 */ in fsl_setup_serdes()
108 /* Configure SRDSCR2 */ in fsl_setup_serdes()
114 /* Configure SRDSCR3 */ in fsl_setup_serdes()
118 /* Configure SRDSCR4 */ in fsl_setup_serdes()
125 /* Configure SRDSCR1 */ in fsl_setup_serdes()
[all …]
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| /rk3399_rockchip-uboot/board/freescale/t102xrdb/ |
| H A D | t1024_pbi.cfg | 6 #Configure CPC1 as 256KB SRAM
11 #Configure LAW for CPC1
15 #Configure alternate space
19 #Configure SPI controller
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| /rk3399_rockchip-uboot/board/freescale/t102xqds/ |
| H A D | t1024_pbi.cfg | 6 #Configure CPC1 as 256KB SRAM
11 #Configure LAW for CPC1
15 #Configure alternate space
19 #Configure SPI controller
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| /rk3399_rockchip-uboot/board/freescale/t1040qds/ |
| H A D | t1040_pbi.cfg | 6 #Configure CPC1 as 256KB SRAM
11 #Configure LAW for CPC1
15 #Configure alternate space
19 #Configure SPI controller
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| /rk3399_rockchip-uboot/board/freescale/b4860qds/ |
| H A D | b4_pbi.cfg | 6 #Configure CPC1 as 512KB SRAM
11 #Configure LAW for CPC1
15 #Configure alternate space
19 #Configure SPI controller
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| /rk3399_rockchip-uboot/board/freescale/t104xrdb/ |
| H A D | t104x_pbi.cfg | 16 #Configure CPC1 as 256KB SRAM
21 #Configure LAW for CPC1
25 #Configure alternate space
29 #Configure SPI controller
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| H A D | t104x_pbi_sb.cfg | 16 #Configure CPC1 as 256KB SRAM
21 #Configure LAW for CPC1
25 #Configure alternate space
29 #Configure SPI controller
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| /rk3399_rockchip-uboot/board/freescale/c29xpcie/ |
| H A D | cpld.h | 28 u8 bootor; /* 0x17 - Boot configure override Register */
29 u8 bootcfg1; /* 0x18 - Boot configure 1 Register */
30 u8 bootcfg2; /* 0x19 - Boot configure 2 Register */
31 u8 bootcfg3; /* 0x1a - Boot configure 3 Register */
32 u8 bootcfg4; /* 0x1b - Boot configure 4 Register */
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| /rk3399_rockchip-uboot/drivers/ddr/marvell/axp/ |
| H A D | ddr3_dfs.c | 132 /* Configure - DRAM DLL final state after DFS is complete - Enable */ in ddr3_dfs_high_2_low()
139 * Configure - XBAR Retry response during Block to enable internal in ddr3_dfs_high_2_low()
148 /* Configure - Block new external transactions - Enable */ in ddr3_dfs_high_2_low()
156 * Configure - Disable Register DIMM CKE Power in ddr3_dfs_high_2_low()
162 * Configure - Disable Register DIMM CKE Power in ddr3_dfs_high_2_low()
169 * Configure - Disable Register DIMM CKE Power in ddr3_dfs_high_2_low()
174 /* Configure - Issue CWA command with the above parameters */ in ddr3_dfs_high_2_low()
187 /* Configure - Disable outputs floating during Self Refresh */ in ddr3_dfs_high_2_low()
195 /* Optional - Configure - DDR3_Rtt_nom_CS# */ in ddr3_dfs_high_2_low()
206 /* Configure - Move DRAM into Self Refresh */ in ddr3_dfs_high_2_low()
[all …]
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| /rk3399_rockchip-uboot/drivers/power/pmic/ |
| H A D | pmic_hi6553.c | 56 /* configure BUCK0 & BUCK1 */ in hi6553_init()
65 /* configure BUCK2 */ in hi6553_init()
73 /* configure BUCK3 */ in hi6553_init()
80 /* configure BUCK4 */ in hi6553_init()
85 /* configure LDO20 */ in hi6553_init()
93 /* configure LDO7 & LDO10 for SD slot */ in hi6553_init()
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| /rk3399_rockchip-uboot/arch/arm/mach-orion5x/ |
| H A D | cpu.c | 66 * orion5x_config_adr_windows - Configure address Windows
82 * first configure window 6 for BOOTCS, then configure window 7 for BOOTCS,
83 * then configure windows 6 for its own target.
94 /* Disable window 0, configure it for its intended target, enable it. */ in orion5x_config_adr_windows()
102 /* Disable window 1, configure it for its intended target, enable it. */ in orion5x_config_adr_windows()
110 /* Disable window 2, configure it for its intended target, enable it. */ in orion5x_config_adr_windows()
116 /* Disable window 3, configure it for its intended target, enable it. */ in orion5x_config_adr_windows()
122 /* Disable window 4, configure it for its intended target, enable it. */ in orion5x_config_adr_windows()
128 /* Disable window 5, configure it for its intended target, enable it. */ in orion5x_config_adr_windows()
134 /* Disable window 6, configure it for FLASH, enable it. */ in orion5x_config_adr_windows()
[all …]
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| /rk3399_rockchip-uboot/drivers/pinctrl/nxp/ |
| H A D | Kconfig | 16 property and configure related registers.
30 property and configure related registers.
44 property and configure related registers.
57 only parses the 'fsl,pins' property and configure related
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| /rk3399_rockchip-uboot/board/freescale/t208xqds/ |
| H A D | t208x_pbi.cfg | 6 # Refer doc/README.pblimage for more details about how-to configure
21 #Configure LAW for CPC1
35 #Configure alternate space
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| /rk3399_rockchip-uboot/board/freescale/t208xrdb/ |
| H A D | t2080_pbi.cfg | 6 # Refer doc/README.pblimage for more details about how-to configure
21 #Configure LAW for CPC1
35 #Configure alternate space
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| /rk3399_rockchip-uboot/arch/arm/cpu/armv7/s5p-common/ |
| H A D | sromc.c | 13 * s5p_config_sromc() - select the proper SROMC Bank and configure the
25 /* Configure SMC_BW register to handle proper SROMC bank */ in s5p_config_sromc()
31 /* Configure SMC_BC register */ in s5p_config_sromc()
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| /rk3399_rockchip-uboot/board/freescale/common/ |
| H A D | vsc3316_3308.c | 92 /* configure global core control register, Turn on Global core power */ in vsc3316_config()
134 /* Configure Global Input ISE */ in vsc3308_config_adjust()
138 /* Configure Tx/Rx Global Output PE1 */ in vsc3308_config_adjust()
141 /* Configure Tx/Rx Global Output PE2 */ in vsc3308_config_adjust()
144 /* Configure Tx/Rx Global Input GAIN */ in vsc3308_config_adjust()
153 /* Configure Tx/Rx Global Output level */ in vsc3308_config_adjust()
194 /* configure global core control register, Turn on Global core power */ in vsc3308_config_adjust()
241 /*Configure Global Input ISE and gain */ in vsc3308_config()
260 /* configure global core control register, Turn on Global core power */ in vsc3308_config()
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| /rk3399_rockchip-uboot/drivers/ddr/fsl/ |
| H A D | fsl_mmdc.c | 37 /* 2. configure the desired timing parameters */ in mmdc_init()
43 /* 3. configure DDR type and other miscellaneous parameters */ in mmdc_init()
49 /* 4. configure the required delay while leaving reset */ in mmdc_init()
52 /* 5. configure DDR physical parameters */ in mmdc_init()
56 /* configure address space partition */ in mmdc_init()
144 /* 10. configure power-down, self-refresh entry, exit parameters */ in mmdc_init()
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| /rk3399_rockchip-uboot/board/keymile/kmp204x/ |
| H A D | pbi.cfg | 6 # Refer docs/README.pblimage for more details about how-to configure
11 #Configure ALTCBAR for DCSR -> DCSR@89000000
60 #Configure LAW for CPC1
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| /rk3399_rockchip-uboot/board/keymile/scripts/ |
| H A D | README | 5 To load and configure these usecase, two environment variables in the u-boot
7 run develop : setup environment to configure for rootfs via nfs
8 run ramfs : setup environment to configure for rootfs in ram
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| /rk3399_rockchip-uboot/board/freescale/ls1021atwr/ |
| H A D | ls102xa_pbi.cfg | 7 #Configure Scratch register
9 #Configure alternate space
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| /rk3399_rockchip-uboot/board/freescale/ls1021aqds/ |
| H A D | ls102xa_pbi.cfg | 7 #Configure Scratch register
9 #Configure alternate space
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| /rk3399_rockchip-uboot/board/sunxi/ |
| H A D | gmac.c | 35 /* Configure pin mux settings for GMAC */ in eth_init_board()
46 /* Configure sun6i RGMII mode pin mux settings */ in eth_init_board()
64 /* Configure sun6i GMII mode pin mux settings */ in eth_init_board()
70 /* Configure sun6i MII mode pin mux settings */ in eth_init_board()
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| /rk3399_rockchip-uboot/board/freescale/ls1021aiot/ |
| H A D | ls102xa_pbi.cfg | 7 #Configure Scratch register
9 #Configure alternate space
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| /rk3399_rockchip-uboot/board/freescale/t4qds/ |
| H A D | t4_pbi.cfg | 12 #Configure LAW for CPC1
16 #Configure alternate space
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| /rk3399_rockchip-uboot/arch/x86/lib/ |
| H A D | pinctrl_ich6.c | 105 /* if iobase is present, let's configure the pad */ in ich6_pinctrl_cfg_pin()
132 /* Configure the pull-up/down if needed */ in ich6_pinctrl_cfg_pin()
169 * Get the memory/io base address to configure every pins. in ich6_pinctrl_probe()
170 * IOBASE is used to configure the mode/pads in ich6_pinctrl_probe()
171 * GPIOBASE is used to configure the direction and default value in ich6_pinctrl_probe()
193 /* Configure the pin */ in ich6_pinctrl_probe()
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