1877bfe37SValentin Longchamp# 2877bfe37SValentin Longchamp# Copyright 2012 Freescale Semiconductor, Inc. 3877bfe37SValentin Longchamp# 4877bfe37SValentin Longchamp# SPDX-License-Identifier: GPL-2.0+ 5877bfe37SValentin Longchamp# 6877bfe37SValentin Longchamp# Refer docs/README.pblimage for more details about how-to configure 7877bfe37SValentin Longchamp# and create PBL boot image 8877bfe37SValentin Longchamp# 9877bfe37SValentin Longchamp 10877bfe37SValentin Longchamp#PBI commands 11*2846c43eSValentin Longchamp#Configure ALTCBAR for DCSR -> DCSR@89000000 12*2846c43eSValentin Longchamp091380c0 000009C4 13fabb9297SValentin Longchamp09000010 00000000 14*2846c43eSValentin Longchamp091380c0 000009C4 15fabb9297SValentin Longchamp09000014 00000000 16*2846c43eSValentin Longchamp091380c0 000009C4 17fabb9297SValentin Longchamp09000018 81d00000 18*2846c43eSValentin Longchamp#Workaround for A-004849 19*2846c43eSValentin Longchamp091380c0 000009C4 20*2846c43eSValentin Longchamp890B0050 00000002 21*2846c43eSValentin Longchamp091380c0 000009C4 22*2846c43eSValentin Longchamp890B0054 00000002 23*2846c43eSValentin Longchamp091380c0 000009C4 24*2846c43eSValentin Longchamp890B0058 00000002 25*2846c43eSValentin Longchamp091380c0 000009C4 26*2846c43eSValentin Longchamp890B005C 00000002 27*2846c43eSValentin Longchamp091380c0 000009C4 28*2846c43eSValentin Longchamp890B0090 00000002 29*2846c43eSValentin Longchamp091380c0 000009C4 30*2846c43eSValentin Longchamp890B0094 00000002 31*2846c43eSValentin Longchamp091380c0 000009C4 32*2846c43eSValentin Longchamp890B0098 00000002 33*2846c43eSValentin Longchamp091380c0 000009C4 34*2846c43eSValentin Longchamp890B009C 00000002 35*2846c43eSValentin Longchamp091380c0 000009C4 36*2846c43eSValentin Longchamp890B0108 00000012 37*2846c43eSValentin Longchamp091380c0 000009C4 38*2846c43eSValentin Longchamp#Workaround for A-006559 needed for rev 2.0 of P2041 silicon 39*2846c43eSValentin Longchamp89021008 0000f000 40*2846c43eSValentin Longchamp091380c0 000009C4 41*2846c43eSValentin Longchamp89021028 0000f000 42*2846c43eSValentin Longchamp091380c0 000009C4 43*2846c43eSValentin Longchamp89021048 0000f000 44*2846c43eSValentin Longchamp091380c0 000009C4 45*2846c43eSValentin Longchamp89021068 0000f000 46*2846c43eSValentin Longchamp091380c0 000009C4 47*2846c43eSValentin Longchamp#Flush PBL data 48*2846c43eSValentin Longchamp09138000 00000000 49*2846c43eSValentin Longchamp#Disable ALTCBAR 50fabb9297SValentin Longchamp09000018 00000000 51*2846c43eSValentin Longchamp091380c0 000009C4 52877bfe37SValentin Longchamp#Initialize CPC1 as 1MB SRAM 53877bfe37SValentin Longchamp09010000 00200400 54877bfe37SValentin Longchamp09138000 00000000 55877bfe37SValentin Longchamp091380c0 00000100 56877bfe37SValentin Longchamp09010100 00000000 57877bfe37SValentin Longchamp09010104 fff0000b 58877bfe37SValentin Longchamp09010f00 08000000 59877bfe37SValentin Longchamp09010000 80000000 60877bfe37SValentin Longchamp#Configure LAW for CPC1 61877bfe37SValentin Longchamp09000d00 00000000 62877bfe37SValentin Longchamp09000d04 fff00000 63877bfe37SValentin Longchamp09000d08 81000013 64877bfe37SValentin Longchamp09000010 00000000 65877bfe37SValentin Longchamp09000014 ff000000 66877bfe37SValentin Longchamp09000018 81000000 67877bfe37SValentin Longchamp#Initialize eSPI controller, default configuration is slow for eSPI to 68877bfe37SValentin Longchamp#load data, this configuration comes from u-boot eSPI driver. 69877bfe37SValentin Longchamp09110000 80000403 70877bfe37SValentin Longchamp09110020 27170008 71877bfe37SValentin Longchamp09110024 00100008 72877bfe37SValentin Longchamp09110028 00100008 73877bfe37SValentin Longchamp0911002c 00100008 74877bfe37SValentin Longchamp#Flush PBL data 75877bfe37SValentin Longchamp09138000 00000000 76877bfe37SValentin Longchamp091380c0 00000000 77