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Searched refs:__BIT5 (Results 1 – 25 of 86) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/hwi2c/hal/k6lite/hwi2c/
H A DregHWI2C.h153 #define CHIP_REG_HWI2C_MIIC1_CLK_MSK (__BIT4 | __BIT5 | __BIT6 | __BIT7)
174 #define _MIIC_CFG_EN_FILTER (__BIT5)
198 #define _INT_SCLERR (__BIT5)
219 … #define _DMA_CTL_TXNOSTOP (__BIT5) //miic transfer format, 1: S+data..., 0: S+data...+P
257 #define _MIIC_CFG_EN_FILTER (__BIT5)
281 #define _INT_SCLERR (__BIT5)
302 … #define _DMA_CTL_TXNOSTOP (__BIT5) //miic transfer format, 1: S+data..., 0: S+data...+P
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/kano/hwi2c/
H A DregHWI2C.h153 #define CHIP_REG_HWI2C_MIIC1_CLK_MSK (__BIT4 | __BIT5 | __BIT6 | __BIT7)
174 #define _MIIC_CFG_EN_FILTER (__BIT5)
198 #define _INT_SCLERR (__BIT5)
219 … #define _DMA_CTL_TXNOSTOP (__BIT5) //miic transfer format, 1: S+data..., 0: S+data...+P
257 #define _MIIC_CFG_EN_FILTER (__BIT5)
281 #define _INT_SCLERR (__BIT5)
302 … #define _DMA_CTL_TXNOSTOP (__BIT5) //miic transfer format, 1: S+data..., 0: S+data...+P
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/k6/hwi2c/
H A DregHWI2C.h153 #define CHIP_REG_HWI2C_MIIC1_CLK_MSK (__BIT4 | __BIT5 | __BIT6 | __BIT7)
174 #define _MIIC_CFG_EN_FILTER (__BIT5)
198 #define _INT_SCLERR (__BIT5)
219 … #define _DMA_CTL_TXNOSTOP (__BIT5) //miic transfer format, 1: S+data..., 0: S+data...+P
257 #define _MIIC_CFG_EN_FILTER (__BIT5)
281 #define _INT_SCLERR (__BIT5)
302 … #define _DMA_CTL_TXNOSTOP (__BIT5) //miic transfer format, 1: S+data..., 0: S+data...+P
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/curry/hwi2c/
H A DregHWI2C.h153 #define CHIP_REG_HWI2C_MIIC1_CLK_MSK (__BIT4 | __BIT5 | __BIT6 | __BIT7)
174 #define _MIIC_CFG_EN_FILTER (__BIT5)
198 #define _INT_SCLERR (__BIT5)
219 … #define _DMA_CTL_TXNOSTOP (__BIT5) //miic transfer format, 1: S+data..., 0: S+data...+P
257 #define _MIIC_CFG_EN_FILTER (__BIT5)
281 #define _INT_SCLERR (__BIT5)
302 … #define _DMA_CTL_TXNOSTOP (__BIT5) //miic transfer format, 1: S+data..., 0: S+data...+P
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/mustang/hwi2c/
H A DregHWI2C.h130 #define CHIP_MIIC2_PAD_2 (__BIT5)
131 #define CHIP_MIIC2_PAD_MSK (__BIT4|__BIT5)
169 #define _MIIC_CFG_EN_FILTER (__BIT5)
193 #define _INT_SCLERR (__BIT5)
215 … #define _DMA_CTL_TXNOSTOP (__BIT5) //miic transfer format, 1: S+data..., 0: S+data...+P
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/maldives/hwi2c/
H A DregHWI2C.h130 #define CHIP_MIIC2_PAD_2 (__BIT5)
131 #define CHIP_MIIC2_PAD_MSK (__BIT4|__BIT5)
169 #define _MIIC_CFG_EN_FILTER (__BIT5)
193 #define _INT_SCLERR (__BIT5)
215 … #define _DMA_CTL_TXNOSTOP (__BIT5) //miic transfer format, 1: S+data..., 0: S+data...+P
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/manhattan/hwi2c/
H A DregHWI2C.h171 #define _MIIC_CFG_EN_FILTER (__BIT5)
195 #define _INT_SCLERR (__BIT5)
213 #define _ADV_B2STOP_DELAY (__BIT5)
235 … #define _DMA_CTL_TXNOSTOP (__BIT5) //miic transfer format, 1: S+data..., 0: S+data...+P
263 #define _DMA_RESERV_CTL (__BIT4 |__BIT5 |__BIT6 |__BIT7)
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/M7821/hwi2c/
H A DregHWI2C.h171 #define _MIIC_CFG_EN_FILTER (__BIT5)
195 #define _INT_SCLERR (__BIT5)
213 #define _ADV_B2STOP_DELAY (__BIT5)
235 … #define _DMA_CTL_TXNOSTOP (__BIT5) //miic transfer format, 1: S+data..., 0: S+data...+P
263 #define _DMA_RESERV_CTL (__BIT4 |__BIT5 |__BIT6 |__BIT7)
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/maserati/hwi2c/
H A DregHWI2C.h171 #define _MIIC_CFG_EN_FILTER (__BIT5)
195 #define _INT_SCLERR (__BIT5)
213 #define _ADV_B2STOP_DELAY (__BIT5)
235 … #define _DMA_CTL_TXNOSTOP (__BIT5) //miic transfer format, 1: S+data..., 0: S+data...+P
263 #define _DMA_RESERV_CTL (__BIT4 |__BIT5 |__BIT6 |__BIT7)
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/M7621/hwi2c/
H A DregHWI2C.h171 #define _MIIC_CFG_EN_FILTER (__BIT5)
195 #define _INT_SCLERR (__BIT5)
213 #define _ADV_B2STOP_DELAY (__BIT5)
235 … #define _DMA_CTL_TXNOSTOP (__BIT5) //miic transfer format, 1: S+data..., 0: S+data...+P
263 #define _DMA_RESERV_CTL (__BIT4 |__BIT5 |__BIT6 |__BIT7)
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/maxim/hwi2c/
H A DregHWI2C.h171 #define _MIIC_CFG_EN_FILTER (__BIT5)
195 #define _INT_SCLERR (__BIT5)
213 #define _ADV_B2STOP_DELAY (__BIT5)
235 … #define _DMA_CTL_TXNOSTOP (__BIT5) //miic transfer format, 1: S+data..., 0: S+data...+P
263 #define _DMA_RESERV_CTL (__BIT4 |__BIT5 |__BIT6 |__BIT7)
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k7u/nsk2/
H A DregEMMflt.h111 #define __BIT5 __BIT(5) macro
231 #define EMM_STR2MIU_PAUSE __BIT5
255 #define REG_STR2MI_WP_LD __BIT5
271 #define REG_P_SEL2 __BIT5
H A DregNSK2.h111 #define __BIT5 __BIT(5) macro
161 #define NSK2_INT_HANG __BIT5
197 #define NI_NSK2_RANDOM_ONEBYONE __BIT5
275 #define NI_SLOW_CLOCK_DETECT __BIT5
/utopia/UTPA2-700.0.x/modules/dscmb/hal/curry/nsk2/
H A DregEMMflt.h111 #define __BIT5 __BIT(5) macro
231 #define EMM_STR2MIU_PAUSE __BIT5
255 #define REG_STR2MI_WP_LD __BIT5
271 #define REG_P_SEL2 __BIT5
H A DregNSK2.h111 #define __BIT5 __BIT(5) macro
159 #define NSK2_INT_HANG __BIT5
195 #define NI_NSK2_RANDOM_ONEBYONE __BIT5
270 #define NI_SLOW_CLOCK_DETECT __BIT5
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6/nsk2/
H A DregEMMflt.h111 #define __BIT5 __BIT(5) macro
231 #define EMM_STR2MIU_PAUSE __BIT5
255 #define REG_STR2MI_WP_LD __BIT5
271 #define REG_P_SEL2 __BIT5
H A DregNSK2.h111 #define __BIT5 __BIT(5) macro
161 #define NSK2_INT_HANG __BIT5
197 #define NI_NSK2_RANDOM_ONEBYONE __BIT5
275 #define NI_SLOW_CLOCK_DETECT __BIT5
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6lite/nsk2/
H A DregEMMflt.h111 #define __BIT5 __BIT(5) macro
231 #define EMM_STR2MIU_PAUSE __BIT5
255 #define REG_STR2MI_WP_LD __BIT5
271 #define REG_P_SEL2 __BIT5
H A DregNSK2.h111 #define __BIT5 __BIT(5) macro
161 #define NSK2_INT_HANG __BIT5
197 #define NI_NSK2_RANDOM_ONEBYONE __BIT5
275 #define NI_SLOW_CLOCK_DETECT __BIT5
/utopia/UTPA2-700.0.x/modules/dscmb/hal/kano/nsk2/
H A DregEMMflt.h111 #define __BIT5 __BIT(5) macro
231 #define EMM_STR2MIU_PAUSE __BIT5
255 #define REG_STR2MI_WP_LD __BIT5
271 #define REG_P_SEL2 __BIT5
H A DregNSK2.h111 #define __BIT5 __BIT(5) macro
160 #define NSK2_INT_HANG __BIT5
196 #define NI_NSK2_RANDOM_ONEBYONE __BIT5
274 #define NI_SLOW_CLOCK_DETECT __BIT5
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/mainz/hwi2c/
H A DregHWI2C.h149 #define _MIIC_CFG_EN_FILTER (__BIT5)
173 #define _INT_SCLERR (__BIT5)
195 … #define _DMA_CTL_TXNOSTOP (__BIT5) //miic transfer format, 1: S+data..., 0: S+data...+P
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/mooney/hwi2c/
H A DregHWI2C.h171 #define _MIIC_CFG_EN_FILTER (__BIT5)
195 #define _INT_SCLERR (__BIT5)
217 … #define _DMA_CTL_TXNOSTOP (__BIT5) //miic transfer format, 1: S+data..., 0: S+data...+P
/utopia/UTPA2-700.0.x/modules/ir_tx/hal/k6lite/ir_tx/
H A Dreg_IR_TX.h7 #define __BIT5 __BIT(5UL) macro
112 #define IR_TX_Unit02_L __BIT5
129 #define IR_TX_Unit10_L __BIT5
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/messi/hwi2c/
H A DregHWI2C.h171 #define _MIIC_CFG_EN_FILTER (__BIT5)
195 #define _INT_SCLERR (__BIT5)
217 … #define _DMA_CTL_TXNOSTOP (__BIT5) //miic transfer format, 1: S+data..., 0: S+data...+P

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