Searched refs:TSP_HW_PVR_BUF_TAIL21_MASK (Results 1 – 19 of 19) sorted by relevance
393 #define TSP_HW_PVR_BUF_TAIL21_MASK 0x0000FFFFUL macro
386 #define TSP_HW_PVR_BUF_TAIL21_MASK 0x0000FFFFUL macro
440 #define TSP_HW_PVR_BUF_TAIL21_MASK 0x000007FF macro
1491 REG16_T(ADDR_PVR_TAIL21)= (u32BufEnd>> (MIU_BUS+ 16)) & TSP_HW_PVR_BUF_TAIL21_MASK; in HAL_TSP_PVR_SetBuffer()
441 #define TSP_HW_PVR_BUF_TAIL21_MASK 0x000007FFUL macro
1538 …)= (MS_U16)(((phyBufEnd-_phyPVRBufMiuOffset[0])>> (MIU_BUS+ 16UL)) & TSP_HW_PVR_BUF_TAIL21_MASK); in HAL_TSP_PVR_SetBuffer()
432 #define TSP_HW_PVR_BUF_TAIL21_MASK 0x000007FFUL macro
1520 …)= (MS_U16)(((phyBufEnd-_phyPVRBufMiuOffset[0])>> (MIU_BUS+ 16UL)) & TSP_HW_PVR_BUF_TAIL21_MASK); in HAL_TSP_PVR_SetBuffer()
454 #define TSP_HW_PVR_BUF_TAIL21_MASK 0x00000FFFUL macro
1487 …)= (MS_U16)(((phyBufEnd-_phyPVRBufMiuOffset[0])>> (MIU_BUS+ 16UL)) & TSP_HW_PVR_BUF_TAIL21_MASK); in HAL_TSP_PVR_SetBuffer()
456 #define TSP_HW_PVR_BUF_TAIL21_MASK 0x00000FFFUL macro
1560 …)= (MS_U16)(((phyBufEnd-_phyPVRBufMiuOffset[0])>> (MIU_BUS+ 16UL)) & TSP_HW_PVR_BUF_TAIL21_MASK); in HAL_TSP_PVR_SetBuffer()
463 #define TSP_HW_PVR_BUF_TAIL21_MASK 0x000007FFUL macro
1617 …)= (MS_U16)(((phyBufEnd-_phyPVRBufMiuOffset[0])>> (MIU_BUS+ 16UL)) & TSP_HW_PVR_BUF_TAIL21_MASK); in HAL_TSP_PVR_SetBuffer()
1578 …)= (MS_U16)(((phyBufEnd-_phyPVRBufMiuOffset[0])>> (MIU_BUS+ 16UL)) & TSP_HW_PVR_BUF_TAIL21_MASK); in HAL_TSP_PVR_SetBuffer()