Searched refs:TSP_HW_PVR_BUF_HEAD21_MASK (Results 1 – 19 of 19) sorted by relevance
383 #define TSP_HW_PVR_BUF_HEAD21_MASK 0x0000FFFFUL macro
376 #define TSP_HW_PVR_BUF_HEAD21_MASK 0x0000FFFFUL macro
428 #define TSP_HW_PVR_BUF_HEAD21_MASK 0x000007FF macro
1489 REG16_T(ADDR_PVR_HEAD21)= (u32BufStart1>> (MIU_BUS+ 16)) & TSP_HW_PVR_BUF_HEAD21_MASK; in HAL_TSP_PVR_SetBuffer()
429 #define TSP_HW_PVR_BUF_HEAD21_MASK 0x000007FFUL macro
1536 … (MS_U16)(((phyBufStart1-_phyPVRBufMiuOffset[0])>> (MIU_BUS+ 16UL)) & TSP_HW_PVR_BUF_HEAD21_MASK); in HAL_TSP_PVR_SetBuffer()
420 #define TSP_HW_PVR_BUF_HEAD21_MASK 0x000007FFUL macro
1518 … (MS_U16)(((phyBufStart1-_phyPVRBufMiuOffset[0])>> (MIU_BUS+ 16UL)) & TSP_HW_PVR_BUF_HEAD21_MASK); in HAL_TSP_PVR_SetBuffer()
442 #define TSP_HW_PVR_BUF_HEAD21_MASK 0x00000FFFUL macro
1485 … (MS_U16)(((phyBufStart1-_phyPVRBufMiuOffset[0])>> (MIU_BUS+ 16UL)) & TSP_HW_PVR_BUF_HEAD21_MASK); in HAL_TSP_PVR_SetBuffer()
444 #define TSP_HW_PVR_BUF_HEAD21_MASK 0x00000FFFUL macro
1558 … (MS_U16)(((phyBufStart1-_phyPVRBufMiuOffset[0])>> (MIU_BUS+ 16UL)) & TSP_HW_PVR_BUF_HEAD21_MASK); in HAL_TSP_PVR_SetBuffer()
451 #define TSP_HW_PVR_BUF_HEAD21_MASK 0x000007FFUL macro
1615 … (MS_U16)(((phyBufStart1-_phyPVRBufMiuOffset[0])>> (MIU_BUS+ 16UL)) & TSP_HW_PVR_BUF_HEAD21_MASK); in HAL_TSP_PVR_SetBuffer()
1576 … (MS_U16)(((phyBufStart1-_phyPVRBufMiuOffset[0])>> (MIU_BUS+ 16UL)) & TSP_HW_PVR_BUF_HEAD21_MASK); in HAL_TSP_PVR_SetBuffer()