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Searched refs:RIU (Results 1 – 25 of 99) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/usb/drv/usbhost/include/
H A DdrvGlobal.h143 RIU[u32Reg] : __MDrv_Read2Byte( u32Reg ))
152 value = ((U32)RIU[(u32Reg) + 2] << 16) | RIU[u32Reg]; \
194 RIU[u32Reg] = u16Val; \
209 RIU[u32Reg] = (U16)(u32Val); \
210 RIU[(u32Reg) + 2] = (U16)((u32Val) >> 16); \
/utopia/UTPA2-700.0.x/modules/mbx/hal/manhattan/mbx/
H A DregMBXINT.h116 #define RIU ((MS_U16 volatile *) RIU_MAP) macro
126 #define FIQ_REG(address) RIU[address*2+REG_FIQ_MASK_BASE]
159 #define CPU_INT_REG(address) RIU[address*2+REG_CPU_INT_BASE]
189 #define FIQ_FRCREG(address) RIU[address*2+REG_FRC_FIQ_MASK_BASE]
205 #define FRC_CPU_INT_REG(address) RIU[address*2+REG_FRC_CPUINT_BASE]
/utopia/UTPA2-700.0.x/modules/mbx/hal/macan/mbx/
H A DregMBXINT.h116 #define RIU ((MS_U16 volatile *) RIU_MAP) macro
126 #define FIQ_REG(address) RIU[address*2+REG_FIQ_MASK_BASE]
159 #define CPU_INT_REG(address) RIU[address*2+REG_CPU_INT_BASE]
189 #define FIQ_FRCREG(address) RIU[address*2+REG_FRC_FIQ_MASK_BASE]
205 #define FRC_CPU_INT_REG(address) RIU[address*2+REG_FRC_CPUINT_BASE]
/utopia/UTPA2-700.0.x/modules/mbx/hal/M7621/mbx/
H A DregMBXINT.h116 #define RIU ((MS_U16 volatile *) RIU_MAP) macro
127 #define FIQ_REG(address) RIU[address*2+REG_FIQ_MASK_BASE]
161 #define CPU_INT_REG(address) RIU[address*2+REG_CPU_INT_BASE]
193 #define FIQ_FRCREG(address) RIU[address*2+REG_FRC_FIQ_MASK_BASE]
210 #define FRC_CPU_INT_REG(address) RIU[address*2+REG_FRC_CPUINT_BASE]
/utopia/UTPA2-700.0.x/modules/mbx/hal/maserati/mbx/
H A DregMBXINT.h116 #define RIU ((MS_U16 volatile *) RIU_MAP) macro
126 #define FIQ_REG(address) RIU[address*2+REG_FIQ_MASK_BASE]
159 #define CPU_INT_REG(address) RIU[address*2+REG_CPU_INT_BASE]
189 #define FIQ_FRCREG(address) RIU[address*2+REG_FRC_FIQ_MASK_BASE]
205 #define FRC_CPU_INT_REG(address) RIU[address*2+REG_FRC_CPUINT_BASE]
/utopia/UTPA2-700.0.x/modules/mbx/hal/maxim/mbx/
H A DregMBXINT.h116 #define RIU ((MS_U16 volatile *) RIU_MAP) macro
126 #define FIQ_REG(address) RIU[address*2+REG_FIQ_MASK_BASE]
159 #define CPU_INT_REG(address) RIU[address*2+REG_CPU_INT_BASE]
189 #define FIQ_FRCREG(address) RIU[address*2+REG_FRC_FIQ_MASK_BASE]
205 #define FRC_CPU_INT_REG(address) RIU[address*2+REG_FRC_CPUINT_BASE]
/utopia/UTPA2-700.0.x/modules/mbx/hal/M7821/mbx/
H A DregMBXINT.h116 #define RIU ((MS_U16 volatile *) RIU_MAP) macro
127 #define FIQ_REG(address) RIU[address*2+REG_FIQ_MASK_BASE]
161 #define CPU_INT_REG(address) RIU[address*2+REG_CPU_INT_BASE]
193 #define FIQ_FRCREG(address) RIU[address*2+REG_FRC_FIQ_MASK_BASE]
210 #define FRC_CPU_INT_REG(address) RIU[address*2+REG_FRC_CPUINT_BASE]
/utopia/UTPA2-700.0.x/modules/graphic/hal/mustang/ge/
H A DregGE.h128 #define RIU ((unsigned short volatile *) RIU_MAP) macro
137 #define MIU1_REG(addr) RIU[ (((addr)*2) + 0x600)]
138 #define GE_REG(addr) RIU[ (((addr)*2) + 0x2800)]
140 #define GE1_REG(addr) RIU[ (((addr)*2) + GE1_BANK_NUM)]
141 #define GE2_REG(addr) RIU[ (((addr)*2) + 0x62800)]
142 #define INTR_CTNL_BK(addr) RIU[ (((addr)*2) + 0x1900) ]
/utopia/UTPA2-700.0.x/modules/graphic/hal/maldives/ge/
H A DregGE.h128 #define RIU ((unsigned short volatile *) RIU_MAP) macro
137 #define MIU1_REG(addr) RIU[ (((addr)*2) + 0x600)]
138 #define GE_REG(addr) RIU[ (((addr)*2) + 0x2800)]
140 #define GE1_REG(addr) RIU[ (((addr)*2) + GE1_BANK_NUM)]
141 #define GE2_REG(addr) RIU[ (((addr)*2) + 0x62800)]
142 #define INTR_CTNL_BK(addr) RIU[ (((addr)*2) + 0x1900) ]
/utopia/UTPA2-700.0.x/modules/graphic/hal/mooney/ge/
H A DregGE.h128 #define RIU ((unsigned short volatile *) RIU_MAP) macro
137 #define MIU1_REG(addr) RIU[ (((addr)*2) + 0x600UL)]
138 #define GE_REG(addr) RIU[ (((addr)*2) + 0x2800UL)]
139 #define GE2_REG(addr) RIU[ (((addr)*2) + 0x62800UL)]
140 #define CLK_REG(addr) RIU[ (((addr)*2) + 0x0B00UL)]
/utopia/UTPA2-700.0.x/modules/graphic/hal/maserati/ge/
H A DregGE.h128 #define RIU ((unsigned short volatile *) RIU_MAP) macro
137 #define MIU1_REG(addr) RIU[ (((addr)*2) + 0x600UL)]
138 #define GE_REG(addr) RIU[ (((addr)*2) + 0x2800UL)]
139 #define GE1_REG(addr) RIU[ (((addr)*2) + 0x10700UL)]
140 #define CLK_REG(addr) RIU[ (((addr)*2) + 0x0B00UL)]
/utopia/UTPA2-700.0.x/modules/graphic/hal/M7821/ge/
H A DregGE.h128 #define RIU ((unsigned short volatile *) RIU_MAP) macro
137 #define MIU1_REG(addr) RIU[ (((addr)*2) + 0x600UL)]
138 #define GE_REG(addr) RIU[ (((addr)*2) + 0x2800UL)]
139 #define GE1_REG(addr) RIU[ (((addr)*2) + 0x10700UL)]
140 #define CLK_REG(addr) RIU[ (((addr)*2) + 0x0B00UL)]
/utopia/UTPA2-700.0.x/modules/graphic/hal/messi/ge/
H A DregGE.h128 #define RIU ((unsigned short volatile *) RIU_MAP) macro
137 #define MIU1_REG(addr) RIU[ (((addr)*2) + 0x600UL)]
138 #define GE_REG(addr) RIU[ (((addr)*2) + 0x2800UL)]
139 #define GE2_REG(addr) RIU[ (((addr)*2) + 0x62800UL)]
140 #define CLK_REG(addr) RIU[ (((addr)*2) + 0x0B00UL)]
/utopia/UTPA2-700.0.x/modules/graphic/hal/mainz/ge/
H A DregGE.h128 #define RIU ((unsigned short volatile *) RIU_MAP) macro
137 #define MIU1_REG(addr) RIU[ (((addr)*2) + 0x600UL)]
138 #define GE_REG(addr) RIU[ (((addr)*2) + 0x2800UL)]
139 #define GE2_REG(addr) RIU[ (((addr)*2) + 0x62800UL)]
140 #define CLK_REG(addr) RIU[ (((addr)*2) + 0x0B00UL)]
/utopia/UTPA2-700.0.x/modules/graphic/hal/macan/ge/
H A DregGE.h128 #define RIU ((unsigned short volatile *) RIU_MAP) macro
137 #define MIU1_REG(addr) RIU[ (((addr)*2) + 0x600UL)]
138 #define GE_REG(addr) RIU[ (((addr)*2) + 0x2800UL)]
139 #define CLK_REG(addr) RIU[ (((addr)*2) + 0x0B00UL)]
/utopia/UTPA2-700.0.x/modules/graphic/hal/curry/ge/
H A DregGE.h128 #define RIU ((unsigned short volatile *) RIU_MAP) macro
137 #define MIU1_REG(addr) RIU[ (((addr)*2) + 0x600UL)]
138 #define GE_REG(addr) RIU[ (((addr)*2) + 0x2800UL)]
139 #define CLK_REG(addr) RIU[ (((addr)*2) + 0x0B00UL)]
/utopia/UTPA2-700.0.x/modules/graphic/hal/k6lite/ge/
H A DregGE.h128 #define RIU ((unsigned short volatile *) RIU_MAP) macro
137 #define MIU1_REG(addr) RIU[ (((addr)*2) + 0x600UL)]
138 #define GE_REG(addr) RIU[ (((addr)*2) + 0x2800UL)]
139 #define CLK_REG(addr) RIU[ (((addr)*2) + 0x0B00UL)]
/utopia/UTPA2-700.0.x/modules/graphic/hal/kano/ge/
H A DregGE.h128 #define RIU ((unsigned short volatile *) RIU_MAP) macro
137 #define MIU1_REG(addr) RIU[ (((addr)*2) + 0x600UL)]
138 #define GE_REG(addr) RIU[ (((addr)*2) + 0x2800UL)]
139 #define CLK_REG(addr) RIU[ (((addr)*2) + 0x0B00UL)]
/utopia/UTPA2-700.0.x/modules/graphic/hal/maxim/ge/
H A DregGE.h128 #define RIU ((unsigned short volatile *) RIU_MAP) macro
137 #define MIU1_REG(addr) RIU[ (((addr)*2) + 0x600UL)]
138 #define GE_REG(addr) RIU[ (((addr)*2) + 0x2800UL)]
139 #define CLK_REG(addr) RIU[ (((addr)*2) + 0x0B00UL)]
/utopia/UTPA2-700.0.x/modules/graphic/hal/manhattan/ge/
H A DregGE.h128 #define RIU ((unsigned short volatile *) RIU_MAP) macro
137 #define MIU1_REG(addr) RIU[ (((addr)*2) + 0x600UL)]
138 #define GE_REG(addr) RIU[ (((addr)*2) + 0x2800UL)]
139 #define CLK_REG(addr) RIU[ (((addr)*2) + 0x0B00UL)]
/utopia/UTPA2-700.0.x/modules/graphic/hal/k6/ge/
H A DregGE.h128 #define RIU ((unsigned short volatile *) RIU_MAP) macro
137 #define MIU1_REG(addr) RIU[ (((addr)*2) + 0x600UL)]
138 #define GE_REG(addr) RIU[ (((addr)*2) + 0x2800UL)]
139 #define CLK_REG(addr) RIU[ (((addr)*2) + 0x0B00UL)]
/utopia/UTPA2-700.0.x/modules/graphic/hal/M7621/ge/
H A DregGE.h128 #define RIU ((unsigned short volatile *) RIU_MAP) macro
137 #define MIU1_REG(addr) RIU[ (((addr)*2) + 0x600UL)]
138 #define GE_REG(addr) RIU[ (((addr)*2) + 0x2800UL)]
139 #define CLK_REG(addr) RIU[ (((addr)*2) + 0x0B00UL)]
/utopia/UTPA2-700.0.x/modules/graphic/hal/kastor/ge/
H A DregGE.h128 #define RIU ((unsigned short volatile *) RIU_MAP) macro
137 #define MIU1_REG(addr) RIU[ (((addr)*2) + 0x600UL)]
138 #define GE_REG(addr) RIU[ (((addr)*2) + 0x2800UL)]
139 #define CLK_REG(addr) RIU[ (((addr)*2) + 0x0B00UL)]
/utopia/UTPA2-700.0.x/modules/mbx/hal/mainz/mbx/
H A DregMBXINT.h91 #define RIU ((MS_U16 volatile *) RIU_MAP) macro
101 #define FIQ_REG(address) RIU[address*2+REG_FIQ_MASK_BASE]
134 #define CPU_INT_REG(address) RIU[address*2+REG_CPU_INT_BASE]
/utopia/UTPA2-700.0.x/modules/mbx/hal/maldives/mbx/
H A DregMBXINT.h91 #define RIU ((unsigned short volatile *) RIU_MAP) macro
101 #define FIQ_REG(address) RIU[address*2+REG_FIQ_MASK_BASE]
137 #define CPU_INT_REG(address) RIU[address*2+REG_CPU_INT_BASE]

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