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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 /////////////////////////////////////////////////////////////////////////////////////////////////// 96 /// 97 /// file regGE.h 98 /// @brief GE Module Register Definition 99 /// @author MStar Semiconductor Inc. 100 /////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _REG_GE_H_ 103 #define _REG_GE_H_ 104 105 //#include "regCHIP.h" 106 107 //------------------------------------------------------------------------------------------------- 108 // Hardware Capability 109 //------------------------------------------------------------------------------------------------- 110 111 #define EUCLID_BRINGUP 1 //[EUCLID] BRINGUP will remove after bringup 112 //------------------------------------------------------------------------------------------------- 113 // Macro and Define 114 //------------------------------------------------------------------------------------------------- 115 #if defined (__aeon__) 116 #define RIU_MAP pGEHalLocal->va_mmio_base 117 #else 118 #define RIU_MAP pGEHalLocal->va_mmio_base 119 #endif 120 /* Chip Reversion*/ 121 #define CHIP_REG_BASE 0x1E00UL // 0x1E00 - 0x1EFF 122 #define CHIP_CLK_BASE 0x0B00UL // 0x1E00 - 0x1EFF 123 #define GHIP_REVERSION (0x02UL) 124 #define CHIP_GE_CLK (0x48UL) 125 #define MIU1_REG_BASE 0x0600UL 126 #define MIU_SELETE_OFFSET 31UL 127 128 #define RIU ((unsigned short volatile *) RIU_MAP) 129 #define RIU8 ((unsigned char volatile *) RIU_MAP) 130 131 #define REG8(a) RIU8[((a) * 2) - ((a) & 1)] 132 133 #define REG_GE_BASE (0xBF800000UL+(0x1400UL<<2)) // 0xbf805000 134 //#define GE_REG(addr) (*((volatile MS_U16*)(REG_GE_BASE + ((addr)<<2)))) 135 #define MIU1_GEGROUP 0x7CUL 136 #define MIU1_GE_CLIENT BIT(1) 137 #define MIU1_REG(addr) RIU[ (((addr)*2) + 0x600UL)] 138 #define GE_REG(addr) RIU[ (((addr)*2) + 0x2800UL)] 139 #define CLK_REG(addr) RIU[ (((addr)*2) + 0x0B00UL)] 140 141 #define REG_GE_EN 0x0000UL 142 #define GE_EN_GE BIT(0) 143 #define GE_EN_DITHER BIT(1) 144 #define GE_EN_BLEND BIT(2) 145 #if (EUCLID_BRINGUP==1) 146 #define GE_EN_ASCK BIT(3) 147 #define GE_EN_DSCK BIT(4) 148 #endif 149 #define GE_EN_ROP2 BIT(5) 150 #define GE_EN_SCK BIT(6) 151 #define GE_EN_DCK BIT(7) 152 #define GE_EN_LINEPAT BIT(8) 153 #define GE_EN_DITHER_RAND BIT(9) //[OBERON] 154 #define GE_EN_DFB_BLD BIT(10) 155 #define GE_EN_ACMP BIT(11) 156 #define GE_EN_ATEST BIT(12) //[OBERON] 157 #define GE_EN_CALC_SRC_WH BIT(13) 158 #if (EUCLID_BRINGUP==1) 159 #define GE_EN_TRAP_SUB_CORR BIT(14) //[Euclid] 160 #endif 161 #define GE_EN_BURST BIT(14) 162 #define GE_EN_ONE_PIXEL_MODE BIT(15) //[OBERON] 163 #define REG_GE_CFG 0x0001UL 164 #define GE_CFG_CMDQ_MASK BMASK(3:0) 165 #define GE_CFG_CMDQ BIT(0) 166 #define GE_CFG_VCMDQ BIT(1) //[OBERON] 167 #define GE_CFG_RPRIO BIT(2) 168 169 #if (EUCLID_BRINGUP==1) 170 #define GE_CFG_DISABLE_MIU_ACS BIT(3) //[Euclid] 171 #else 172 #define GE_CFG_WPRIO BIT(3) 173 #endif 174 #define GE_CFG_BLT_STRETCH BIT(4) 175 #define GE_CFG_EN_CLIPCHK BIT(5) //[OBERON] hw patch for both start/end out of clipping window 176 #define GE_CFG_BLT_ITALIC BIT(6) 177 #define GE_CFG_LENGTH_LIMIT BIT(7) //[OBERON] burst length limit to 1 178 #define GE_CFG_SRC_TILE BIT(8) //[OBERON] source buffer tile mode 179 #define GE_CFG_DST_TILE BIT(9) //[OBERON] destination buffer tile mode 180 #define GE_CFG_MIU0_PROT BIT(10) //[OBERON] 181 #define GE_CFG_MIU1_PROT BIT(11) //[OBERON] 182 #define GE_CFG_RW_SPLIT BIT(14) //[OBERON] 183 #if (EUCLID_BRINGUP==1) 184 #define GE_CFG_CLR_MIU_FLG BIT(12) //[Euclid] 185 #define GE_CFG_EN_DNY_CLK_GATE BIT(15) //[Euclid] 186 #endif 187 #define REG_GE_DBG 0x0002UL 188 #if (EUCLID_BRINGUP==1) 189 #define GE_DBG_MIU_MAX_LEG BMASK(8:12) //[Euclid] 190 #define GE_DBG_POL_VAR_MODE BIT(14) //[Euclid] 191 #define GE_DBG_LEG_MODE BIT(15) //[Euclid] 192 #endif 193 194 #define REG_GE_TH 0x0003UL 195 #define GE_TH_STBB_MASK BMASK(3:0) 196 #define GE_TH_CMDQ_MASK BMASK(7:4) //[OBERON] 197 #define GE_TH_CMDQ2_MASK BMASK(11:8) //[OBERON] 198 #define REG_GE_VCMDQ_STAT 0x0004UL 199 #define REG_GE_BIST_STAT 0x0005UL 200 #define GE_VCMDQ_STAT_H_MASK BMASK(0:0) //[OBERON] virtual queue status [16] 201 #define GE_STAT_VCMDQ_MAX 131071UL 202 #define REG_GE_STAT 0x0007UL 203 #define GE_STAT_BUSY BIT(0) 204 #define GE_STAT_CMDQ2_MASK BMASK(7:3) 205 #define GE_STAT_CMDQ2_SHFT 3UL 206 #define GE_STAT_CMDQ2_MAX 16UL 207 #define GE_STAT_CMDQ_MASK BMASK(15:11) 208 #define GE_STAT_CMDQ_SHFT 11UL 209 #define GE_STAT_CMDQ_MAX 8UL 210 #define REG_GE_MIU_PROT_LTH_L(_miu) (0x0008UL+(_miu<<2)) 211 #define REG_GE_MIU_PROT_LTH_H(_miu) (0x0009UL+(_miu<<2)) 212 #define GE_MIU_PROT_LTH_H_MASK BMASK(10:0) 213 #define GE_MIU_PROT_MODE_MASK BIT(15) 214 #define GE_MIU_PROT_MODE_SHFT 15UL 215 #define GE_MIU_PROT_MODE_EQ BITS(15:15, 0) 216 #define GE_MIU_PROT_MODE_NE BITS(15:15, 1) 217 #define REG_GE_MIU_PROT_HTH_L(_miu) (0x000A+(_miu<<2)) 218 #define REG_GE_MIU_PROT_HTH_H(_miu) (0x000B+(_miu<<2)) 219 #define REG_GE_ROP2 0x0010UL 220 #define GE_ROP2_MASK BMASK(3:0) 221 #define REG_GE_BLEND 0x0011UL // source coefficient of alpha blending 222 #define GE_BLEND_MASK BMASK(3:0) 223 #define GE_BLEND_ONE BITS(3:0, 0) 224 #define GE_BLEND_CONST BITS(3:0, 1) 225 #define GE_BLEND_ASRC BITS(3:0, 2) 226 #define GE_BLEND_ADST BITS(3:0, 3) 227 #define GE_BLEND_ROP8_ALPHA BITS(3:0, 4) //[OBERON] 228 #define GE_BLEND_ROP8_SRCOVER BITS(3:0, 5) //[OBERON] 229 #define GE_BLEND_ROP8_DSTOVER BITS(3:0, 6) //[OBERON] 230 #if (EUCLID_BRINGUP==1) 231 #define GE_BLEND_ROP8_DSTNEW BITS(3:0, 7) //[Euclid] Csrc*Aconst 232 #endif 233 #define GE_BLEND_ZERO BITS(3:0, 8) 234 #define GE_BLEND_CONST_INV BITS(3:0, 9) 235 #define GE_BLEND_ASRC_INV BITS(3:0, 10) 236 #define GE_BLEND_ADST_INV1 BITS(3:0, 11) 237 #define GE_BLEND_ADST_INV2 BITS(3:0, 12) 238 #define GE_BLEND_ADST_INV3 BITS(3:0, 13) 239 #if (EUCLID_BRINGUP==1) 240 #define GE_BLEND_ADST_INV4 BITS(3:0, 14) //[Euclid] Csrc*Aconst 241 #define GE_BLEND_ADST_INV5 BITS(3:0, 15) //[Euclid] Csrc*Aconst 242 #endif 243 244 #define GE_ALPHA_ARGB1555 BMASK(15:8) //[OBERON] 245 #define REG_GE_ALPHA 0x0012UL 246 #define GE_ALPHA_MASK BMASK(12:8) 247 #define GE_ALPHA_SHFT 8UL 248 #define REG_GE_ALPHA_CONST 0x0013UL 249 #define GE_ALPHA_CONST_MASK BMASK(7:0) 250 #define GE_ALPHA_SRCMASK_MASK BMASK(15:8) 251 252 #define REG_GE_SCK_HTH_L 0x0014UL //ARGB8888(32), CrYCb, BLINK(16), I8(8) 253 #define REG_GE_SCK_HTH_H 0x0015UL // 254 #define REG_GE_SCK_LTH_L 0x0016UL //ARGB8888(32), CrYCb, BLINK(16), I8(8) 255 #define REG_GE_SCK_LTH_H 0x0017UL // 256 #define REG_GE_DCK_HTH_L 0x0018UL //ARGB8888(32), CrYCb, BLINK(16), I8(8) 257 #define REG_GE_DCK_HTH_H 0x0019UL // 258 #define REG_GE_DCK_LTH_L 0x001AUL //ARGB8888(32), CrYCb, BLINK(16), I8(8) 259 #define REG_GE_DCK_LTH_H 0x001BUL // 260 #define REG_GE_OP_MODE 0x001CUL 261 #define GE_OP_SCK_SHFT 0UL 262 #define GE_OP_SCK_NE BIT(0) // 263 #define GE_OP_DCK_SHFT 1UL 264 #define GE_OP_DCK_NE BIT(1) // 265 #define GE_OP_ACMP_SHFT 4UL 266 #define GE_OP_ACMP_MIN BIT(4) // MIN(Asrc,Adst) 267 #define GE_OP_ATEST_SHFT 5UL 268 #define GE_OP_ATEST_NE BIT(5) 269 #define GE_SRCCOLOR_MASK_B BMASK(15:8) 270 #define GE_SRCCOLOR_MASK_B_SHIFT 8UL 271 #define REG_GE_ATEST_TH 0x001DUL 272 #define GE_ATEST_HTH_MASK BMASK(7:0) 273 #define GE_ATEST_LTH_MASK BMASK(15:8) 274 #define REG_GE_SRCMASK_GB 0x001EUL 275 #define GE_SRCCOLOR_MASK_G BMASK(7:0) 276 #define GE_SRCCOLOR_MASK_G_SHIFT 0UL 277 #define GE_SRCCOLOR_MASK_R BMASK(15:8) 278 #define GE_SRCCOLOR_MASK_R_SHIFT 8UL 279 #define REG_GE_YUV_MODE 0x001FUL //[URANUS] write only 280 #define GE_FMT_YVYU 0UL 281 #define GE_FMT_YUYV 1UL 282 #define GE_FMT_VYUY 2UL 283 #define GE_FMT_UYVY 3UL 284 #define GE_YUV_RGB2YUV_MASK BMASK(1:0) 285 #define GE_YUV_RGB2YUV_SHFT 0UL 286 #define GE_YUV_RGB2YUV_PC BITS(1:0, 0) 287 #define GE_YUV_RGB2YUV_255 BITS(1:0, 1) 288 #define GE_YUV_OUT_RANGE_MASK BMASK(2) 289 #define GE_YUV_OUT_RANGE_SHFT 2UL 290 #define GE_YUV_OUT_255 BITS(2:2, 0) 291 #define GE_YUV_OUT_PC BITS(2:2, 1) 292 #define GE_YUV_IN_RANGE_MASK BMASK(3) 293 #define GE_YUV_IN_RANGE_SHFT 3UL 294 #define GE_YUV_IN_255 BITS(3:3, 0) 295 #define GE_YUV_IN_127 BITS(3:3, 1) 296 #define GE_YUV_SRC_YUV422_MASK BMASK(5:4) 297 #define GE_YUV_SRC_YUV422_SHFT 4UL 298 #define GE_YUV_SRC_YVYU BITS(5:4, GE_FMT_YVYU) // CbY1CrY0 299 #define GE_YUV_SRC_YUYV BITS(5:4, GE_FMT_YUYV) // CrY1CbY0 (ATI) 300 #define GE_YUV_SRC_VYUY BITS(5:4, GE_FMT_VYUY) // Y1CbY0Cr 301 #define GE_YUV_SRC_UYVY BITS(5:4, GE_FMT_UYVY) // Y1CrY0Cb 302 #define GE_YUV_DST_YUV422_MASK BMASK(7:6) 303 #define GE_YUV_DST_YUV422_SHFT 6UL 304 #define GE_YUV_DST_YVYU BITS(7:6, GE_FMT_YVYU) 305 #define GE_YUV_DST_YUYV BITS(7:6, GE_FMT_YUYV) 306 #define GE_YUV_DST_VYUY BITS(7:6, GE_FMT_VYUY) 307 #define GE_YUV_DST_UYVY BITS(7:6, GE_FMT_UYVY) 308 #define GE_YUV_CSC_MASK BMASK(7:0) 309 #define GE_SRC_BUFFER_MIU_H_SHFT 13UL 310 #define GE_DST_BUFFER_MIU_H_SHFT 14UL 311 #define GE_VCMQ_MIU_SEL_H BIT(15) 312 #define REG_GE_SRC_BASE_L 0x0020UL 313 #define REG_GE_SRC_BASE_H 0x0021UL 314 #if (EUCLID_BRINGUP==1) 315 #define GE_SB_MIU_SEL BIT(15) //[Euclid] Source Buffer MIU Selection 316 #endif 317 #define REG_GE_DST_BASE_L 0x0026UL 318 #define REG_GE_DST_BASE_H 0x0027UL 319 #if (EUCLID_BRINGUP==1) 320 #define GE_DB_MIU_SEL BIT(15) //[Euclid] Destination Buffer MIU Selection 321 #endif 322 323 #define REG_GE_VCMDQ_BASE_L 0x0028UL 324 #define REG_GE_VCMDQ_BASE_H 0x0029UL 325 #if (EUCLID_BRINGUP==1) 326 #define GE_VCMQ_MIU_SEL BIT(15) //[Euclid] Virtual Command Queue MIU Selection 327 #endif 328 329 #define REG_GE_VCMDQ_SIZE 0x002AUL 330 #define GE_VCMDQ_SIZE_MASK BMASK(2:0) 331 #define GE_VCMDQ_SIZE_MIN 0x00001000UL // 4KB 332 #define GE_VCMDQ_SIZE_MAX 0x00080000UL // 512KB 333 #define GE_VCMDQ_SIZE(_size) ( (_size>>19) ? 7 : \ 334 (_size>>18) ? 6 : \ 335 (_size>>17) ? 5 : \ 336 (_size>>16) ? 4 : \ 337 (_size>>15) ? 3 : \ 338 (_size>>14) ? 2 : \ 339 (_size>>13) ? 1 : 0 ) 340 #define REG_GE_DFB_BLD_OP 0x002AUL 341 #define GE_DFB_SRC_COLORMASK BIT(7) 342 #define GE_DFB_SRC_COLORMASK_SHIFT 7UL 343 #define GE_DFB_SRCBLD_OP_MASK BMASK(11:8) 344 #define GE_DFB_SRCBLD_OP_SHFT 8UL 345 #define GE_DFB_SRCBLD_OP_ZERO BITS(11:8, 0) 346 #define GE_DFB_SRCBLD_OP_ONE BITS(11:8, 1) 347 #define GE_DFB_SRCBLD_OP_SRCCOLOR BITS(11:8, 2) 348 #define GE_DFB_SRCBLD_OP_INVSRCCOLOR BITS(11:8, 3) 349 #define GE_DFB_SRCBLD_OP_SRCALPHA BITS(11:8, 4) 350 #define GE_DFB_SRCBLD_OP_INVSRCALPHA BITS(11:8, 5) 351 #define GE_DFB_SRCBLD_OP_DESTALPHA BITS(11:8, 6) 352 #define GE_DFB_SRCBLD_OP_INVDESTALPHA BITS(11:8, 7) 353 #define GE_DFB_SRCBLD_OP_DESTCOLOR BITS(11:8, 8) 354 #define GE_DFB_SRCBLD_OP_INVDESTCOLOR BITS(11:8, 9) 355 #define GE_DFB_SRCBLD_OP_SRCALPHASAT BITS(11:8, 10) 356 #define GE_DFB_DSTBLD_OP_MASK BMASK(15:12) 357 #define GE_DFB_DSTBLD_OP_SHFT 12UL 358 #define GE_DFB_DSTBLD_OP_ZERO BITS(15:12, 0) 359 #define GE_DFB_DSTBLD_OP_ONE BITS(15:12, 1) 360 #define GE_DFB_DSTBLD_OP_SRCCOLOR BITS(15:12, 2) 361 #define GE_DFB_DSTBLD_OP_INVSRCCOLOR BITS(15:12, 3) 362 #define GE_DFB_DSTBLD_OP_SRCALPHA BITS(15:12, 4) 363 #define GE_DFB_DSTBLD_OP_INVSRCALPHA BITS(15:12, 5) 364 #define GE_DFB_DSTBLD_OP_DESTALPHA BITS(15:12, 6) 365 #define GE_DFB_DSTBLD_OP_INVDESTALPHA BITS(15:12, 7) 366 #define GE_DFB_DSTBLD_OP_DESTCOLOR BITS(15:12, 8) 367 #define GE_DFB_DSTBLD_OP_INVDESTCOLOR BITS(15:12, 9) 368 #define GE_DFB_DSTBLD_OP_SRCALPHASAT BITS(15:12, 10) 369 #define REG_GE_DFB_BLD_FLAGS 0x002BUL 370 #define GE_DFB_BLD_FLAGS_MASK BMASK(7:0) 371 #define GE_DFB_BLD_FLAG_COLORALPHA BIT(0) 372 #define GE_DFB_BLD_FLAG_ALPHACHANNEL BIT(1) 373 #define GE_DFB_BLD_FLAG_COLORIZE BIT(2) 374 #define GE_DFB_BLD_FLAG_SRCPREMUL BIT(3) 375 #define GE_DFB_BLD_FLAG_SRCPREMULCOL BIT(4) 376 #define GE_DFB_BLD_FLAG_DSTPREMUL BIT(5) 377 #define GE_DFB_BLD_FLAG_XOR BIT(6) 378 #define GE_DFB_BLD_FLAG_DEMULTIPLY BIT(7) 379 #define REG_GE_B_CONST 0x002BUL 380 #define GE_B_CONST_MASK BMASK(15:8) 381 #define GE_B_CONST_SHIFT 8UL 382 #define REG_GE_G_CONST 0x002CUL 383 #define GE_G_CONST_MASK BMASK(7:0) 384 #define GE_G_CONST_SHIFT 0UL 385 #define REG_GE_R_CONST 0x002CUL 386 #define GE_R_CONST_MASK BMASK(15:8) 387 #define GE_R_CONST_SHIFT 8UL 388 #define REG_GE_CLUT_L 0x002DUL 389 #define REG_GE_CLUT_H 0x002EUL 390 #define REG_GE_CLUT_CTRL 0x002FUL 391 #define GE_CLUT_CTRL_IDX_MASK BMASK(7:0) 392 #define GE_CLUT_CTRL_RD BITS(8:8, 0) 393 #define GE_CLUT_CTRL_WR BITS(8:8, 1) 394 #define REG_GE_SRC_PITCH 0x0030UL 395 #define REG_GE_TAG 0x0032UL 396 #define REG_GE_DST_PITCH 0x0033UL 397 #define REG_GE_FMT 0x0034UL 398 #define GE_SRC_FMT_MASK BMASK(4:0) 399 #define GE_SRC_FMT_SHFT 0UL 400 #define GE_DST_FMT_MASK BMASK(12:8) 401 #define GE_DST_FMT_SHFT 8UL 402 #define REG_GE_C_L(_idx) (0x0035UL+(_idx<<1)) // [31:0]ARGB8888, [15:0]blink, [7:0]I8 403 #define REG_GE_C_H(_idx) (0x0036UL+(_idx<<1)) 404 #define REG_GE_CLIP_L 0x0055UL 405 #define REG_GE_CLIP_R 0x0056UL 406 #define REG_GE_CLIP_T 0x0057UL 407 #define REG_GE_CLIP_B 0x0058UL 408 #define REG_GE_ROT_MODE 0x0059UL 409 #define REG_GE_ROT_MODE_MASK BMASK(1:0) 410 #define REG_GE_ROT_MODE_SHFT 0UL 411 #define REG_GE_ROT_0 BITS(1:0, 0) 412 #define REG_GE_ROT_90 BITS(1:0, 1) 413 #define REG_GE_ROT_180 BITS(1:0, 2) 414 #define REG_GE_ROT_270 BITS(1:0, 3) 415 #if (EUCLID_BRINGUP==1) 416 #define GE_TRAP_DX1 BMASK(15:0) 417 #define REG_GE_BLT_SCK_MODE 0x0059UL 418 #define GE_BLT_SCK_MODE_MASK BMASK(7:6) 419 #define GE_BLT_SCK_BILINEAR BITS(7:6, 0) //[Euclid] Do nothing 420 #define GE_BLT_SCK_NEAREST BITS(7:6, 1) //[Euclid] NEAREST WHEN THE COLOR KEY HAPPENED 421 #define GE_BLT_SCK_CONST BITS(7:6, 2) //[Euclid] REPLACE THE KEY TO CUSTOM COLOR 422 #define GE_TRAP_DX0_MSB BMASK(9:8) 423 #define GE_TRAP_DX0_MSB_SHFT 8UL 424 #define GE_TRAP_DX1_MSB BMASK(13:12) 425 #define GE_TRAP_DX1_MSB_SHFT 12UL 426 427 #define REG_GE_TRAPEZOID_DX0 0x005AUL 428 #define GE_TRAP_DX0 BMASK(15:0) 429 #define REG_GE_TRAPEZOID_DX1 0x005BUL 430 #define GE_TRAP_DX1 BMASK(15:0) 431 #else 432 #define REG_GE_BLT_SCK_MODE 0x005BUL 433 #define GE_BLT_SCK_MODE_MASK BMASK(1:0) 434 #define GE_BLT_SCK_BILINEAR BITS(1:0, 0) 435 #define GE_BLT_SCK_NEAREST BITS(1:0, 1) 436 #define GE_BLT_SCK_CONST BITS(1:0, 2) // replace to const color 437 #endif 438 #define REG_GE_BLT_SCK_CONST_L 0x005CUL // GB 439 #define REG_GE_BLT_SCK_CONST_H 0x005DUL // R, Uranus doesn't have alpha key 440 #define REG_GE_BLT_DST_X_OFST 0x005EUL // (s.12) 441 #if (EUCLID_BRINGUP==1) 442 #define GE_STBB_DX_MSB BIT(15) 443 #define GE_STBB_DX_MSB_SHFT 15UL 444 #endif 445 #define REG_GE_BLT_DST_Y_OFST 0x005FUL // (s.12) 446 #if (EUCLID_BRINGUP==1) 447 #define GE_STBB_DY_MSB BIT(15) 448 #define GE_STBB_DY_MSB_SHFT 15UL 449 #endif 450 #define REG_GE_CMD 0x0060UL 451 #define GE_PRIM_TYPE_MASK BMASK(6:4) 452 #define GE_PRIM_LINE BITS(6:4, 1) 453 #if (EUCLID_BRINGUP==1) 454 #define GE_PRIM_TRAPEZOID BITS(6:4, 2) 455 #endif 456 #define GE_PRIM_RECT BITS(6:4, 3) 457 #define GE_PRIM_BITBLT BITS(6:4, 4) 458 #if (EUCLID_BRINGUP==1) 459 #define GE_PRIM_TRAPEZOID_BLT BITS(6:4, 5) 460 #endif 461 #define GE_SRC_DIR_X_INV BIT(7) 462 #define GE_SRC_DIR_Y_INV BIT(8) 463 #define GE_DST_DIR_X_INV BIT(9) 464 #define GE_DST_DIR_Y_INV BIT(10) 465 #define GE_LINE_GRADIENT BIT(11) 466 #define GE_RECT_GRADIENT_H BIT(12) 467 #define GE_RECT_GRADIENT_V BIT(13) 468 #define GE_STRETCH_BILINEAR BITS(14:14, 0) 469 #define GE_STRETCH_NEAREST BITS(14:14, 1) 470 #define GE_STRETCH_CLAMP BIT(15) 471 #define REG_GE_LINE_DELTA 0x0061UL 472 #define GE_LINE_DELTA_MASK BMASK(14:1) // (s1.12) minor direction delta value of line 473 #define GE_LINE_DELTA_SHFT 1UL 474 #define GE_LINE_MAJOR_X BITS(15:15, 0) 475 #define GE_LINE_MAJOR_Y BITS(15:15, 1) 476 #define REG_GE_LINE_STYLE 0x0062UL 477 #define GE_LINEPAT_MASK BMASK(5:0) 478 #define GE_LINEPAT_RST BIT(8) 479 #define GE_LINE_LAST BIT(9) 480 #define GE_LINEPAT_REP_MASK BMASK(7:6) 481 #define GE_LINEPAT_REP_SHFT 6UL 482 #define GE_LINEPAT_REP1 BITS(7:6, 0) 483 #define GE_LINEPAT_REP2 BITS(7:6, 1) 484 #define GE_LINEPAT_REP3 BITS(7:6, 2) 485 #define GE_LINEPAT_REP4 BITS(7:6, 3) 486 #define REG_GE_LINE_LENGTH 0x0063UL 487 #define GE_LINE_LENGTH_MASK BMASK(11:0) 488 #define REG_GE_BLT_SRC_DX 0x0064UL //[EUCLID] (5.12) 489 #define REG_GE_BLT_SRC_DY 0x0065UL //[EUCLID] (5.12) 490 #define GE_STBB_DXY_MASK BMASK(12:0) 491 #define REG_GE_ITALIC_OFFSET 0x0066UL 492 #define GE_ITALIC_X_MASK BMASK(7:0) 493 #define GE_ITALIC_X_SHFT 0UL 494 #define GE_ITALIC_Y_MASK BMASK(15:8) 495 #define GE_ITALIC_Y_SHFT 8UL 496 #define REG_GE_ITALIC_DELTA 0x0067UL 497 #define GE_ITALIC_D_MASK BMASK(7:0) // (s1.3) 498 #define GE_ITALIC_D_SHFT 0UL 499 #define REG_GE_PRIM_V0_X 0x0068UL //[EUCLID] COORDINATE X0 OF PRIMITIVE VERTEX 0 500 #define REG_GE_PRIM_V0_Y 0x0069UL //[EUCLID] COORDINATE Y0 OF PRIMITIVE VERTEX 0 501 #define REG_GE_PRIM_V1_X 0x006AUL //[EUCLID] COORDINATE X1 OF PRIMITIVE VERTEX 1 502 #define REG_GE_PRIM_V1_Y 0x006BUL //[EUCLID] COORDINATE Y1 OF PRIMITIVE VERTEX 1 503 #define REG_GE_PRIM_V2_X 0x006CUL 504 #define REG_GE_PRIM_V2_Y 0x006DUL 505 #define REG_GE_BLT_SRC_W 0x006EUL 506 #define REG_GE_BLT_SRC_H 0x006FUL 507 #define REG_GE_PRIM_C_L 0x0070UL // [L]:B,Bg(AXFB2355,AAFB2266),I8, [H]:G,Fg(AXFB2355,AAFB2266) 508 #define REG_GE_PRIM_C_H 0x0071UL // [L]:R,AX(AXFB2355),Ba(AAFB2266), [H]:A,1(AXFB2355),Fa(AAFB2266) 509 #define REG_GE_PRIM_RDX_L 0x0072UL // (s7.12) 510 #define REG_GE_PRIM_RDX_H 0x0073UL 511 #define REG_GE_PRIM_RDY_L 0x0074UL 512 #define REG_GE_PRIM_RDY_H 0x0075UL 513 #define REG_GE_PRIM_GDX_L 0x0076UL 514 #define REG_GE_PRIM_GDX_H 0x0077UL 515 #define REG_GE_PRIM_GDY_L 0x0078UL 516 #define REG_GE_PRIM_GDY_H 0x0079UL 517 #define REG_GE_PRIM_BDX_L 0x007AUL 518 #define REG_GE_PRIM_BDX_H 0x007BUL 519 #define REG_GE_PRIM_BDY_L 0x007CUL 520 #define REG_GE_PRIM_BDY_H 0x007DUL 521 #define REG_GE_PRIM_ADX 0x007EUL // (s4.11) 522 #define REG_GE_PRIM_ADY 0x007FUL 523 524 #define REG_GE_TLB_TYPE_EN 0x0000UL 525 #define GE_TLB_MODE_MASK BMASK(2:1) 526 #define GE_TLB_SRC BIT(1) 527 #define GE_TLB_DST BIT(2) 528 #define GE_TLB_FLUSH BIT(3) 529 530 #define REG_GE_TLB_EN 0x0001UL 531 #define GE_TLB_EN BIT(0) 532 533 #define REG_GE_TLB_TAG 0x0010UL 534 #define GE_TLB_TAG BMASK(5:0) 535 536 #define REG_GE_TLB_BASE_MIU_H 0x001FUL 537 #define GE_SB_TLB_SRC_MIU_SEL_H BIT(13) 538 #define GE_SB_TLB_DST_MIU_SEL_H BIT(14) 539 540 #define REG_GE_SRC_TLB_BASE_L 0x0020UL 541 #define REG_GE_SRC_TLB_BASE_H 0x0021UL 542 #define GE_SB_TLB_MIU_SEL BIT(15) 543 544 #define REG_GE_DST_TLB_BASE_L 0x0022UL 545 #define REG_GE_DST_TLB_BASE_H 0x0023UL 546 #define GE_DB_TLB_MIU_SEL BIT(15) 547 548 549 //------------------------------------------------------------------------------------------------- 550 // Type and Structure 551 //------------------------------------------------------------------------------------------------- 552 553 554 #endif // _REG_GE_H_ 555 556