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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 /////////////////////////////////////////////////////////////////////////////////////////////////// 96 /// 97 /// file regGE.h 98 /// @brief GE Module Register Definition 99 /// @author MStar Semiconductor Inc. 100 /////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _REG_GE_H_ 103 #define _REG_GE_H_ 104 105 //#include "regCHIP.h" 106 107 //------------------------------------------------------------------------------------------------- 108 // Hardware Capability 109 //------------------------------------------------------------------------------------------------- 110 111 #define EUCLID_BRINGUP 1 //[EUCLID] BRINGUP will remove after bringup 112 //------------------------------------------------------------------------------------------------- 113 // Macro and Define 114 //------------------------------------------------------------------------------------------------- 115 #if defined (__aeon__) 116 #define RIU_MAP pGEHalLocal->u32_mmio_base 117 #else 118 #define RIU_MAP pGEHalLocal->u32_mmio_base 119 #endif 120 /* Chip Reversion*/ 121 #define CHIP_REG_BASE 0x1E00 // 0x1E00 - 0x1EFF 122 #define CHIP_CLK_BASE 0x0B00 // 0x1E00 - 0x1EFF 123 #define GHIP_REVERSION (0x02) 124 #define CHIP_GE_CLK (0x2A) 125 #define MIU1_REG_BASE 0x0600 126 #define MIU_SELETE_OFFSET 31 127 128 #define RIU ((unsigned short volatile *) RIU_MAP) 129 #define RIU8 ((unsigned char volatile *) RIU_MAP) 130 131 #define REG8(a) RIU8[((a) * 2) - ((a) & 1)] 132 133 #define REG_GE_BASE (0xBF800000+(0x1400<<2)) // 0xbf805000 134 //#define GE_REG(addr) (*((volatile MS_U16*)(REG_GE_BASE + ((addr)<<2)))) 135 #define MIU1_GEGROUP 0x7B 136 #define MIU1_GE_CLIENT BIT(0) 137 #define MIU1_REG(addr) RIU[ (((addr)*2) + 0x600)] 138 #define GE_REG(addr) RIU[ (((addr)*2) + 0x2800)] 139 #define GE1_BANK_NUM 0x10700 140 #define GE1_REG(addr) RIU[ (((addr)*2) + GE1_BANK_NUM)] 141 #define GE2_REG(addr) RIU[ (((addr)*2) + 0x62800)] 142 #define INTR_CTNL_BK(addr) RIU[ (((addr)*2) + 0x1900) ] 143 144 #define REG_GE_EN 0x0000 145 #define GE_EN_GE BIT(0) 146 #define GE_EN_DITHER BIT(1) 147 #define GE_EN_BLEND BIT(2) 148 #if (EUCLID_BRINGUP==1) 149 #define GE_EN_ASCK BIT(3) 150 #define GE_EN_DSCK BIT(4) 151 #endif 152 #define GE_EN_ROP2 BIT(5) 153 #define GE_EN_SCK BIT(6) 154 #define GE_EN_DCK BIT(7) 155 #define GE_EN_LINEPAT BIT(8) 156 #define GE_EN_DITHER_RAND BIT(9) //[OBERON] 157 #define GE_EN_DFB_BLD BIT(10) 158 #define GE_EN_ACMP BIT(11) 159 #define GE_EN_ATEST BIT(12) //[OBERON] 160 #define GE_EN_CALC_SRC_WH BIT(13) 161 #if (EUCLID_BRINGUP==1) 162 #define GE_EN_TRAP_SUB_CORR BIT(14) //[Euclid] 163 #endif 164 #define GE_EN_BURST BIT(14) 165 #define GE_EN_ONE_PIXEL_MODE BIT(15) //[OBERON] 166 #define REG_GE_CFG 0x0001 167 #define GE_CFG_CMDQ_MASK BMASK(3:0) 168 #define GE_CFG_CMDQ BIT(0) 169 #define GE_CFG_VCMDQ BIT(1) //[OBERON] 170 #define GE_CFG_RPRIO BIT(2) 171 172 #if (EUCLID_BRINGUP==1) 173 #define GE_CFG_DISABLE_MIU_ACS BIT(3) //[Euclid] 174 #else 175 #define GE_CFG_WPRIO BIT(3) 176 #endif 177 #define GE_CFG_BLT_STRETCH BIT(4) 178 #define GE_CFG_EN_CLIPCHK BIT(5) //[OBERON] hw patch for both start/end out of clipping window 179 #define GE_CFG_BLT_ITALIC BIT(6) 180 #define GE_CFG_LENGTH_LIMIT BIT(7) //[OBERON] burst length limit to 1 181 #define GE_CFG_SRC_TILE BIT(8) //[OBERON] source buffer tile mode 182 #define GE_CFG_DST_TILE BIT(9) //[OBERON] destination buffer tile mode 183 #define GE_CFG_MIU0_PROT BIT(10) //[OBERON] 184 #define GE_CFG_MIU1_PROT BIT(11) //[OBERON] 185 #define GE_CFG_RW_SPLIT BIT(14) //[OBERON] 186 #if (EUCLID_BRINGUP==1) 187 #define GE_CFG_CLR_MIU_FLG BIT(12) //[Euclid] 188 #define GE_CFG_EN_DNY_CLK_GATE BIT(15) //[Euclid] 189 #endif 190 #define REG_GE_DBG 0x0002 191 #if (EUCLID_BRINGUP==1) 192 #define GE_DBG_MIU_MAX_LEG BMASK(13:8) //[Euclid] 193 #define GE_DBG_POL_VAR_MODE BIT(14) //[Euclid] 194 #define GE_DBG_LEG_MODE BIT(15) //[Euclid] 195 #endif 196 197 #define REG_GE_TH 0x0003 198 #define GE_TH_STBB_MASK BMASK(3:0) 199 #define GE_TH_CMDQ_MASK BMASK(7:4) //[OBERON] 200 #define GE_TH_CMDQ2_MASK BMASK(11:8) //[OBERON] 201 #define REG_GE_VCMDQ_STAT 0x0004 //[OBERON] virtual queue status [15:0] 202 #define REG_GE_BIST_STAT 0x0005 203 #define GE_VCMDQ_STAT_H_MASK BMASK(0:0) //[OBERON] virtual queue status [16] 204 #define GE_STAT_VCMDQ_MAX 131071 205 #define REG_GE_STAT 0x0007 206 #define GE_STAT_BUSY BIT(0) 207 #define GE_STAT_CMDQ2_MASK BMASK(7:3) 208 #define GE_STAT_CMDQ2_SHFT 3 209 #define GE_STAT_CMDQ2_MAX 16 210 #define GE_STAT_CMDQ_MASK BMASK(15:11) 211 #define GE_STAT_CMDQ_SHFT 11 212 #define GE_STAT_CMDQ_MAX 16 213 #define REG_GE_MIU_PROT_LTH_L(_miu) (0x0008+(_miu<<2)) 214 #define REG_GE_MIU_PROT_LTH_H(_miu) (0x0009+(_miu<<2)) 215 #define GE_MIU_PROT_LTH_H_MASK BMASK(10:0) 216 #define GE_MIU_PROT_MODE_MASK BIT(15) 217 #define GE_MIU_PROT_MODE_SHFT 15 218 #define GE_MIU_PROT_MODE_EQ BITS(15:15, 0) 219 #define GE_MIU_PROT_MODE_NE BITS(15:15, 1) 220 #define REG_GE_MIU_PROT_HTH_L(_miu) (0x000A+(_miu<<2)) 221 #define REG_GE_MIU_PROT_HTH_H(_miu) (0x000B+(_miu<<2)) 222 #define REG_GE_ROP2 0x0010 223 #define GE_ROP2_MASK BMASK(3:0) 224 #define REG_GE_BLEND 0x0011 // source coefficient of alpha blending 225 #define GE_BLEND_MASK BMASK(3:0) 226 #define GE_BLEND_ONE BITS(3:0, 0) 227 #define GE_BLEND_CONST BITS(3:0, 1) 228 #define GE_BLEND_ASRC BITS(3:0, 2) 229 #define GE_BLEND_ADST BITS(3:0, 3) 230 #define GE_BLEND_ROP8_ALPHA BITS(3:0, 4) //[OBERON] 231 #define GE_BLEND_ROP8_SRCOVER BITS(3:0, 5) //[OBERON] 232 #define GE_BLEND_ROP8_DSTOVER BITS(3:0, 6) //[OBERON] 233 #if (EUCLID_BRINGUP==1) 234 #define GE_BLEND_ROP8_DSTNEW BITS(3:0, 7) //[Euclid] Csrc*Aconst 235 #endif 236 #define GE_BLEND_ZERO BITS(3:0, 8) 237 #define GE_BLEND_CONST_INV BITS(3:0, 9) 238 #define GE_BLEND_ASRC_INV BITS(3:0, 10) 239 #define GE_BLEND_ADST_INV1 BITS(3:0, 11) 240 #define GE_BLEND_ADST_INV2 BITS(3:0, 12) 241 #define GE_BLEND_ADST_INV3 BITS(3:0, 13) 242 #if (EUCLID_BRINGUP==1) 243 #define GE_BLEND_ADST_INV4 BITS(3:0, 14) //[Euclid] Csrc*Aconst 244 #define GE_BLEND_ADST_INV5 BITS(3:0, 15) //[Euclid] Csrc*Aconst 245 #endif 246 247 #define GE_ALPHA_ARGB1555 BMASK(15:8) //[OBERON] 248 #define REG_GE_ALPHA 0x0012 249 #define GE_ALPHA_MASK BMASK(12:8) 250 #define GE_ALPHA_SHFT 8 251 #define GE_ALPHA_CONST BITS(12:8, 0) 252 #define GE_ALPHA_ASRC BITS(12:8, 1) 253 #define GE_ALPHA_ADST BITS(12:8, 2) 254 #define GE_ALPHA_ROP8_SRC BITS(12:8, 3) 255 #define GE_ALPHA_ROP8_IN BITS(12:8, 4) //[OBERON] 256 #define GE_ALPHA_ROP8_DSTOUT BITS(12:8, 5) //[OBERON] 257 #define GE_ALPHA_ROP8_SRCOUT BITS(12:8, 6) //[OBERON] 258 #define GE_ALPHA_ROP8_OVER BITS(12:8, 7) //[OBERON] 259 #if (EUCLID_BRINGUP==1) 260 #define GE_ALPHA_N_CONST BITS(12:8, 8) //[Euclid] Csrc*Aconst 261 #define GE_ALPHA_N_ASRC BITS(12:8, 9) //[Euclid] Csrc*Aconst 262 #define GE_ALPHA_N_ADST BITS(12:8, 10) //[Euclid] Csrc*Aconst 263 #define GE_ALPHA_NEW1 BITS(12:8, 11) //[Euclid] Csrc*Aconst 264 #define GE_ALPHA_NEW2 BITS(12:8, 12) //[Euclid] Csrc*Aconst 265 #define GE_ALPHA_NEW3 BITS(12:8, 13) //[Euclid] Csrc*Aconst 266 #define GE_ALPHA_NEW4 BITS(12:8, 14) //[Euclid] Csrc*Aconst 267 #define GE_ALPHA_NEW5 BITS(12:8, 15) //[Euclid] Csrc*Aconst 268 #endif 269 #define REG_GE_ALPHA_CONST 0x0013 270 #define GE_ALPHA_CONST_MASK BMASK(7:0) 271 #define GE_ALPHA_SRCMASK_MASK BMASK(15:8) 272 273 #define REG_GE_SCK_HTH_L 0x0014 //ARGB8888(32), CrYCb, BLINK(16), I8(8) 274 #define REG_GE_SCK_HTH_H 0x0015 // 275 #define REG_GE_SCK_LTH_L 0x0016 //ARGB8888(32), CrYCb, BLINK(16), I8(8) 276 #define REG_GE_SCK_LTH_H 0x0017 // 277 #define REG_GE_DCK_HTH_L 0x0018 //ARGB8888(32), CrYCb, BLINK(16), I8(8) 278 #define REG_GE_DCK_HTH_H 0x0019 // 279 #define REG_GE_DCK_LTH_L 0x001A //ARGB8888(32), CrYCb, BLINK(16), I8(8) 280 #define REG_GE_DCK_LTH_H 0x001B // 281 #define REG_GE_OP_MODE 0x001C 282 #define GE_OP_SCK_SHFT 0 283 #define GE_OP_SCK_NE BIT(0) // 284 #define GE_OP_DCK_SHFT 1 285 #define GE_OP_DCK_NE BIT(1) // 286 #define GE_OP_ACMP_SHFT 4 287 #define GE_OP_ACMP_MIN BIT(4) // MIN(Asrc,Adst) 288 #define GE_OP_ATEST_SHFT 5 289 #define GE_OP_ATEST_NE BIT(5) 290 #define GE_SRCCOLOR_MASK_B BMASK(15:8) 291 #define GE_SRCCOLOR_MASK_B_SHIFT 8 292 #define REG_GE_ATEST_TH 0x001D 293 #define GE_ATEST_HTH_MASK BMASK(7:0) 294 #define GE_ATEST_LTH_MASK BMASK(15:8) 295 #define REG_GE_SRCMASK_GB 0x001E 296 #define GE_SRCCOLOR_MASK_G BMASK(7:0) 297 #define GE_SRCCOLOR_MASK_G_SHIFT 0 298 #define GE_SRCCOLOR_MASK_R BMASK(15:8) 299 #define GE_SRCCOLOR_MASK_R_SHIFT 8 300 #define GE_INT_MODE_CLEAR 0xC00 301 #define GE_INT_TAG_MODE 0x20 302 #define GE_INT_TAG_MASK 0xC0 303 #define REG_GE_YUV_MODE 0x001F //[URANUS] write only 304 #define GE_FMT_YVYU 0 305 #define GE_FMT_YUYV 1 306 #define GE_FMT_VYUY 2 307 #define GE_FMT_UYVY 3 308 #define GE_YUV_RGB2YUV_MASK BMASK(1:0) 309 #define GE_YUV_RGB2YUV_SHFT 0 310 #define GE_YUV_RGB2YUV_PC BITS(1:0, 0) 311 #define GE_YUV_RGB2YUV_255 BITS(1:0, 1) 312 #define GE_YUV_OUT_RANGE_MASK BMASK(2) 313 #define GE_YUV_OUT_RANGE_SHFT 2 314 #define GE_YUV_OUT_255 BITS(2:2, 0) 315 #define GE_YUV_OUT_PC BITS(2:2, 1) 316 #define GE_YUV_IN_RANGE_MASK BMASK(3) 317 #define GE_YUV_IN_RANGE_SHFT 3 318 #define GE_YUV_IN_255 BITS(3:3, 0) 319 #define GE_YUV_IN_127 BITS(3:3, 1) 320 #define GE_YUV_SRC_YUV422_MASK BMASK(5:4) 321 #define GE_YUV_SRC_YUV422_SHFT 4 322 #define GE_YUV_SRC_YVYU BITS(5:4, GE_FMT_YVYU) // CbY1CrY0 323 #define GE_YUV_SRC_YUYV BITS(5:4, GE_FMT_YUYV) // CrY1CbY0 (ATI) 324 #define GE_YUV_SRC_VYUY BITS(5:4, GE_FMT_VYUY) // Y1CbY0Cr 325 #define GE_YUV_SRC_UYVY BITS(5:4, GE_FMT_UYVY) // Y1CrY0Cb 326 #define GE_YUV_DST_YUV422_MASK BMASK(7:6) 327 #define GE_YUV_DST_YUV422_SHFT 6 328 #define GE_YUV_DST_YVYU BITS(7:6, GE_FMT_YVYU) 329 #define GE_YUV_DST_YUYV BITS(7:6, GE_FMT_YUYV) 330 #define GE_YUV_DST_VYUY BITS(7:6, GE_FMT_VYUY) 331 #define GE_YUV_DST_UYVY BITS(7:6, GE_FMT_UYVY) 332 #define GE_SRC_BUFFER_MIU_H_SHFT 13 333 #define GE_DST_BUFFER_MIU_H_SHFT 14 334 #define REG_GE_SRC_BASE_L 0x0020 335 #define REG_GE_SRC_BASE_H 0x0021 336 #if (EUCLID_BRINGUP==1) 337 #define GE_SB_MIU_SEL BIT(15) //[Euclid] Source Buffer MIU Selection 338 #endif 339 #define REG_GE_INT_TAG_COND_H 0x0024 340 #define REG_GE_INT_TAG_COND_L 0x0025 341 #define REG_GE_DST_BASE_L 0x0026 342 #define REG_GE_DST_BASE_H 0x0027 343 #if (EUCLID_BRINGUP==1) 344 #define GE_DB_MIU_SEL BIT(15) //[Euclid] Destination Buffer MIU Selection 345 #endif 346 347 #define REG_GE_VCMDQ_BASE_L 0x0028 348 #define REG_GE_VCMDQ_BASE_H 0x0029 349 #if (EUCLID_BRINGUP==1) 350 #define GE_VCMQ_MIU_SEL BIT(15) //[Euclid] Virtual Command Queue MIU Selection 351 #endif 352 353 #define REG_GE_VCMDQ_SIZE 0x002A 354 #define GE_VCMDQ_SIZE_MASK BMASK(2:0) 355 #define GE_VCMDQ_SIZE(_size) ( (_size>>19) ? 7 : \ 356 (_size>>18) ? 6 : \ 357 (_size>>17) ? 5 : \ 358 (_size>>16) ? 4 : \ 359 (_size>>15) ? 3 : \ 360 (_size>>14) ? 2 : \ 361 (_size>>13) ? 1 : 0 ) 362 #define REG_GE_DFB_BLD_OP 0x002A 363 #define GE_DFB_SRC_COLORMASK BIT(7) 364 #define GE_DFB_SRC_COLORMASK_SHIFT 7 365 #define GE_DFB_SRCBLD_OP_MASK BMASK(11:8) 366 #define GE_DFB_SRCBLD_OP_SHFT 8 367 #define GE_DFB_SRCBLD_OP_ZERO BITS(11:8, 0) 368 #define GE_DFB_SRCBLD_OP_ONE BITS(11:8, 1) 369 #define GE_DFB_SRCBLD_OP_SRCCOLOR BITS(11:8, 2) 370 #define GE_DFB_SRCBLD_OP_INVSRCCOLOR BITS(11:8, 3) 371 #define GE_DFB_SRCBLD_OP_SRCALPHA BITS(11:8, 4) 372 #define GE_DFB_SRCBLD_OP_INVSRCALPHA BITS(11:8, 5) 373 #define GE_DFB_SRCBLD_OP_DESTALPHA BITS(11:8, 6) 374 #define GE_DFB_SRCBLD_OP_INVDESTALPHA BITS(11:8, 7) 375 #define GE_DFB_SRCBLD_OP_DESTCOLOR BITS(11:8, 8) 376 #define GE_DFB_SRCBLD_OP_INVDESTCOLOR BITS(11:8, 9) 377 #define GE_DFB_SRCBLD_OP_SRCALPHASAT BITS(11:8, 10) 378 #define GE_DFB_DSTBLD_OP_MASK BMASK(15:12) 379 #define GE_DFB_DSTBLD_OP_SHFT 12 380 #define GE_DFB_DSTBLD_OP_ZERO BITS(15:12, 0) 381 #define GE_DFB_DSTBLD_OP_ONE BITS(15:12, 1) 382 #define GE_DFB_DSTBLD_OP_SRCCOLOR BITS(15:12, 2) 383 #define GE_DFB_DSTBLD_OP_INVSRCCOLOR BITS(15:12, 3) 384 #define GE_DFB_DSTBLD_OP_SRCALPHA BITS(15:12, 4) 385 #define GE_DFB_DSTBLD_OP_INVSRCALPHA BITS(15:12, 5) 386 #define GE_DFB_DSTBLD_OP_DESTALPHA BITS(15:12, 6) 387 #define GE_DFB_DSTBLD_OP_INVDESTALPHA BITS(15:12, 7) 388 #define GE_DFB_DSTBLD_OP_DESTCOLOR BITS(15:12, 8) 389 #define GE_DFB_DSTBLD_OP_INVDESTCOLOR BITS(15:12, 9) 390 #define GE_DFB_DSTBLD_OP_SRCALPHASAT BITS(15:12, 10) 391 #define REG_GE_DFB_BLD_FLAGS 0x002B 392 #define GE_DFB_BLD_FLAGS_MASK BMASK(7:0) 393 #define GE_DFB_BLD_FLAG_COLORALPHA BIT(0) 394 #define GE_DFB_BLD_FLAG_ALPHACHANNEL BIT(1) 395 #define GE_DFB_BLD_FLAG_COLORIZE BIT(2) 396 #define GE_DFB_BLD_FLAG_SRCPREMUL BIT(3) 397 #define GE_DFB_BLD_FLAG_SRCPREMULCOL BIT(4) 398 #define GE_DFB_BLD_FLAG_DSTPREMUL BIT(5) 399 #define GE_DFB_BLD_FLAG_XOR BIT(6) 400 #define GE_DFB_BLD_FLAG_DEMULTIPLY BIT(7) 401 #define REG_GE_B_CONST 0x002B 402 #define GE_B_CONST_MASK BMASK(15:8) 403 #define GE_B_CONST_SHIFT 8 404 #define REG_GE_G_CONST 0x002C 405 #define GE_G_CONST_MASK BMASK(7:0) 406 #define GE_G_CONST_SHIFT 0 407 #define REG_GE_R_CONST 0x002C 408 #define GE_R_CONST_MASK BMASK(15:8) 409 #define GE_R_CONST_SHIFT 8 410 #define REG_GE_CLUT_L 0x002D 411 #define REG_GE_CLUT_H 0x002E 412 #define REG_GE_CLUT_CTRL 0x002F 413 #define GE_CLUT_CTRL_IDX_MASK BMASK(7:0) 414 #define GE_CLUT_CTRL_RD BITS(8:8, 0) 415 #define GE_CLUT_CTRL_WR BITS(8:8, 1) 416 #define REG_GE_SRC_PITCH 0x0030 417 #define REG_GE_TAG_H 0x0031 418 #define REG_GE_TAG_L 0x0032 419 #define REG_GE_DST_PITCH 0x0033 420 #define REG_GE_FMT 0x0034 421 #define GE_SRC_FMT_MASK BMASK(4:0) 422 #define GE_SRC_FMT_SHFT 0 423 #define GE_DST_FMT_MASK BMASK(12:8) 424 #define GE_DST_FMT_SHFT 8 425 #define REG_GE_C_L(_idx) (0x0035+(_idx<<1)) // [31:0]ARGB8888, [15:0]blink, [7:0]I8 426 #define REG_GE_C_H(_idx) (0x0036+(_idx<<1)) 427 #define REG_GE_CLIP_L 0x0055 428 #define REG_GE_CLIP_R 0x0056 429 #define REG_GE_CLIP_T 0x0057 430 #define REG_GE_CLIP_B 0x0058 431 #define REG_GE_ROT_MODE 0x0059 432 #define REG_GE_ROT_MODE_MASK BMASK(1:0) 433 #define REG_GE_ROT_MODE_SHFT 0 434 #define REG_GE_ROT_0 BITS(1:0, 0) 435 #define REG_GE_ROT_90 BITS(1:0, 1) 436 #define REG_GE_ROT_180 BITS(1:0, 2) 437 #define REG_GE_ROT_270 BITS(1:0, 3) 438 #if (EUCLID_BRINGUP==1) 439 #define GE_TRAP_DX1 BMASK(15:0) 440 #define REG_GE_BLT_SCK_MODE 0x0059 441 #define GE_BLT_SCK_MODE_MASK BMASK(7:6) 442 #define GE_BLT_SCK_BILINEAR BITS(7:6, 0) //[Euclid] Do nothing 443 #define GE_BLT_SCK_NEAREST BITS(7:6, 1) //[Euclid] NEAREST WHEN THE COLOR KEY HAPPENED 444 #define GE_BLT_SCK_CONST BITS(7:6, 2) //[Euclid] REPLACE THE KEY TO CUSTOM COLOR 445 #define GE_TRAP_DX0_MSB BMASK(9:8) 446 #define GE_TRAP_DX0_MSB_SHFT 8 447 #define GE_TRAP_DX1_MSB BMASK(13:12) 448 #define GE_TRAP_DX1_MSB_SHFT 12 449 450 #define REG_GE_TRAPEZOID_DX0 0x005A 451 #define GE_TRAP_DX0 BMASK(15:0) 452 #define REG_GE_TRAPEZOID_DX1 0x005B 453 #define GE_TRAP_DX1 BMASK(15:0) 454 #else 455 #define REG_GE_BLT_SCK_MODE 0x005B 456 #define GE_BLT_SCK_MODE_MASK BMASK(1:0) 457 #define GE_BLT_SCK_BILINEAR BITS(1:0, 0) 458 #define GE_BLT_SCK_NEAREST BITS(1:0, 1) 459 #define GE_BLT_SCK_CONST BITS(1:0, 2) // replace to const color 460 #endif 461 #define REG_GE_BLT_SCK_CONST_L 0x005C // GB 462 #define REG_GE_BLT_SCK_CONST_H 0x005D // R, Uranus doesn't have alpha key 463 #define REG_GE_BLT_DST_X_OFST 0x005E // (s.12) 464 #if (EUCLID_BRINGUP==1) 465 #define GE_STBB_DX_MSB BIT(15) 466 #define GE_STBB_DX_MSB_SHFT 15 467 #endif 468 #define REG_GE_BLT_DST_Y_OFST 0x005F // (s.12) 469 #if (EUCLID_BRINGUP==1) 470 #define GE_STBB_DY_MSB BIT(15) 471 #define GE_STBB_DY_MSB_SHFT 15 472 #endif 473 #define REG_GE_CMD 0x0060 474 #define GE_PRIM_TYPE_MASK BMASK(6:4) 475 #define GE_PRIM_LINE BITS(6:4, 1) 476 #if (EUCLID_BRINGUP==1) 477 #define GE_PRIM_TRAPEZOID BITS(6:4, 2) 478 #endif 479 #define GE_PRIM_RECT BITS(6:4, 3) 480 #define GE_PRIM_BITBLT BITS(6:4, 4) 481 #if (EUCLID_BRINGUP==1) 482 #define GE_PRIM_TRAPEZOID_BLT BITS(6:4, 5) 483 #endif 484 #define GE_SRC_DIR_X_INV BIT(7) 485 #define GE_SRC_DIR_Y_INV BIT(8) 486 #define GE_DST_DIR_X_INV BIT(9) 487 #define GE_DST_DIR_Y_INV BIT(10) 488 #define GE_LINE_GRADIENT BIT(11) 489 #define GE_RECT_GRADIENT_H BIT(12) 490 #define GE_RECT_GRADIENT_V BIT(13) 491 #define GE_STRETCH_BILINEAR BITS(14:14, 0) 492 #define GE_STRETCH_NEAREST BITS(14:14, 1) 493 #define GE_STRETCH_CLAMP BIT(15) 494 #define REG_GE_LINE_DELTA 0x0061 495 #define GE_LINE_DELTA_MASK BMASK(14:1) // (s1.12) minor direction delta value of line 496 #define GE_LINE_DELTA_SHFT 1 497 #define GE_LINE_MAJOR_X BITS(15:15, 0) 498 #define GE_LINE_MAJOR_Y BITS(15:15, 1) 499 #define REG_GE_LINE_STYLE 0x0062 500 #define GE_LINEPAT_MASK BMASK(5:0) 501 #define GE_LINEPAT_RST BIT(8) 502 #define GE_LINE_LAST BIT(9) 503 #define GE_LINEPAT_REP_MASK BMASK(7:6) 504 #define GE_LINEPAT_REP_SHFT 6 505 #define GE_LINEPAT_REP1 BITS(7:6, 0) 506 #define GE_LINEPAT_REP2 BITS(7:6, 1) 507 #define GE_LINEPAT_REP3 BITS(7:6, 2) 508 #define GE_LINEPAT_REP4 BITS(7:6, 3) 509 #define REG_GE_LINE_LENGTH 0x0063 510 #define GE_LINE_LENGTH_MASK BMASK(11:0) 511 #define REG_GE_BLT_SRC_DX 0x0064 //[EUCLID] (5.12) 512 #define REG_GE_BLT_SRC_DY 0x0065 //[EUCLID] (5.12) 513 #define GE_STBB_DXY_MASK BMASK(12:0) 514 #define REG_GE_ITALIC_OFFSET 0x0066 515 #define GE_ITALIC_X_MASK BMASK(7:0) 516 #define GE_ITALIC_X_SHFT 0 517 #define GE_ITALIC_Y_MASK BMASK(15:8) 518 #define GE_ITALIC_Y_SHFT 8 519 #define REG_GE_ITALIC_DELTA 0x0067 520 #define GE_ITALIC_D_MASK BMASK(7:0) // (s1.3) 521 #define GE_ITALIC_D_SHFT 0 522 #define REG_GE_PRIM_V0_X 0x0068 //[EUCLID] COORDINATE X0 OF PRIMITIVE VERTEX 0 523 #define REG_GE_PRIM_V0_Y 0x0069 //[EUCLID] COORDINATE Y0 OF PRIMITIVE VERTEX 0 524 #define REG_GE_PRIM_V1_X 0x006A //[EUCLID] COORDINATE X1 OF PRIMITIVE VERTEX 1 525 #define REG_GE_PRIM_V1_Y 0x006B //[EUCLID] COORDINATE Y1 OF PRIMITIVE VERTEX 1 526 #define REG_GE_PRIM_V2_X 0x006C 527 #define REG_GE_PRIM_V2_Y 0x006D 528 #define REG_GE_BLT_SRC_W 0x006E 529 #define REG_GE_BLT_SRC_H 0x006F 530 #define REG_GE_PRIM_C_L 0x0070 // [L]:B,Bg(AXFB2355,AAFB2266),I8, [H]:G,Fg(AXFB2355,AAFB2266) 531 #define REG_GE_PRIM_C_H 0x0071 // [L]:R,AX(AXFB2355),Ba(AAFB2266), [H]:A,1(AXFB2355),Fa(AAFB2266) 532 #define REG_GE_PRIM_RDX_L 0x0072 // (s7.12) 533 #define REG_GE_PRIM_RDX_H 0x0073 534 #define REG_GE_PRIM_RDY_L 0x0074 535 #define REG_GE_PRIM_RDY_H 0x0075 536 #define REG_GE_PRIM_GDX_L 0x0076 537 #define REG_GE_PRIM_GDX_H 0x0077 538 #define REG_GE_PRIM_GDY_L 0x0078 539 #define REG_GE_PRIM_GDY_H 0x0079 540 #define REG_GE_PRIM_BDX_L 0x007A 541 #define REG_GE_PRIM_BDX_H 0x007B 542 #define REG_GE_PRIM_BDY_L 0x007C 543 #define REG_GE_PRIM_BDY_H 0x007D 544 #define REG_GE_PRIM_ADX 0x007E // (s4.11) 545 #define REG_GE_PRIM_ADY 0x007F 546 547 #define REG_GE_TLB_TYPE_EN 0x0000 548 #define GE_TLB_MODE_MASK BMASK(2:1) 549 #define GE_TLB_SRC BIT(1) 550 #define GE_TLB_DST BIT(2) 551 #define GE_TLB_FLUSH BIT(3) 552 553 #define REG_GE_TLB_EN 0x0001 554 #define GE_TLB_EN BIT(0) 555 556 #define REG_GE_TLB_TAG 0x0010 557 #define GE_TLB_TAG BMASK(5:0) 558 559 #define REG_GE_TLB_BASE_MIU_H 0x001F 560 #define GE_SB_TLB_SRC_MIU_SEL_H BIT(13) 561 #define GE_SB_TLB_DST_MIU_SEL_H BIT(14) 562 563 #define REG_GE_SRC_TLB_BASE_L 0x0020 564 #define REG_GE_SRC_TLB_BASE_H 0x0021 565 #if (EUCLID_BRINGUP==1) 566 #define GE_SB_TLB_MIU_SEL BIT(15) //[Euclid] Source Buffer MIU Selection 567 #endif 568 #define REG_GE_DST_TLB_BASE_L 0x0022 569 #define REG_GE_DST_TLB_BASE_H 0x0023 570 #if (EUCLID_BRINGUP==1) 571 #define GE_DB_TLB_MIU_SEL BIT(15) //[Euclid] Destination Buffer MIU Selection 572 #endif 573 574 //------------------------------------------------------------------------------------------------- 575 // Type and Structure 576 //------------------------------------------------------------------------------------------------- 577 578 579 #endif // _REG_GE_H_ 580 581