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Searched refs:REG_PM_MHL_CBUS_21 (Results 1 – 25 of 42) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/hdmi/hal/macan/mhl/internal/
H A DhalMHL.c154 {REG_PM_MHL_CBUS_21, BIT(1), BIT(1)}, // [1]: output mhl_zxsense_tmds inv
1211 W2BYTEMSK(REG_PM_MHL_CBUS_21, 0, BIT(11)); in _mhal_mhl_CbusAndClockSelect()
3239 W2BYTEMSK(REG_PM_MHL_CBUS_21, BIT(7), BIT(7)); in mhal_mhl_VbusConfigSetting()
3279 W2BYTEMSK(REG_PM_MHL_CBUS_21, BIT(7), BIT(7)); in mhal_mhl_VbusConfigSetting()
3309 W2BYTEMSK(REG_PM_MHL_CBUS_21, BIT(7), BIT(7)); in mhal_mhl_VbusConfigSetting()
H A DhwregMHL.h281 #define REG_PM_MHL_CBUS_21 (REG_PM_MHL_CBUS_BANK + 0x42) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mustang/mhl/internal/
H A DhalMHL.c148 {REG_PM_MHL_CBUS_21, BIT(1), BIT(1)}, // [1]: output mhl_zxsense_tmds inv
2420 W2BYTEMSK(REG_PM_MHL_CBUS_21, BIT(7), BIT(7)); in mhal_mhl_VbusConfigSetting()
2460 W2BYTEMSK(REG_PM_MHL_CBUS_21, BIT(7), BIT(7)); in mhal_mhl_VbusConfigSetting()
2490 W2BYTEMSK(REG_PM_MHL_CBUS_21, BIT(7), BIT(7)); in mhal_mhl_VbusConfigSetting()
H A DhwregMHL.h169 #define REG_PM_MHL_CBUS_21 (REG_PM_MHL_CBUS_BANK + 0x42) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maldives/mhl/internal/
H A DhalMHL.c148 {REG_PM_MHL_CBUS_21, BIT(1), BIT(1)}, // [1]: output mhl_zxsense_tmds inv
2417 W2BYTEMSK(REG_PM_MHL_CBUS_21, BIT(7), BIT(7)); in mhal_mhl_VbusConfigSetting()
2457 W2BYTEMSK(REG_PM_MHL_CBUS_21, BIT(7), BIT(7)); in mhal_mhl_VbusConfigSetting()
2487 W2BYTEMSK(REG_PM_MHL_CBUS_21, BIT(7), BIT(7)); in mhal_mhl_VbusConfigSetting()
H A DhwregMHL.h169 #define REG_PM_MHL_CBUS_21 (REG_PM_MHL_CBUS_BANK + 0x42) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7621/mhl/internal/
H A DhalMHL.c165 {REG_PM_MHL_CBUS_21, BIT(1), BIT(1)}, // [1]: output mhl_zxsense_tmds inv
3743 W2BYTEMSK(REG_PM_MHL_CBUS_21, BIT(7), BIT(7)); in mhal_mhl_VbusConfigSetting()
3770 W2BYTEMSK(REG_PM_MHL_CBUS_21, BIT(7), BIT(7)); in mhal_mhl_VbusConfigSetting()
3797 W2BYTEMSK(REG_PM_MHL_CBUS_21, BIT(7), BIT(7)); in mhal_mhl_VbusConfigSetting()
3824 W2BYTEMSK(REG_PM_MHL_CBUS_21, BIT(7), BIT(7)); in mhal_mhl_VbusConfigSetting()
H A DhwregMHL.h281 #define REG_PM_MHL_CBUS_21 (REG_PM_MHL_CBUS_BANK + 0x42) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maxim/mhl/internal/
H A DhalMHL.c165 {REG_PM_MHL_CBUS_21, BIT(1), BIT(1)}, // [1]: output mhl_zxsense_tmds inv
3743 W2BYTEMSK(REG_PM_MHL_CBUS_21, BIT(7), BIT(7)); in mhal_mhl_VbusConfigSetting()
3770 W2BYTEMSK(REG_PM_MHL_CBUS_21, BIT(7), BIT(7)); in mhal_mhl_VbusConfigSetting()
3797 W2BYTEMSK(REG_PM_MHL_CBUS_21, BIT(7), BIT(7)); in mhal_mhl_VbusConfigSetting()
3824 W2BYTEMSK(REG_PM_MHL_CBUS_21, BIT(7), BIT(7)); in mhal_mhl_VbusConfigSetting()
H A DhwregMHL.h281 #define REG_PM_MHL_CBUS_21 (REG_PM_MHL_CBUS_BANK + 0x42) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maserati/mhl/internal/
H A DhalMHL.c165 {REG_PM_MHL_CBUS_21, BIT(1), BIT(1)}, // [1]: output mhl_zxsense_tmds inv
3743 W2BYTEMSK(REG_PM_MHL_CBUS_21, BIT(7), BIT(7)); in mhal_mhl_VbusConfigSetting()
3770 W2BYTEMSK(REG_PM_MHL_CBUS_21, BIT(7), BIT(7)); in mhal_mhl_VbusConfigSetting()
3797 W2BYTEMSK(REG_PM_MHL_CBUS_21, BIT(7), BIT(7)); in mhal_mhl_VbusConfigSetting()
3824 W2BYTEMSK(REG_PM_MHL_CBUS_21, BIT(7), BIT(7)); in mhal_mhl_VbusConfigSetting()
H A DhwregMHL.h281 #define REG_PM_MHL_CBUS_21 (REG_PM_MHL_CBUS_BANK + 0x42) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7821/mhl/internal/
H A DhalMHL.c165 {REG_PM_MHL_CBUS_21, BIT(1), BIT(1)}, // [1]: output mhl_zxsense_tmds inv
3743 W2BYTEMSK(REG_PM_MHL_CBUS_21, BIT(7), BIT(7)); in mhal_mhl_VbusConfigSetting()
3770 W2BYTEMSK(REG_PM_MHL_CBUS_21, BIT(7), BIT(7)); in mhal_mhl_VbusConfigSetting()
3797 W2BYTEMSK(REG_PM_MHL_CBUS_21, BIT(7), BIT(7)); in mhal_mhl_VbusConfigSetting()
3824 W2BYTEMSK(REG_PM_MHL_CBUS_21, BIT(7), BIT(7)); in mhal_mhl_VbusConfigSetting()
H A DhwregMHL.h281 #define REG_PM_MHL_CBUS_21 (REG_PM_MHL_CBUS_BANK + 0x42) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/manhattan/mhl/internal/
H A DhalMHL.c165 {REG_PM_MHL_CBUS_21, BIT(1), BIT(1)}, // [1]: output mhl_zxsense_tmds inv
3743 W2BYTEMSK(REG_PM_MHL_CBUS_21, BIT(7), BIT(7)); in mhal_mhl_VbusConfigSetting()
3770 W2BYTEMSK(REG_PM_MHL_CBUS_21, BIT(7), BIT(7)); in mhal_mhl_VbusConfigSetting()
3797 W2BYTEMSK(REG_PM_MHL_CBUS_21, BIT(7), BIT(7)); in mhal_mhl_VbusConfigSetting()
3824 W2BYTEMSK(REG_PM_MHL_CBUS_21, BIT(7), BIT(7)); in mhal_mhl_VbusConfigSetting()
H A DhwregMHL.h281 #define REG_PM_MHL_CBUS_21 (REG_PM_MHL_CBUS_BANK + 0x42) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mooney/mhl/internal/
H A DhalMHL.c154 {REG_PM_MHL_CBUS_21, BIT(1), BIT(1)}, // [1]: output mhl_zxsense_tmds inv
3215 W2BYTEMSK(REG_PM_MHL_CBUS_21, BIT(7), BIT(7)); in mhal_mhl_VbusConfigSetting()
3255 W2BYTEMSK(REG_PM_MHL_CBUS_21, BIT(7), BIT(7)); in mhal_mhl_VbusConfigSetting()
3285 W2BYTEMSK(REG_PM_MHL_CBUS_21, BIT(7), BIT(7)); in mhal_mhl_VbusConfigSetting()
H A DhwregMHL.h281 #define REG_PM_MHL_CBUS_21 (REG_PM_MHL_CBUS_BANK + 0x42) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/messi/mhl/internal/
H A DhalMHL.c170 {REG_PM_MHL_CBUS_21, BIT(1), BIT(1)}, // [1]: output mhl_zxsense_tmds inv
2792 W2BYTEMSK(REG_PM_MHL_CBUS_21, BIT(7), BIT(7)); in mhal_mhl_VbusConfigSetting()
2822 W2BYTEMSK(REG_PM_MHL_CBUS_21, BIT(7), BIT(7)); in mhal_mhl_VbusConfigSetting()
H A DhwregMHL.h281 #define REG_PM_MHL_CBUS_21 (REG_PM_MHL_CBUS_BANK + 0x42) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mainz/mhl/internal/
H A DhalMHL.c170 {REG_PM_MHL_CBUS_21, BIT(1), BIT(1)}, // [1]: output mhl_zxsense_tmds inv
2792 W2BYTEMSK(REG_PM_MHL_CBUS_21, BIT(7), BIT(7)); in mhal_mhl_VbusConfigSetting()
2822 W2BYTEMSK(REG_PM_MHL_CBUS_21, BIT(7), BIT(7)); in mhal_mhl_VbusConfigSetting()
H A DhwregMHL.h281 #define REG_PM_MHL_CBUS_21 (REG_PM_MHL_CBUS_BANK + 0x42) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/
H A Dhwreg_mhl.h141 #define REG_PM_MHL_CBUS_21 (REG_PM_MHL_CBUS_BANK + 0x42) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/
H A Dhwreg_mhl.h141 #define REG_PM_MHL_CBUS_21 (REG_PM_MHL_CBUS_BANK + 0x42) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dhwreg_pm_sleep.h692 #define REG_PM_MHL_CBUS_21 (REG_PM_MHL_CBUS_BANK + 0x42) macro

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