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Searched refs:REG_MOD_BK00_7D_L (Results 1 – 11 of 11) sorted by relevance

/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/pnl/
H A DhalPNL.c1567 return (MS_BOOL)((MOD_R2BYTEMSK(REG_MOD_BK00_7D_L, BIT(8))) >> 8); in msModCalDDAOUT()
1640 …MOD_W2BYTEMSK(REG_MOD_BK00_7D_L, BIT(2), BIT(3)|BIT(2)); // Select calibration source pair, 01: c… in msModCurrentCalibration()
1641 …MOD_W2BYTEMSK(REG_MOD_BK00_7D_L, _u8MOD_CALI_TARGET, BIT(1)|BIT(0)); // Select calibration targ… in msModCurrentCalibration()
1642 MOD_W2BYTEMSK(REG_MOD_BK00_7D_L, BIT(7), BIT(7)); // Enable calibration function in msModCurrentCalibration()
1699 MOD_W2BYTEMSK(REG_MOD_BK00_7D_L, 0x00, BIT(7)); // Disable calibration function in msModCurrentCalibration()
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/pnl/
H A DhalPNL.c1567 return (MS_BOOL)((MOD_R2BYTEMSK(REG_MOD_BK00_7D_L, BIT(8))) >> 8); in msModCalDDAOUT()
1640 …MOD_W2BYTEMSK(REG_MOD_BK00_7D_L, BIT(2), BIT(3)|BIT(2)); // Select calibration source pair, 01: c… in msModCurrentCalibration()
1641 …MOD_W2BYTEMSK(REG_MOD_BK00_7D_L, _u8MOD_CALI_TARGET, BIT(1)|BIT(0)); // Select calibration targ… in msModCurrentCalibration()
1642 MOD_W2BYTEMSK(REG_MOD_BK00_7D_L, BIT(7), BIT(7)); // Enable calibration function in msModCurrentCalibration()
1699 MOD_W2BYTEMSK(REG_MOD_BK00_7D_L, 0x00, BIT(7)); // Disable calibration function in msModCurrentCalibration()
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/pnl/
H A DhalPNL.c763 …MOD_W2BYTEMSK(REG_MOD_BK00_7D_L, 0x1F, LBMASK); //[6]disable power down bit and [5:0]enable … in MHal_PNL_Init_MOD()
873 return (MS_BOOL)((MOD_R2BYTEMSK(REG_MOD_BK00_7D_L, BIT(8))) >> 8); in msModCalDDAOUT()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/pnl/
H A DhalPNL.c763 …MOD_W2BYTEMSK(REG_MOD_BK00_7D_L, 0x1F, LBMASK); //[6]disable power down bit and [5:0]enable … in MHal_PNL_Init_MOD()
873 return (MS_BOOL)((MOD_R2BYTEMSK(REG_MOD_BK00_7D_L, BIT(8))) >> 8); in msModCalDDAOUT()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/pnl/
H A DhalPNL.c763 …MOD_W2BYTEMSK(REG_MOD_BK00_7D_L, 0x1F, LBMASK); //[6]disable power down bit and [5:0]enable … in MHal_PNL_Init_MOD()
873 return (MS_BOOL)((MOD_R2BYTEMSK(REG_MOD_BK00_7D_L, BIT(8))) >> 8); in msModCalDDAOUT()
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/pnl/
H A DhalPNL.c763 …MOD_W2BYTEMSK(REG_MOD_BK00_7D_L, 0x1F, LBMASK); //[6]disable power down bit and [5:0]enable … in MHal_PNL_Init_MOD()
873 return (MS_BOOL)((MOD_R2BYTEMSK(REG_MOD_BK00_7D_L, BIT(8))) >> 8); in msModCalDDAOUT()
/utopia/UTPA2-700.0.x/modules/xc/drv/xc/include/
H A Dhwreg_mod.h359 #define REG_MOD_BK00_7D_L _PK_L_(0x00, 0x7D) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/pnl/
H A DhalPNL.c260 MOD_W2BYTEMSK(REG_MOD_BK00_7D_L, 0x0080, 0x0080); // reg_proc_st_clr in MHal_MOD_PowerOn()
261 MOD_W2BYTEMSK(REG_MOD_BK00_7D_L, 0x0000, 0x0080); in MHal_MOD_PowerOn()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/pnl/
H A DhalPNL.c261 MOD_W2BYTEMSK(REG_MOD_BK00_7D_L, 0x0080, 0x0080); // reg_proc_st_clr in MHal_MOD_PowerOn()
262 MOD_W2BYTEMSK(REG_MOD_BK00_7D_L, 0x0000, 0x0080); in MHal_MOD_PowerOn()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/pnl/
H A DhalPNL.c261 MOD_W2BYTEMSK(REG_MOD_BK00_7D_L, 0x0080, 0x0080); // reg_proc_st_clr in MHal_MOD_PowerOn()
262 MOD_W2BYTEMSK(REG_MOD_BK00_7D_L, 0x0000, 0x0080); in MHal_MOD_PowerOn()
/utopia/UTPA2-700.0.x/modules/xc/drv/pnl/include/
H A Dpnl_hwreg_utility2.h1950 #define REG_MOD_BK00_7D_L _PK_L_(0x00, 0x7D) macro