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Searched refs:REG_MOD_BK00_45_L (Results 1 – 16 of 16) sorted by relevance

/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/pnl/
H A DhalPNL.c1283 MOD_W2BYTE(REG_MOD_BK00_45_L, 0x0000); // TTL output enable in MHal_PNL_SetOutputType()
1390 …MOD_W2BYTE(REG_MOD_BK00_45_L, 0x003F); // LVDS output enable, [5:4] Output enable: PANEL_LVDS/… in MHal_PNL_SetOutputType()
1589 u16reg_328a = MOD_R2BYTEMSK(REG_MOD_BK00_45_L, LBMASK); in msModCurrentCalibration()
1704 MOD_W2BYTEMSK(REG_MOD_BK00_45_L, u16reg_328a, LBMASK); in msModCurrentCalibration()
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/pnl/
H A DhalPNL.c1283 MOD_W2BYTE(REG_MOD_BK00_45_L, 0x0000); // TTL output enable in MHal_PNL_SetOutputType()
1390 …MOD_W2BYTE(REG_MOD_BK00_45_L, 0x003F); // LVDS output enable, [5:4] Output enable: PANEL_LVDS/… in MHal_PNL_SetOutputType()
1589 u16reg_328a = MOD_R2BYTEMSK(REG_MOD_BK00_45_L, LBMASK); in msModCurrentCalibration()
1704 MOD_W2BYTEMSK(REG_MOD_BK00_45_L, u16reg_328a, LBMASK); in msModCurrentCalibration()
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/pnl/
H A DhalPNL.c617 MOD_W2BYTE(REG_MOD_BK00_45_L, 0x0000); // TTL output enable in MHal_PNL_SetOutputType()
671 …MOD_W2BYTE(REG_MOD_BK00_45_L, 0x003F); // LVDS output enable, [5:4] Output enable: PANEL_LVDS/… in MHal_PNL_SetOutputType()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/pnl/
H A DhalPNL.c617 MOD_W2BYTE(REG_MOD_BK00_45_L, 0x0000); // TTL output enable in MHal_PNL_SetOutputType()
671 …MOD_W2BYTE(REG_MOD_BK00_45_L, 0x003F); // LVDS output enable, [5:4] Output enable: PANEL_LVDS/… in MHal_PNL_SetOutputType()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/pnl/
H A DhalPNL.c617 MOD_W2BYTE(REG_MOD_BK00_45_L, 0x0000); // TTL output enable in MHal_PNL_SetOutputType()
671 …MOD_W2BYTE(REG_MOD_BK00_45_L, 0x003F); // LVDS output enable, [5:4] Output enable: PANEL_LVDS/… in MHal_PNL_SetOutputType()
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/pnl/
H A DhalPNL.c617 MOD_W2BYTE(REG_MOD_BK00_45_L, 0x0000); // TTL output enable in MHal_PNL_SetOutputType()
671 …MOD_W2BYTE(REG_MOD_BK00_45_L, 0x003F); // LVDS output enable, [5:4] Output enable: PANEL_LVDS/… in MHal_PNL_SetOutputType()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_frc.c1254 MOD_W2BYTEMSK(REG_MOD_BK00_45_L, 0x0000, 0x8000); in MHal_FRC_ByPass_Enable()
1258 MOD_W2BYTEMSK(REG_MOD_BK00_45_L, 0x8000, 0x8000); in MHal_FRC_ByPass_Enable()
/utopia/UTPA2-700.0.x/modules/xc/drv/xc/include/
H A Dhwreg_mod.h247 #define REG_MOD_BK00_45_L _PK_L_(0x00, 0x45) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_frc.c1599 MOD_W2BYTEMSK(REG_MOD_BK00_45_L, 0x0000, 0x8000); in MHal_FRC_ByPass_Enable()
1603 MOD_W2BYTEMSK(REG_MOD_BK00_45_L, 0x8000, 0x8000); in MHal_FRC_ByPass_Enable()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_frc.c1582 MOD_W2BYTEMSK(REG_MOD_BK00_45_L, 0x0000, 0x8000); in MHal_FRC_ByPass_Enable()
1586 MOD_W2BYTEMSK(REG_MOD_BK00_45_L, 0x8000, 0x8000); in MHal_FRC_ByPass_Enable()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/pnl/
H A DhalPNL.c2908 MOD_W2BYTEMSK(REG_MOD_BK00_45_L, 0x0003, 0x0003); //[1]:reg_vby1_vs_inv, [0]:reg_vby1_hs_inv in MHal_PNL_Init_MOD()
3856 MOD_W2BYTEMSK(REG_MOD_BK00_45_L, 0x0000, 0x0003); //[1]:reg_vby1_vs_inv, [0]:reg_vby1_hs_inv in MHal_PNL_SetOSDCOutputType()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_frc.c1957 MOD_W2BYTEMSK(REG_MOD_BK00_45_L, 0x0000, 0x8000); in MHal_FRC_ByPass_Enable()
1961 MOD_W2BYTEMSK(REG_MOD_BK00_45_L, 0x8000, 0x8000); in MHal_FRC_ByPass_Enable()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_frc.c1957 MOD_W2BYTEMSK(REG_MOD_BK00_45_L, 0x0000, 0x8000); in MHal_FRC_ByPass_Enable()
1961 MOD_W2BYTEMSK(REG_MOD_BK00_45_L, 0x8000, 0x8000); in MHal_FRC_ByPass_Enable()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/pnl/
H A DhalPNL.c2910 MOD_W2BYTEMSK(REG_MOD_BK00_45_L, 0x0003, 0x0003); //[1]:reg_vby1_vs_inv, [0]:reg_vby1_hs_inv in MHal_PNL_Init_MOD()
3902 MOD_W2BYTEMSK(REG_MOD_BK00_45_L, 0x0000, 0x0003); //[1]:reg_vby1_vs_inv, [0]:reg_vby1_hs_inv in MHal_PNL_SetOSDCOutputType()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/pnl/
H A DhalPNL.c2910 MOD_W2BYTEMSK(REG_MOD_BK00_45_L, 0x0003, 0x0003); //[1]:reg_vby1_vs_inv, [0]:reg_vby1_hs_inv in MHal_PNL_Init_MOD()
3902 MOD_W2BYTEMSK(REG_MOD_BK00_45_L, 0x0000, 0x0003); //[1]:reg_vby1_vs_inv, [0]:reg_vby1_hs_inv in MHal_PNL_SetOSDCOutputType()
/utopia/UTPA2-700.0.x/modules/xc/drv/pnl/include/
H A Dpnl_hwreg_utility2.h1838 #define REG_MOD_BK00_45_L _PK_L_(0x00, 0x45) macro