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Searched refs:REG_MHL_CBUS_52 (Results 1 – 25 of 35) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/hdmi/hal/mustang/mhl/internal/
H A DhalMHL.c2185 W2BYTEMSK(REG_MHL_CBUS_52, BIT(1), BIT(1)); // CPU write enable in mhal_mhl_LoadEDID()
2189 W2BYTEMSK(REG_MHL_CBUS_52, ustemp <<8, 0xFF00); // address in mhal_mhl_LoadEDID()
2191 W2BYTEMSK(REG_MHL_CBUS_52, BIT(0), BIT(0)); // write trigger in mhal_mhl_LoadEDID()
2192 W2BYTEMSK(REG_MHL_CBUS_52, 0, BIT(0)); in mhal_mhl_LoadEDID()
2193 while(R2BYTE(REG_MHL_CBUS_52) & BIT(5)); in mhal_mhl_LoadEDID()
2196 W2BYTEMSK(REG_MHL_CBUS_52, 0, BIT(1)); // CPU write disable in mhal_mhl_LoadEDID()
2221 W2BYTEMSK(REG_MHL_CBUS_52, ustemp <<8, 0xFF00); // address in mhal_mhl_ReadEDID()
2222 W2BYTEMSK(REG_MHL_CBUS_52, BIT(3), BIT(3)); // read trigger in mhal_mhl_ReadEDID()
2223 W2BYTEMSK(REG_MHL_CBUS_52, 0, BIT(0)); in mhal_mhl_ReadEDID()
2224 while(R2BYTE(REG_MHL_CBUS_52) & BIT(4)); in mhal_mhl_ReadEDID()
H A DhwregMHL.h144 #define REG_MHL_CBUS_52 (REG_MHL_CBUS_BANK + 0xA4) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maldives/mhl/internal/
H A DhalMHL.c2185 W2BYTEMSK(REG_MHL_CBUS_52, BIT(1), BIT(1)); // CPU write enable in mhal_mhl_LoadEDID()
2189 W2BYTEMSK(REG_MHL_CBUS_52, ustemp <<8, 0xFF00); // address in mhal_mhl_LoadEDID()
2191 W2BYTEMSK(REG_MHL_CBUS_52, BIT(0), BIT(0)); // write trigger in mhal_mhl_LoadEDID()
2192 W2BYTEMSK(REG_MHL_CBUS_52, 0, BIT(0)); in mhal_mhl_LoadEDID()
2193 while(R2BYTE(REG_MHL_CBUS_52) & BIT(5)); in mhal_mhl_LoadEDID()
2196 W2BYTEMSK(REG_MHL_CBUS_52, 0, BIT(1)); // CPU write disable in mhal_mhl_LoadEDID()
2221 W2BYTEMSK(REG_MHL_CBUS_52, ustemp <<8, 0xFF00); // address in mhal_mhl_ReadEDID()
2222 W2BYTEMSK(REG_MHL_CBUS_52, BIT(3), BIT(3)); // read trigger in mhal_mhl_ReadEDID()
2223 W2BYTEMSK(REG_MHL_CBUS_52, 0, BIT(0)); in mhal_mhl_ReadEDID()
2224 while(R2BYTE(REG_MHL_CBUS_52) & BIT(4)); in mhal_mhl_ReadEDID()
H A DhwregMHL.h144 #define REG_MHL_CBUS_52 (REG_MHL_CBUS_BANK + 0xA4) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/messi/mhl/internal/
H A DhalMHL.c2550 W2BYTEMSK(REG_MHL_CBUS_52, BIT(1), BIT(1)); // CPU write enable in mhal_mhl_LoadEDID()
2554 W2BYTEMSK(REG_MHL_CBUS_52, ustemp <<8, 0xFF00); // address in mhal_mhl_LoadEDID()
2556 W2BYTEMSK(REG_MHL_CBUS_52, BIT(0), BIT(0)); // write trigger in mhal_mhl_LoadEDID()
2557 W2BYTEMSK(REG_MHL_CBUS_52, 0, BIT(0)); in mhal_mhl_LoadEDID()
2558 while(R2BYTE(REG_MHL_CBUS_52) & BIT(5)); in mhal_mhl_LoadEDID()
2561 W2BYTEMSK(REG_MHL_CBUS_52, 0, BIT(1)); // CPU write disable in mhal_mhl_LoadEDID()
2586 W2BYTEMSK(REG_MHL_CBUS_52, ustemp <<8, 0xFF00); // address in mhal_mhl_ReadEDID()
2587 W2BYTEMSK(REG_MHL_CBUS_52, BIT(3), BIT(3)); // read trigger in mhal_mhl_ReadEDID()
2588 W2BYTEMSK(REG_MHL_CBUS_52, 0, BIT(0)); in mhal_mhl_ReadEDID()
2589 while(R2BYTE(REG_MHL_CBUS_52) & BIT(4)); in mhal_mhl_ReadEDID()
H A DhwregMHL.h198 #define REG_MHL_CBUS_52 (REG_MHL_CBUS_BANK + 0xA4) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mainz/mhl/internal/
H A DhalMHL.c2550 W2BYTEMSK(REG_MHL_CBUS_52, BIT(1), BIT(1)); // CPU write enable in mhal_mhl_LoadEDID()
2554 W2BYTEMSK(REG_MHL_CBUS_52, ustemp <<8, 0xFF00); // address in mhal_mhl_LoadEDID()
2556 W2BYTEMSK(REG_MHL_CBUS_52, BIT(0), BIT(0)); // write trigger in mhal_mhl_LoadEDID()
2557 W2BYTEMSK(REG_MHL_CBUS_52, 0, BIT(0)); in mhal_mhl_LoadEDID()
2558 while(R2BYTE(REG_MHL_CBUS_52) & BIT(5)); in mhal_mhl_LoadEDID()
2561 W2BYTEMSK(REG_MHL_CBUS_52, 0, BIT(1)); // CPU write disable in mhal_mhl_LoadEDID()
2586 W2BYTEMSK(REG_MHL_CBUS_52, ustemp <<8, 0xFF00); // address in mhal_mhl_ReadEDID()
2587 W2BYTEMSK(REG_MHL_CBUS_52, BIT(3), BIT(3)); // read trigger in mhal_mhl_ReadEDID()
2588 W2BYTEMSK(REG_MHL_CBUS_52, 0, BIT(0)); in mhal_mhl_ReadEDID()
2589 while(R2BYTE(REG_MHL_CBUS_52) & BIT(4)); in mhal_mhl_ReadEDID()
H A DhwregMHL.h198 #define REG_MHL_CBUS_52 (REG_MHL_CBUS_BANK + 0xA4) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mooney/mhl/internal/
H A DhalMHL.c2980 W2BYTEMSK(REG_MHL_CBUS_52, BIT(1), BIT(1)); // CPU write enable in mhal_mhl_LoadEDID()
2984 W2BYTEMSK(REG_MHL_CBUS_52, ustemp <<8, 0xFF00); // address in mhal_mhl_LoadEDID()
2986 W2BYTEMSK(REG_MHL_CBUS_52, BIT(0), BIT(0)); // write trigger in mhal_mhl_LoadEDID()
2987 W2BYTEMSK(REG_MHL_CBUS_52, 0, BIT(0)); in mhal_mhl_LoadEDID()
2988 while(R2BYTE(REG_MHL_CBUS_52) & BIT(5)); in mhal_mhl_LoadEDID()
2991 W2BYTEMSK(REG_MHL_CBUS_52, 0, BIT(1)); // CPU write disable in mhal_mhl_LoadEDID()
3016 W2BYTEMSK(REG_MHL_CBUS_52, ustemp <<8, 0xFF00); // address in mhal_mhl_ReadEDID()
3017 W2BYTEMSK(REG_MHL_CBUS_52, BIT(3), BIT(3)); // read trigger in mhal_mhl_ReadEDID()
3018 W2BYTEMSK(REG_MHL_CBUS_52, 0, BIT(0)); in mhal_mhl_ReadEDID()
3019 while(R2BYTE(REG_MHL_CBUS_52) & BIT(4)); in mhal_mhl_ReadEDID()
H A DhwregMHL.h198 #define REG_MHL_CBUS_52 (REG_MHL_CBUS_BANK + 0xA4) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/macan/mhl/internal/
H A DhalMHL.c3004 W2BYTEMSK(REG_MHL_CBUS_52, BIT(1), BIT(1)); // CPU write enable in mhal_mhl_LoadEDID()
3008 W2BYTEMSK(REG_MHL_CBUS_52, ustemp <<8, 0xFF00); // address in mhal_mhl_LoadEDID()
3010 W2BYTEMSK(REG_MHL_CBUS_52, BIT(0), BIT(0)); // write trigger in mhal_mhl_LoadEDID()
3011 W2BYTEMSK(REG_MHL_CBUS_52, 0, BIT(0)); in mhal_mhl_LoadEDID()
3012 while(R2BYTE(REG_MHL_CBUS_52) & BIT(5)); in mhal_mhl_LoadEDID()
3015 W2BYTEMSK(REG_MHL_CBUS_52, 0, BIT(1)); // CPU write disable in mhal_mhl_LoadEDID()
3040 W2BYTEMSK(REG_MHL_CBUS_52, ustemp <<8, 0xFF00); // address in mhal_mhl_ReadEDID()
3041 W2BYTEMSK(REG_MHL_CBUS_52, BIT(3), BIT(3)); // read trigger in mhal_mhl_ReadEDID()
3042 W2BYTEMSK(REG_MHL_CBUS_52, 0, BIT(0)); in mhal_mhl_ReadEDID()
3043 while(R2BYTE(REG_MHL_CBUS_52) & BIT(4)); in mhal_mhl_ReadEDID()
H A DhwregMHL.h198 #define REG_MHL_CBUS_52 (REG_MHL_CBUS_BANK + 0xA4) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7621/mhl/internal/
H A DhalMHL.c3528 W2BYTEMSK(REG_MHL_CBUS_52, BIT(1), BIT(1)); // CPU write enable in mhal_mhl_LoadEDID()
3532 W2BYTEMSK(REG_MHL_CBUS_52, ustemp <<8, 0xFF00); // address in mhal_mhl_LoadEDID()
3534 W2BYTEMSK(REG_MHL_CBUS_52, BIT(0), BIT(0)); // write trigger in mhal_mhl_LoadEDID()
3535 W2BYTEMSK(REG_MHL_CBUS_52, 0, BIT(0)); in mhal_mhl_LoadEDID()
3536 while(R2BYTE(REG_MHL_CBUS_52) & BIT(5)); in mhal_mhl_LoadEDID()
3539 W2BYTEMSK(REG_MHL_CBUS_52, 0, BIT(1)); // CPU write disable in mhal_mhl_LoadEDID()
3564 W2BYTEMSK(REG_MHL_CBUS_52, ustemp <<8, 0xFF00); // address in mhal_mhl_ReadEDID()
3565 W2BYTEMSK(REG_MHL_CBUS_52, BIT(3), BIT(3)); // read trigger in mhal_mhl_ReadEDID()
3566 W2BYTEMSK(REG_MHL_CBUS_52, 0, BIT(0)); in mhal_mhl_ReadEDID()
3567 while(R2BYTE(REG_MHL_CBUS_52) & BIT(4)); in mhal_mhl_ReadEDID()
H A DhwregMHL.h198 #define REG_MHL_CBUS_52 (REG_MHL_CBUS_BANK + 0xA4) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maxim/mhl/internal/
H A DhalMHL.c3528 W2BYTEMSK(REG_MHL_CBUS_52, BIT(1), BIT(1)); // CPU write enable in mhal_mhl_LoadEDID()
3532 W2BYTEMSK(REG_MHL_CBUS_52, ustemp <<8, 0xFF00); // address in mhal_mhl_LoadEDID()
3534 W2BYTEMSK(REG_MHL_CBUS_52, BIT(0), BIT(0)); // write trigger in mhal_mhl_LoadEDID()
3535 W2BYTEMSK(REG_MHL_CBUS_52, 0, BIT(0)); in mhal_mhl_LoadEDID()
3536 while(R2BYTE(REG_MHL_CBUS_52) & BIT(5)); in mhal_mhl_LoadEDID()
3539 W2BYTEMSK(REG_MHL_CBUS_52, 0, BIT(1)); // CPU write disable in mhal_mhl_LoadEDID()
3564 W2BYTEMSK(REG_MHL_CBUS_52, ustemp <<8, 0xFF00); // address in mhal_mhl_ReadEDID()
3565 W2BYTEMSK(REG_MHL_CBUS_52, BIT(3), BIT(3)); // read trigger in mhal_mhl_ReadEDID()
3566 W2BYTEMSK(REG_MHL_CBUS_52, 0, BIT(0)); in mhal_mhl_ReadEDID()
3567 while(R2BYTE(REG_MHL_CBUS_52) & BIT(4)); in mhal_mhl_ReadEDID()
H A DhwregMHL.h198 #define REG_MHL_CBUS_52 (REG_MHL_CBUS_BANK + 0xA4) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maserati/mhl/internal/
H A DhalMHL.c3528 W2BYTEMSK(REG_MHL_CBUS_52, BIT(1), BIT(1)); // CPU write enable in mhal_mhl_LoadEDID()
3532 W2BYTEMSK(REG_MHL_CBUS_52, ustemp <<8, 0xFF00); // address in mhal_mhl_LoadEDID()
3534 W2BYTEMSK(REG_MHL_CBUS_52, BIT(0), BIT(0)); // write trigger in mhal_mhl_LoadEDID()
3535 W2BYTEMSK(REG_MHL_CBUS_52, 0, BIT(0)); in mhal_mhl_LoadEDID()
3536 while(R2BYTE(REG_MHL_CBUS_52) & BIT(5)); in mhal_mhl_LoadEDID()
3539 W2BYTEMSK(REG_MHL_CBUS_52, 0, BIT(1)); // CPU write disable in mhal_mhl_LoadEDID()
3564 W2BYTEMSK(REG_MHL_CBUS_52, ustemp <<8, 0xFF00); // address in mhal_mhl_ReadEDID()
3565 W2BYTEMSK(REG_MHL_CBUS_52, BIT(3), BIT(3)); // read trigger in mhal_mhl_ReadEDID()
3566 W2BYTEMSK(REG_MHL_CBUS_52, 0, BIT(0)); in mhal_mhl_ReadEDID()
3567 while(R2BYTE(REG_MHL_CBUS_52) & BIT(4)); in mhal_mhl_ReadEDID()
H A DhwregMHL.h198 #define REG_MHL_CBUS_52 (REG_MHL_CBUS_BANK + 0xA4) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7821/mhl/internal/
H A DhalMHL.c3528 W2BYTEMSK(REG_MHL_CBUS_52, BIT(1), BIT(1)); // CPU write enable in mhal_mhl_LoadEDID()
3532 W2BYTEMSK(REG_MHL_CBUS_52, ustemp <<8, 0xFF00); // address in mhal_mhl_LoadEDID()
3534 W2BYTEMSK(REG_MHL_CBUS_52, BIT(0), BIT(0)); // write trigger in mhal_mhl_LoadEDID()
3535 W2BYTEMSK(REG_MHL_CBUS_52, 0, BIT(0)); in mhal_mhl_LoadEDID()
3536 while(R2BYTE(REG_MHL_CBUS_52) & BIT(5)); in mhal_mhl_LoadEDID()
3539 W2BYTEMSK(REG_MHL_CBUS_52, 0, BIT(1)); // CPU write disable in mhal_mhl_LoadEDID()
3564 W2BYTEMSK(REG_MHL_CBUS_52, ustemp <<8, 0xFF00); // address in mhal_mhl_ReadEDID()
3565 W2BYTEMSK(REG_MHL_CBUS_52, BIT(3), BIT(3)); // read trigger in mhal_mhl_ReadEDID()
3566 W2BYTEMSK(REG_MHL_CBUS_52, 0, BIT(0)); in mhal_mhl_ReadEDID()
3567 while(R2BYTE(REG_MHL_CBUS_52) & BIT(4)); in mhal_mhl_ReadEDID()
H A DhwregMHL.h198 #define REG_MHL_CBUS_52 (REG_MHL_CBUS_BANK + 0xA4) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/manhattan/mhl/internal/
H A DhalMHL.c3528 W2BYTEMSK(REG_MHL_CBUS_52, BIT(1), BIT(1)); // CPU write enable in mhal_mhl_LoadEDID()
3532 W2BYTEMSK(REG_MHL_CBUS_52, ustemp <<8, 0xFF00); // address in mhal_mhl_LoadEDID()
3534 W2BYTEMSK(REG_MHL_CBUS_52, BIT(0), BIT(0)); // write trigger in mhal_mhl_LoadEDID()
3535 W2BYTEMSK(REG_MHL_CBUS_52, 0, BIT(0)); in mhal_mhl_LoadEDID()
3536 while(R2BYTE(REG_MHL_CBUS_52) & BIT(5)); in mhal_mhl_LoadEDID()
3539 W2BYTEMSK(REG_MHL_CBUS_52, 0, BIT(1)); // CPU write disable in mhal_mhl_LoadEDID()
3564 W2BYTEMSK(REG_MHL_CBUS_52, ustemp <<8, 0xFF00); // address in mhal_mhl_ReadEDID()
3565 W2BYTEMSK(REG_MHL_CBUS_52, BIT(3), BIT(3)); // read trigger in mhal_mhl_ReadEDID()
3566 W2BYTEMSK(REG_MHL_CBUS_52, 0, BIT(0)); in mhal_mhl_ReadEDID()
3567 while(R2BYTE(REG_MHL_CBUS_52) & BIT(4)); in mhal_mhl_ReadEDID()
H A DhwregMHL.h198 #define REG_MHL_CBUS_52 (REG_MHL_CBUS_BANK + 0xA4) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/
H A Dhwreg_mhl.h120 #define REG_MHL_CBUS_52 (REG_MHL_CBUS_BANK + 0xA4) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/
H A Dhwreg_mhl.h120 #define REG_MHL_CBUS_52 (REG_MHL_CBUS_BANK + 0xA4) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dhwreg_pm_sleep.h609 #define REG_MHL_CBUS_52 (REG_MHL_CBUS_BANK + 0xA4) macro

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