| /utopia/UTPA2-700.0.x/modules/irq/hal/M7821/irq/ |
| H A D | regIRQ.h | 202 #define REG_IRQ_FINAL_STATUS REG_FRC_IRQ_FINAL_STATUS macro
223 #define REG_IRQ_FINAL_STATUS REG_AEON_IRQ_FINAL_STATUS macro
248 #define REG_IRQ_FINAL_STATUS REG_MIPS_IRQ_FINAL_STATUS macro
274 #define REG_IRQ_FINAL_STATUS REG_MIPS_IRQ_FINAL_STATUS macro
298 #define REG_IRQ_FINAL_STATUS REG_MIPS_IRQ_FINAL_STATUS macro
321 #define REG_IRQ_FINAL_STATUS REG_MIPS_IRQ_FINAL_STATUS macro
345 #define REG_IRQ_FINAL_STATUS REG_MIPS_IRQ_FINAL_STATUS macro
368 #define REG_IRQ_FINAL_STATUS REG_MIPS_IRQ_FINAL_STATUS macro
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| H A D | halIRQ.c | 380 status = _IRQ_Read4Byte(REG_IRQ_FINAL_STATUS); in _HAL_IRQ_IRQHnd_ARM()
516 status = _IRQ_Read4Byte(REG_IRQ_FINAL_STATUS); in _HAL_IRQ_IRQHnd()
532 status = _IRQ_Read4Byte(REG_IRQ_FINAL_STATUS); in _HAL_IRQ_IRQHnd()
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| /utopia/UTPA2-700.0.x/modules/irq/hal/macan/irq/ |
| H A D | regIRQ.h | 202 #define REG_IRQ_FINAL_STATUS REG_FRC_IRQ_FINAL_STATUS macro
223 #define REG_IRQ_FINAL_STATUS REG_AEON_IRQ_FINAL_STATUS macro
248 #define REG_IRQ_FINAL_STATUS REG_MIPS_IRQ_FINAL_STATUS macro
274 #define REG_IRQ_FINAL_STATUS REG_MIPS_IRQ_FINAL_STATUS macro
298 #define REG_IRQ_FINAL_STATUS REG_MIPS_IRQ_FINAL_STATUS macro
321 #define REG_IRQ_FINAL_STATUS REG_MIPS_IRQ_FINAL_STATUS macro
345 #define REG_IRQ_FINAL_STATUS REG_MIPS_IRQ_FINAL_STATUS macro
368 #define REG_IRQ_FINAL_STATUS REG_MIPS_IRQ_FINAL_STATUS macro
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| H A D | halIRQ.c | 374 status = _IRQ_Read4Byte(REG_IRQ_FINAL_STATUS); in _HAL_IRQ_IRQHnd_ARM()
510 status = _IRQ_Read4Byte(REG_IRQ_FINAL_STATUS); in _HAL_IRQ_IRQHnd()
526 status = _IRQ_Read4Byte(REG_IRQ_FINAL_STATUS); in _HAL_IRQ_IRQHnd()
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| /utopia/UTPA2-700.0.x/modules/irq/hal/maserati/irq/ |
| H A D | regIRQ.h | 202 #define REG_IRQ_FINAL_STATUS REG_FRC_IRQ_FINAL_STATUS macro
223 #define REG_IRQ_FINAL_STATUS REG_AEON_IRQ_FINAL_STATUS macro
248 #define REG_IRQ_FINAL_STATUS REG_MIPS_IRQ_FINAL_STATUS macro
274 #define REG_IRQ_FINAL_STATUS REG_MIPS_IRQ_FINAL_STATUS macro
298 #define REG_IRQ_FINAL_STATUS REG_MIPS_IRQ_FINAL_STATUS macro
321 #define REG_IRQ_FINAL_STATUS REG_MIPS_IRQ_FINAL_STATUS macro
345 #define REG_IRQ_FINAL_STATUS REG_MIPS_IRQ_FINAL_STATUS macro
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| H A D | halIRQ.c | 378 status = _IRQ_Read4Byte(REG_IRQ_FINAL_STATUS); in _HAL_IRQ_IRQHnd_ARM()
514 status = _IRQ_Read4Byte(REG_IRQ_FINAL_STATUS); in _HAL_IRQ_IRQHnd()
530 status = _IRQ_Read4Byte(REG_IRQ_FINAL_STATUS); in _HAL_IRQ_IRQHnd()
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| /utopia/UTPA2-700.0.x/modules/irq/hal/manhattan/irq/ |
| H A D | regIRQ.h | 202 #define REG_IRQ_FINAL_STATUS REG_FRC_IRQ_FINAL_STATUS macro
223 #define REG_IRQ_FINAL_STATUS REG_AEON_IRQ_FINAL_STATUS macro
248 #define REG_IRQ_FINAL_STATUS REG_MIPS_IRQ_FINAL_STATUS macro
274 #define REG_IRQ_FINAL_STATUS REG_MIPS_IRQ_FINAL_STATUS macro
298 #define REG_IRQ_FINAL_STATUS REG_MIPS_IRQ_FINAL_STATUS macro
321 #define REG_IRQ_FINAL_STATUS REG_MIPS_IRQ_FINAL_STATUS macro
345 #define REG_IRQ_FINAL_STATUS REG_MIPS_IRQ_FINAL_STATUS macro
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| H A D | halIRQ.c | 374 status = _IRQ_Read4Byte(REG_IRQ_FINAL_STATUS); in _HAL_IRQ_IRQHnd_ARM()
510 status = _IRQ_Read4Byte(REG_IRQ_FINAL_STATUS); in _HAL_IRQ_IRQHnd()
526 status = _IRQ_Read4Byte(REG_IRQ_FINAL_STATUS); in _HAL_IRQ_IRQHnd()
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| /utopia/UTPA2-700.0.x/modules/irq/hal/maxim/irq/ |
| H A D | regIRQ.h | 202 #define REG_IRQ_FINAL_STATUS REG_FRC_IRQ_FINAL_STATUS macro
223 #define REG_IRQ_FINAL_STATUS REG_AEON_IRQ_FINAL_STATUS macro
248 #define REG_IRQ_FINAL_STATUS REG_MIPS_IRQ_FINAL_STATUS macro
274 #define REG_IRQ_FINAL_STATUS REG_MIPS_IRQ_FINAL_STATUS macro
298 #define REG_IRQ_FINAL_STATUS REG_MIPS_IRQ_FINAL_STATUS macro
321 #define REG_IRQ_FINAL_STATUS REG_MIPS_IRQ_FINAL_STATUS macro
345 #define REG_IRQ_FINAL_STATUS REG_MIPS_IRQ_FINAL_STATUS macro
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| H A D | halIRQ.c | 378 status = _IRQ_Read4Byte(REG_IRQ_FINAL_STATUS); in _HAL_IRQ_IRQHnd_ARM()
514 status = _IRQ_Read4Byte(REG_IRQ_FINAL_STATUS); in _HAL_IRQ_IRQHnd()
530 status = _IRQ_Read4Byte(REG_IRQ_FINAL_STATUS); in _HAL_IRQ_IRQHnd()
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| /utopia/UTPA2-700.0.x/modules/irq/hal/M7621/irq/ |
| H A D | regIRQ.h | 202 #define REG_IRQ_FINAL_STATUS REG_FRC_IRQ_FINAL_STATUS macro
223 #define REG_IRQ_FINAL_STATUS REG_AEON_IRQ_FINAL_STATUS macro
248 #define REG_IRQ_FINAL_STATUS REG_MIPS_IRQ_FINAL_STATUS macro
274 #define REG_IRQ_FINAL_STATUS REG_MIPS_IRQ_FINAL_STATUS macro
298 #define REG_IRQ_FINAL_STATUS REG_MIPS_IRQ_FINAL_STATUS macro
321 #define REG_IRQ_FINAL_STATUS REG_MIPS_IRQ_FINAL_STATUS macro
345 #define REG_IRQ_FINAL_STATUS REG_MIPS_IRQ_FINAL_STATUS macro
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| H A D | halIRQ.c | 378 status = _IRQ_Read4Byte(REG_IRQ_FINAL_STATUS); in _HAL_IRQ_IRQHnd_ARM()
514 status = _IRQ_Read4Byte(REG_IRQ_FINAL_STATUS); in _HAL_IRQ_IRQHnd()
530 status = _IRQ_Read4Byte(REG_IRQ_FINAL_STATUS); in _HAL_IRQ_IRQHnd()
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| /utopia/UTPA2-700.0.x/modules/irq/hal/mustang/irq/ |
| H A D | regIRQ.h | 156 #define REG_IRQ_FINAL_STATUS REG_AEON_IRQ_FINAL_STATUS macro
173 #define REG_IRQ_FINAL_STATUS REG_MIPS_IRQ_FINAL_STATUS macro
191 #define REG_IRQ_FINAL_STATUS REG_MIPS_IRQ_FINAL_STATUS macro
207 #define REG_IRQ_FINAL_STATUS REG_MIPS_IRQ_FINAL_STATUS macro
223 #define REG_IRQ_FINAL_STATUS REG_MIPS_IRQ_FINAL_STATUS macro
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| /utopia/UTPA2-700.0.x/modules/irq/hal/maldives/irq/ |
| H A D | regIRQ.h | 156 #define REG_IRQ_FINAL_STATUS REG_AEON_IRQ_FINAL_STATUS macro
173 #define REG_IRQ_FINAL_STATUS REG_MIPS_IRQ_FINAL_STATUS macro
191 #define REG_IRQ_FINAL_STATUS REG_MIPS_IRQ_FINAL_STATUS macro
207 #define REG_IRQ_FINAL_STATUS REG_MIPS_IRQ_FINAL_STATUS macro
223 #define REG_IRQ_FINAL_STATUS REG_MIPS_IRQ_FINAL_STATUS macro
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| /utopia/UTPA2-700.0.x/modules/irq/hal/mainz/irq/ |
| H A D | regIRQ.h | 147 #define REG_IRQ_FINAL_STATUS REG_AEON_IRQ_FINAL_STATUS macro
163 #define REG_IRQ_FINAL_STATUS REG_MIPS_IRQ_FINAL_STATUS macro
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| /utopia/UTPA2-700.0.x/modules/irq/hal/mooney/irq/ |
| H A D | regIRQ.h | 147 #define REG_IRQ_FINAL_STATUS REG_AEON_IRQ_FINAL_STATUS macro
163 #define REG_IRQ_FINAL_STATUS REG_MIPS_IRQ_FINAL_STATUS macro
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| /utopia/UTPA2-700.0.x/modules/irq/hal/messi/irq/ |
| H A D | regIRQ.h | 147 #define REG_IRQ_FINAL_STATUS REG_AEON_IRQ_FINAL_STATUS macro
163 #define REG_IRQ_FINAL_STATUS REG_MIPS_IRQ_FINAL_STATUS macro
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| /utopia/UTPA2-700.0.x/modules/irq/hal/kano/irq/ |
| H A D | regIRQ.h | 160 #define REG_IRQ_FINAL_STATUS REG_AEON_IRQ_FINAL_STATUS macro
182 #define REG_IRQ_FINAL_STATUS REG_MIPS_IRQ_FINAL_STATUS macro
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| H A D | halIRQ.c | 375 status = _IRQ_Read4Byte(REG_IRQ_FINAL_STATUS); in _HAL_IRQ_IRQHnd_ARM()
487 status = _IRQ_Read4Byte(REG_IRQ_FINAL_STATUS); in _HAL_IRQ_IRQHnd()
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| /utopia/UTPA2-700.0.x/modules/irq/hal/k7u/irq/ |
| H A D | regIRQ.h | 160 #define REG_IRQ_FINAL_STATUS REG_AEON_IRQ_FINAL_STATUS macro
182 #define REG_IRQ_FINAL_STATUS REG_MIPS_IRQ_FINAL_STATUS macro
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| /utopia/UTPA2-700.0.x/modules/irq/hal/k6lite/irq/ |
| H A D | regIRQ.h | 160 #define REG_IRQ_FINAL_STATUS REG_AEON_IRQ_FINAL_STATUS macro
182 #define REG_IRQ_FINAL_STATUS REG_MIPS_IRQ_FINAL_STATUS macro
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| H A D | halIRQ.c | 375 status = _IRQ_Read4Byte(REG_IRQ_FINAL_STATUS); in _HAL_IRQ_IRQHnd_ARM()
487 status = _IRQ_Read4Byte(REG_IRQ_FINAL_STATUS); in _HAL_IRQ_IRQHnd()
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| /utopia/UTPA2-700.0.x/modules/irq/hal/curry/irq/ |
| H A D | regIRQ.h | 160 #define REG_IRQ_FINAL_STATUS REG_AEON_IRQ_FINAL_STATUS macro
182 #define REG_IRQ_FINAL_STATUS REG_MIPS_IRQ_FINAL_STATUS macro
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| /utopia/UTPA2-700.0.x/modules/irq/hal/k6/irq/ |
| H A D | regIRQ.h | 160 #define REG_IRQ_FINAL_STATUS REG_AEON_IRQ_FINAL_STATUS macro
182 #define REG_IRQ_FINAL_STATUS REG_MIPS_IRQ_FINAL_STATUS macro
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| H A D | halIRQ.c | 375 status = _IRQ_Read4Byte(REG_IRQ_FINAL_STATUS); in _HAL_IRQ_IRQHnd_ARM()
487 status = _IRQ_Read4Byte(REG_IRQ_FINAL_STATUS); in _HAL_IRQ_IRQHnd()
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