xref: /utopia/UTPA2-700.0.x/modules/irq/hal/kano/irq/regIRQ.h (revision 53ee8cc121a030b8d368113ac3e966b4705770ef)

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#ifndef _REG_IRQ_H_
#define _REG_IRQ_H_

//-------------------------------------------------------------------------------------------------
//  Hardware Capability
//-------------------------------------------------------------------------------------------------

//-------------------------------------------------------------------------------------------------
//  Macro and Define
//-------------------------------------------------------------------------------------------------
//Host 0: PM51
//Host 1: Secure R2
//Host 2: Cortex-A7 Core 0
//Host 3: Cortex-A7 Core 1

#define RIUBASE_IRQ         0x1900   //(0x101900-0x100000)
#define RIUBASE_IRQ_EXP     0x1900   //(0x101900-0x100000)
#define RIUBASE_IRQ_HYP     0x1000   //(0x101000-0x100000)

#define REG_AEON_C_FIQ_MASK                     (RIUBASE_IRQ + (0x24 << 1))
#define REG_AEON_C_FIQ_CLR                      (RIUBASE_IRQ + (0x2C << 1))
#define REG_AEON_FIQ_FINAL_STATUS               (RIUBASE_IRQ + (0x2C << 1))

#define REG_AEON_C_IRQ_MASK                     (RIUBASE_IRQ + (0x34 << 1))
#define REG_AEON_IRQ_FINAL_STATUS               (RIUBASE_IRQ + (0x3C << 1))

#define REG_AEON_C_FIQ_EXP_MASK                 (RIUBASE_IRQ_EXP + (0x26 << 1))
#define REG_AEON_C_FIQ_EXP_CLR                  (RIUBASE_IRQ_EXP + (0x2e << 1))
#define REG_AEON_C_FIQ_EXP_FINAL_STATUS         (RIUBASE_IRQ_EXP + (0x2e << 1))

#define REG_AEON_C_FIQ_HYP_MASK                 (RIUBASE_IRQ_HYP + (0x24 << 1)) //NOT EXIST NOW
#define REG_AEON_C_FIQ_HYP_CLR                  (RIUBASE_IRQ_HYP + (0x2C << 1)) //NOT EXIST NOW
#define REG_AEON_C_FIQ_HYP_FINAL_STATUS         (RIUBASE_IRQ_HYP + (0x2C << 1)) //NOT EXIST NOW
#define REG_AEON_C_IRQ_EXP_MASK                 (RIUBASE_IRQ_EXP + (0x36 << 1))
#define REG_AEON_C_IRQ_EXP_FINAL_STATUS         (RIUBASE_IRQ_EXP + (0x3e << 1))

#define REG_AEON_C_IRQ_HYP_MASK                 (RIUBASE_IRQ_HYP + (0x34 << 1)) //NOT EXIST NOW
#define REG_AEON_C_IRQ_HYP_FINAL_STATUS         (RIUBASE_IRQ_HYP + (0x3C << 1)) //NOT EXIST NOW

#define REG_MIPS_C_FIQ_MASK                     (RIUBASE_IRQ + (0x44 << 1))
#define REG_MIPS_C_FIQ_CLR                      (RIUBASE_IRQ + (0x4c << 1))
#define REG_MIPS_FIQ_FINAL_STATUS               (RIUBASE_IRQ + (0x4c << 1))

#define REG_MIPS_C_IRQ_MASK                     (RIUBASE_IRQ + (0x54 << 1))
#define REG_MIPS_IRQ_FINAL_STATUS               (RIUBASE_IRQ + (0x5c << 1))

#define REG_MIPS_C_FIQ_EXP_MASK                 (RIUBASE_IRQ_EXP + (0x46 << 1))
#define REG_MIPS_C_FIQ_EXP_CLR                  (RIUBASE_IRQ_EXP + (0x4e << 1))
#define REG_MIPS_C_FIQ_EXP_FINAL_STATUS         (RIUBASE_IRQ_EXP + (0x4e << 1))

#define REG_MIPS_C_FIQ_HYP_MASK                 (RIUBASE_IRQ_HYP + (0x44 << 1))
#define REG_MIPS_C_FIQ_HYP_CLR                  (RIUBASE_IRQ_HYP + (0x4C << 1))
#define REG_MIPS_C_FIQ_HYP_FINAL_STATUS         (RIUBASE_IRQ_HYP + (0x4C << 1))
#define REG_MIPS_C_IRQ_EXP_MASK                 (RIUBASE_IRQ_EXP + (0x56 << 1))
#define REG_MIPS_C_IRQ_EXP_FINAL_STATUS         (RIUBASE_IRQ_EXP + (0x5e << 1))

#define REG_MIPS_C_IRQ_HYP_MASK                 (RIUBASE_IRQ_HYP + (0x54 << 1))
#define REG_MIPS_C_IRQ_HYP_FINAL_STATUS         (RIUBASE_IRQ_HYP + (0x5C << 1))
#ifdef MCU_AEON

#define REG_C_FIQ_MASK                          REG_AEON_C_FIQ_MASK
#define REG_C_FIQ_CLR                           REG_AEON_C_FIQ_CLR
#define REG_FIQ_FINAL_STATUS                    REG_AEON_FIQ_FINAL_STATUS

#define REG_C_IRQ_MASK                          REG_AEON_C_IRQ_MASK
#define REG_IRQ_FINAL_STATUS                    REG_AEON_IRQ_FINAL_STATUS

#define REG_C_FIQ_EXP_MASK                      REG_AEON_C_FIQ_EXP_MASK
#define REG_C_FIQ_EXP_CLR                       REG_AEON_C_FIQ_EXP_CLR
#define REG_C_FIQ_EXP_FINAL_STATUS              REG_AEON_C_FIQ_EXP_FINAL_STATUS

#define REG_C_FIQ_HYP_MASK                      REG_AEON_C_FIQ_HYP_MASK
#define REG_C_FIQ_HYP_CLR                       REG_AEON_C_FIQ_HYP_CLR
#define REG_C_FIQ_HYP_FINAL_STATUS              REG_AEON_C_FIQ_HYP_FINAL_STATUS

#define REG_C_IRQ_EXP_MASK                      REG_AEON_C_IRQ_EXP_MASK
#define REG_C_IRQ_EXP_FINAL_STATUS              REG_AEON_C_IRQ_EXP_FINAL_STATUS

#define REG_C_IRQ_HYP_MASK                      REG_AEON_C_IRQ_HYP_MASK
#define REG_C_IRQ_HYP_FINAL_STATUS              REG_AEON_C_IRQ_HYP_FINAL_STATUS
#else

#define REG_C_FIQ_MASK                          REG_MIPS_C_FIQ_MASK
#define REG_C_FIQ_CLR                           REG_MIPS_C_FIQ_CLR
#define REG_FIQ_FINAL_STATUS                    REG_MIPS_FIQ_FINAL_STATUS

#define REG_C_IRQ_MASK                          REG_MIPS_C_IRQ_MASK
#define REG_IRQ_FINAL_STATUS                    REG_MIPS_IRQ_FINAL_STATUS

#define REG_C_FIQ_EXP_MASK                      REG_MIPS_C_FIQ_EXP_MASK
#define REG_C_FIQ_EXP_CLR                       REG_MIPS_C_FIQ_EXP_CLR
#define REG_C_FIQ_EXP_FINAL_STATUS              REG_MIPS_C_FIQ_EXP_FINAL_STATUS

#define REG_C_FIQ_HYP_MASK                      REG_MIPS_C_FIQ_HYP_MASK
#define REG_C_FIQ_HYP_CLR                       REG_MIPS_C_FIQ_HYP_CLR
#define REG_C_FIQ_HYP_FINAL_STATUS              REG_MIPS_C_FIQ_HYP_FINAL_STATUS

#define REG_C_IRQ_EXP_MASK                      REG_MIPS_C_IRQ_EXP_MASK
#define REG_C_IRQ_EXP_FINAL_STATUS              REG_MIPS_C_IRQ_EXP_FINAL_STATUS

#define REG_C_IRQ_HYP_MASK                      REG_MIPS_C_IRQ_HYP_MASK
#define REG_C_IRQ_HYP_FINAL_STATUS              REG_MIPS_C_IRQ_HYP_FINAL_STATUS

#endif

/*
#define REG_SEND_IRQ_FROM_CPU0                  (RIUBASE_IRQ + 0x7C)
#define REG_SEND_IRQ_FROM_CPU1                  (RIUBASE_IRQ + 0x7E)
#define REG_SEND_IRQ_FROM_CPU2                  (RIUBASE_IRQ_AEON1 + 0x7E)
*/

//-------------------------------------------------------------------------------------------------
//  Type and Structure
//-------------------------------------------------------------------------------------------------


#endif // _REG_IRQ_H_