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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 #ifndef _REG_IRQ_H_ 96 #define _REG_IRQ_H_ 97 98 //------------------------------------------------------------------------------------------------- 99 // Hardware Capability 100 //------------------------------------------------------------------------------------------------- 101 102 //------------------------------------------------------------------------------------------------- 103 // Macro and Define 104 //------------------------------------------------------------------------------------------------- 105 //Host 0: PM51 106 //Host 1: Secure R2 107 //Host 2: Cortex-A7 Core 0 108 //Host 3: Cortex-A7 Core 1 109 110 #define RIUBASE_IRQ 0x1900 //(0x101900-0x100000) 111 #define RIUBASE_IRQ_EXP 0x1900 //(0x101900-0x100000) 112 #define RIUBASE_IRQ_HYP 0x1000 //(0x101000-0x100000) 113 114 #define REG_AEON_C_FIQ_MASK (RIUBASE_IRQ + (0x24 << 1)) 115 #define REG_AEON_C_FIQ_CLR (RIUBASE_IRQ + (0x2C << 1)) 116 #define REG_AEON_FIQ_FINAL_STATUS (RIUBASE_IRQ + (0x2C << 1)) 117 118 #define REG_AEON_C_IRQ_MASK (RIUBASE_IRQ + (0x34 << 1)) 119 #define REG_AEON_IRQ_FINAL_STATUS (RIUBASE_IRQ + (0x3C << 1)) 120 121 #define REG_AEON_C_FIQ_EXP_MASK (RIUBASE_IRQ_EXP + (0x26 << 1)) 122 #define REG_AEON_C_FIQ_EXP_CLR (RIUBASE_IRQ_EXP + (0x2e << 1)) 123 #define REG_AEON_C_FIQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + (0x2e << 1)) 124 125 #define REG_AEON_C_FIQ_HYP_MASK (RIUBASE_IRQ_HYP + (0x24 << 1)) //NOT EXIST NOW 126 #define REG_AEON_C_FIQ_HYP_CLR (RIUBASE_IRQ_HYP + (0x2C << 1)) //NOT EXIST NOW 127 #define REG_AEON_C_FIQ_HYP_FINAL_STATUS (RIUBASE_IRQ_HYP + (0x2C << 1)) //NOT EXIST NOW 128 #define REG_AEON_C_IRQ_EXP_MASK (RIUBASE_IRQ_EXP + (0x36 << 1)) 129 #define REG_AEON_C_IRQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + (0x3e << 1)) 130 131 #define REG_AEON_C_IRQ_HYP_MASK (RIUBASE_IRQ_HYP + (0x34 << 1)) //NOT EXIST NOW 132 #define REG_AEON_C_IRQ_HYP_FINAL_STATUS (RIUBASE_IRQ_HYP + (0x3C << 1)) //NOT EXIST NOW 133 134 #define REG_MIPS_C_FIQ_MASK (RIUBASE_IRQ + (0x44 << 1)) 135 #define REG_MIPS_C_FIQ_CLR (RIUBASE_IRQ + (0x4c << 1)) 136 #define REG_MIPS_FIQ_FINAL_STATUS (RIUBASE_IRQ + (0x4c << 1)) 137 138 #define REG_MIPS_C_IRQ_MASK (RIUBASE_IRQ + (0x54 << 1)) 139 #define REG_MIPS_IRQ_FINAL_STATUS (RIUBASE_IRQ + (0x5c << 1)) 140 141 #define REG_MIPS_C_FIQ_EXP_MASK (RIUBASE_IRQ_EXP + (0x46 << 1)) 142 #define REG_MIPS_C_FIQ_EXP_CLR (RIUBASE_IRQ_EXP + (0x4e << 1)) 143 #define REG_MIPS_C_FIQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + (0x4e << 1)) 144 145 #define REG_MIPS_C_FIQ_HYP_MASK (RIUBASE_IRQ_HYP + (0x44 << 1)) 146 #define REG_MIPS_C_FIQ_HYP_CLR (RIUBASE_IRQ_HYP + (0x4C << 1)) 147 #define REG_MIPS_C_FIQ_HYP_FINAL_STATUS (RIUBASE_IRQ_HYP + (0x4C << 1)) 148 #define REG_MIPS_C_IRQ_EXP_MASK (RIUBASE_IRQ_EXP + (0x56 << 1)) 149 #define REG_MIPS_C_IRQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + (0x5e << 1)) 150 151 #define REG_MIPS_C_IRQ_HYP_MASK (RIUBASE_IRQ_HYP + (0x54 << 1)) 152 #define REG_MIPS_C_IRQ_HYP_FINAL_STATUS (RIUBASE_IRQ_HYP + (0x5C << 1)) 153 #ifdef MCU_AEON 154 155 #define REG_C_FIQ_MASK REG_AEON_C_FIQ_MASK 156 #define REG_C_FIQ_CLR REG_AEON_C_FIQ_CLR 157 #define REG_FIQ_FINAL_STATUS REG_AEON_FIQ_FINAL_STATUS 158 159 #define REG_C_IRQ_MASK REG_AEON_C_IRQ_MASK 160 #define REG_IRQ_FINAL_STATUS REG_AEON_IRQ_FINAL_STATUS 161 162 #define REG_C_FIQ_EXP_MASK REG_AEON_C_FIQ_EXP_MASK 163 #define REG_C_FIQ_EXP_CLR REG_AEON_C_FIQ_EXP_CLR 164 #define REG_C_FIQ_EXP_FINAL_STATUS REG_AEON_C_FIQ_EXP_FINAL_STATUS 165 166 #define REG_C_FIQ_HYP_MASK REG_AEON_C_FIQ_HYP_MASK 167 #define REG_C_FIQ_HYP_CLR REG_AEON_C_FIQ_HYP_CLR 168 #define REG_C_FIQ_HYP_FINAL_STATUS REG_AEON_C_FIQ_HYP_FINAL_STATUS 169 170 #define REG_C_IRQ_EXP_MASK REG_AEON_C_IRQ_EXP_MASK 171 #define REG_C_IRQ_EXP_FINAL_STATUS REG_AEON_C_IRQ_EXP_FINAL_STATUS 172 173 #define REG_C_IRQ_HYP_MASK REG_AEON_C_IRQ_HYP_MASK 174 #define REG_C_IRQ_HYP_FINAL_STATUS REG_AEON_C_IRQ_HYP_FINAL_STATUS 175 #else 176 177 #define REG_C_FIQ_MASK REG_MIPS_C_FIQ_MASK 178 #define REG_C_FIQ_CLR REG_MIPS_C_FIQ_CLR 179 #define REG_FIQ_FINAL_STATUS REG_MIPS_FIQ_FINAL_STATUS 180 181 #define REG_C_IRQ_MASK REG_MIPS_C_IRQ_MASK 182 #define REG_IRQ_FINAL_STATUS REG_MIPS_IRQ_FINAL_STATUS 183 184 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK 185 #define REG_C_FIQ_EXP_CLR REG_MIPS_C_FIQ_EXP_CLR 186 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS 187 188 #define REG_C_FIQ_HYP_MASK REG_MIPS_C_FIQ_HYP_MASK 189 #define REG_C_FIQ_HYP_CLR REG_MIPS_C_FIQ_HYP_CLR 190 #define REG_C_FIQ_HYP_FINAL_STATUS REG_MIPS_C_FIQ_HYP_FINAL_STATUS 191 192 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK 193 #define REG_C_IRQ_EXP_FINAL_STATUS REG_MIPS_C_IRQ_EXP_FINAL_STATUS 194 195 #define REG_C_IRQ_HYP_MASK REG_MIPS_C_IRQ_HYP_MASK 196 #define REG_C_IRQ_HYP_FINAL_STATUS REG_MIPS_C_IRQ_HYP_FINAL_STATUS 197 198 #endif 199 200 /* 201 #define REG_SEND_IRQ_FROM_CPU0 (RIUBASE_IRQ + 0x7C) 202 #define REG_SEND_IRQ_FROM_CPU1 (RIUBASE_IRQ + 0x7E) 203 #define REG_SEND_IRQ_FROM_CPU2 (RIUBASE_IRQ_AEON1 + 0x7E) 204 */ 205 206 //------------------------------------------------------------------------------------------------- 207 // Type and Structure 208 //------------------------------------------------------------------------------------------------- 209 210 211 #endif // _REG_IRQ_H_ 212