1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
5 // All software, firmware and related documentation herein ("MStar Software") are
6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by
7 // law, including, but not limited to, copyright law and international treaties.
8 // Any use, modification, reproduction, retransmission, or republication of all
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10 // permission has been granted by MStar.
11 //
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15 //
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19 // modification/derivatives thereof is transferred to you under Terms.
20 //
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32 //
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75 //
76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc.
81 // All rights reserved.
82 //
83 // Unless otherwise stipulated in writing, any and all information contained
84 // herein regardless in any format shall remain the sole proprietary of
85 // MStar Semiconductor Inc. and be kept in strict confidence
86 // ("MStar Confidential Information") by the recipient.
87 // Any unauthorized act including without limitation unauthorized disclosure,
88 // copying, use, reproduction, sale, distribution, modification, disassembling,
89 // reverse engineering and compiling of the contents of MStar Confidential
90 // Information is unlawful and strictly prohibited. MStar hereby reserves the
91 // rights to any and all damages, losses, costs and expenses resulting therefrom.
92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95 #if defined(MSOS_TYPE_NOS) || defined(MSOS_TYPE_NUTTX)
96
97 //-------------------------------------------------------------------------------------------------
98 // Include Files
99 //-------------------------------------------------------------------------------------------------
100 #include "MsCommon.h"
101 #include "MsOS.h"
102 #include "halIRQTBL.h"
103 #include "regCHIP.h"
104 #include "drvIRQ.h"
105 #include "halIRQ.h"
106 #include "regIRQ.h"
107
108 #if defined(MSOS_TYPE_NUTTX)
109 #include "debug.h"
110 #endif
111
112 #define MST_MACRO_START do {
113 #define MST_MACRO_END } while (0)
114
115 #if defined (__mips__)
116 #define mtspr(spr, value) printf("[NIY] mtspr in line:%s %d\n",__FILE__, __LINE__);
117 #define mfspr(spr) printf("[NIY] mfspr in line:%s %d\n",__FILE__, __LINE__);
118
__mhal_lsbit_index(MS_U32 _value_)119 inline MS_U32 __mhal_lsbit_index(MS_U32 _value_)
120 {
121 MS_U32 index = 1;
122
123 while((_value_&0x01) == 0x00)
124 {
125 _value_ = (_value_ >> 1);
126 index++;
127 if(index == 32)
128 {
129 index = 0;
130 break;
131 }
132 }
133
134 return index;
135 //printf(const char * fmt, ...)("[NIY] __mhal_lsbit_index in line: %s %d\n",__FILE__, __LINE__);
136 }
137
138
139 #define __mhal_interrupt_disable(_old_) (_old_=_old_)
140
141 #define __mhal_interrupt_restore(_old_) (_old_=_old_)
142
143 #elif defined (__arm__)
144 #define mtspr(spr, value) printf("[NIY] mtspr in line:%s %d\n",__FILE__, __LINE__);
145 #define mfspr(spr) printf("[NIY] mfspr in line:%s %d\n",__FILE__, __LINE__);
146
__mhal_lsbit_index(MS_U32 _value_)147 inline MS_U32 __mhal_lsbit_index(MS_U32 _value_)
148 {
149 MS_U32 index = 1;
150
151 while((_value_&0x01) == 0x00)
152 {
153 _value_ = (_value_ >> 1);
154 index++;
155 if(index == 32)
156 {
157 index = 0;
158 break;
159 }
160 }
161
162 return index;
163 //printf(const char * fmt, ...)("[NIY] __mhal_lsbit_index in line: %s %d\n",__FILE__, __LINE__);
164 }
165
166
167 #define __mhal_interrupt_disable(_old_) (_old_=_old_)
168
169 #define __mhal_interrupt_restore(_old_) (_old_=_old_)
170 #else
171 #define mtspr(spr, value) \
172 __asm__ __volatile__ ("l.mtspr\t\t%0,%1,0" : : "r" (spr), "r" (value))
173
174 #define mfspr(spr) \
175 ({ \
176 unsigned long value; \
177 __asm__ __volatile__ ("l.mfspr\t\t%0,%1,0" : "=r" (value) : "r" (spr) : "memory"); \
178 value; \
179 })
180
181 #define __mhal_lsbit_index(_value_) \
182 ({ \
183 unsigned long _index_; \
184 __asm__ __volatile__ ("l.ff1\t\t%0,%1" : "=r" (_index_) : "r" (_value_));\
185 _index_; \
186 })
187
188
189 #define GRP_BITS (11)
190 #define SPR_SR ((0 << GRP_BITS) + 17)
191 #define SPR_SR_TEE 0x00000002 // Tick timer Exception Enable
192 #define SPR_SR_IEE 0x00000004 // Interrupt Exception Enable
193
194 #define __mhal_interrupt_disable(_old_) \
195 MST_MACRO_START \
196 _old_ = mfspr(SPR_SR); \
197 mtspr(SPR_SR, (_old_) & ~(SPR_SR_IEE | SPR_SR_TEE)); \
198 MST_MACRO_END
199
200 #define __mhal_interrupt_restore(_old_) \
201 mtspr(SPR_SR, (~(SPR_SR_IEE|SPR_SR_TEE) & mfspr(SPR_SR) ) | \
202 ( (SPR_SR_IEE|SPR_SR_TEE) & (_old_) ))
203 #endif
204
205
206 //-------------------------------------------------------------------------------------------------
207 // Driver Compiler Options
208 //-------------------------------------------------------------------------------------------------
209
210
211 //-------------------------------------------------------------------------------------------------
212 // Local Defines
213 //-------------------------------------------------------------------------------------------------
214 #define COUNTOF( array ) (sizeof(array) / sizeof((array)[0]))
215 //#define E_INTERRUPT_FIQ E_INTERRUPT_02
216 //#define E_INTERRUPT_IRQ E_INTERRUPT_03
217
218 //-------------------------------------------------------------------------------------------------
219 // Local Structures
220 //-------------------------------------------------------------------------------------------------
221 typedef void (*IRQCb)(MS_U32 u32Vector);
222
223 //-------------------------------------------------------------------------------------------------
224 // Global Variables
225 //-------------------------------------------------------------------------------------------------
226
227
228 //-------------------------------------------------------------------------------------------------
229 // Local Variables
230 //-------------------------------------------------------------------------------------------------
231 static IRQCb irq_table[E_IRQ_FIQ_ALL] = {0};
232 // static MS_U32 _u32FIQ, _u32IRQ, _u32FIQExp, _u32IRQExp, _u32MIO_MapBase = 0;
233 static MS_U32 _u32FIQ_Msk, _u32IRQ_Msk, _u32FIQExp_Msk, _u32IRQExp_Msk;
234
235 #if defined(MCU_AEON)
236 static MS_U32 _u32MIO_MapBase= 0xFA200000;
237 #elif defined(MCU_ARM_CA12)
238 #ifdef CONFIG_MBOOT
239 static MS_U32 _u32MIO_MapBase= 0x1f200000;
240 #else
241 static MS_U32 _u32MIO_MapBase= 0xfd200000;
242 #endif
243 #else
244 static MS_U32 _u32MIO_MapBase= 0xbf200000;
245 #endif
246
247 static MS_BOOL _bInIRQ = FALSE, _bInFIQ = FALSE;
248
249 //-------------------------------------------------------------------------------------------------
250 // External Functions
251 //-------------------------------------------------------------------------------------------------
252
253 #define REG16_R(u32RegAddr) ((*((volatile MS_U16*)(_u32MIO_MapBase+ ((u32RegAddr)<< 1)))) & 0xFFFF)
254 #define REG16_W(u32RegAddr, u32Value) (*((volatile MS_U32*)(_u32MIO_MapBase+ ((u32RegAddr)<< 1))))= ((u32Value) & 0xFFFF)
255
256 /*
257 static MS_U16 REG16_R(MS_U32 u32RegAddr_in)
258 {
259 MS_U32 u32RegAddr1 = (u32RegAddr_in << 1);
260 MS_U32 u32RegAddr = (_u32MIO_MapBase+ (u32RegAddr1));
261 MS_U16 u16RegValue = (*((volatile MS_U16*)(u32RegAddr)) & 0xFFFF);
262
263 printf("[%s][%d] 0x%08x, 0x%08x\n", __FUNCTION__, __LINE__, u32RegAddr, u16RegValue);
264 return u16RegValue;
265 }
266
267 static MS_U16 REG16_W(MS_U32 u32RegAddr_in, MS_U32 u32Value)
268 {
269 MS_U32 u32RegAddr1 = (u32RegAddr_in << 1);
270 MS_U32 u32RegAddr = (_u32MIO_MapBase+ (u32RegAddr1));
271 *((volatile MS_U16*)(u32RegAddr)) = ((u32Value) & 0xFFFF);
272
273 // printf("[%s][%d] 0x%08x, 0x%08x\n", __FUNCTION__, __LINE__, u32RegAddr, u32Value);
274 // REG16_R(u32RegAddr_in);
275 }
276 */
277
278 //-------------------------------------------------------------------------------------------------
279 // Local Functions
280 //-------------------------------------------------------------------------------------------------
281 static void _HAL_IRQ_Enable(MS_U32 u32Vector, int enable);
282
_IRQ_Read2Byte(MS_U32 u32RegAddr)283 static MS_U16 _IRQ_Read2Byte(MS_U32 u32RegAddr)
284 {
285 return REG16_R(u32RegAddr);
286 }
287
_IRQ_Read4Byte(MS_U32 u32RegAddr)288 static MS_U32 _IRQ_Read4Byte(MS_U32 u32RegAddr)
289 {
290 return (_IRQ_Read2Byte(u32RegAddr) | _IRQ_Read2Byte(u32RegAddr+2) << 16);
291 }
292
293 #if 0
294 static void _IRQ_WriteByte(MS_U32 u32RegAddr, MS_U8 u8Val)
295 {
296 if (u32RegAddr & 1)
297 {
298 REG16_W(u32RegAddr, (REG16_R(u32RegAddr) & ~(0xFF00))| (u8Val<< 8));
299 }
300 else
301 {
302 REG16_W(u32RegAddr, (REG16_R(u32RegAddr) & ~(0x00FF))| (u8Val));
303 }
304 }
305 #endif
306
_IRQ_Write2Byte(MS_U32 u32RegAddr,MS_U16 u16Val)307 static void _IRQ_Write2Byte(MS_U32 u32RegAddr, MS_U16 u16Val)
308 {
309 REG16_W(u32RegAddr, u16Val);
310 }
311
_IRQ_Write4Byte(MS_U32 u32RegAddr,MS_U32 u32Val)312 static void _IRQ_Write4Byte(MS_U32 u32RegAddr, MS_U32 u32Val)
313 {
314 _IRQ_Write2Byte(u32RegAddr, u32Val & 0x0000FFFF);
315 _IRQ_Write2Byte(u32RegAddr+2, u32Val >> 16);
316 }
317
318 #if defined(MCU_ARM_CA12)
_HAL_IRQ_FIQHnd_ARM(void)319 static void _HAL_IRQ_FIQHnd_ARM(void)
320 {
321 MS_U32 status;
322 MS_U32 index;
323
324 _bInFIQ = TRUE;
325 status = _IRQ_Read4Byte(REG_FIQ_FINAL_STATUS);
326
327 index = __mhal_lsbit_index(status);
328 if (index)
329 {
330
331 _IRQ_Write4Byte(REG_C_FIQ_CLR + 0, status);
332 _IRQ_Write4Byte(REG_C_FIQ_CLR + 0, 0);
333
334 do
335 {
336 status &= ~(1 << --index);
337 index += (MS_U32)E_FIQL_START;
338 if (irq_table[index])
339 {
340 _HAL_IRQ_Enable(index, DISABLE);
341 irq_table[index](HWIdx2IntEnum[index]);
342 }
343 index = __mhal_lsbit_index(status);
344 } while (index);
345 }
346
347 status = _IRQ_Read4Byte(REG_C_FIQ_EXP_FINAL_STATUS);
348
349 index = __mhal_lsbit_index(status);
350 if (index)
351 {
352 _IRQ_Write4Byte(REG_C_FIQ_EXP_CLR, status);
353 _IRQ_Write4Byte(REG_C_FIQ_EXP_CLR, 0);
354 do {
355 status &= ~(1 << --index);
356 index += (MS_U32)E_FIQEXPL_START;
357 if (irq_table[index])
358 {
359 _HAL_IRQ_Enable(index, DISABLE);
360 irq_table[index](HWIdx2IntEnum[index]);
361 }
362 index = __mhal_lsbit_index(status);
363 } while (index);
364 }
365 _bInFIQ = FALSE;
366 }
367
_HAL_IRQ_IRQHnd_ARM(void)368 static void _HAL_IRQ_IRQHnd_ARM(void)
369 {
370 MS_U32 status;
371 MS_U32 index;
372
373 _bInIRQ = TRUE;
374 status = _IRQ_Read4Byte(REG_IRQ_FINAL_STATUS);
375 index = __mhal_lsbit_index(status);
376 if (index)
377 {
378 do {
379 status &= ~(1 << --index);
380 index += (MS_U32)E_IRQL_START;
381 if (irq_table[index])
382 {
383 _HAL_IRQ_Enable(index, DISABLE);
384 //fix Uart Rx interrupt can't work
385 irq_table[index](HWIdx2IntEnum[index]);
386 }
387 index = __mhal_lsbit_index(status);
388 } while (index);
389 }
390
391 status = _IRQ_Read4Byte(REG_C_IRQ_EXP_FINAL_STATUS);
392 index = __mhal_lsbit_index(status);
393 if (index)
394 {
395 do {
396 status &= ~(1 << --index);
397 index += (MS_U32)E_IRQEXPL_START;
398 if (irq_table[index])
399 {
400 _HAL_IRQ_Enable(index, DISABLE);
401 irq_table[index](HWIdx2IntEnum[index]);
402 }
403 index = __mhal_lsbit_index(status);
404 } while (index);
405 }
406 _bInIRQ = FALSE;
407 }
408
409 #else
_HAL_IRQ_FIQHnd(MHAL_SavedRegisters * pHalReg,MS_U32 u32Vector)410 static void _HAL_IRQ_FIQHnd(MHAL_SavedRegisters *pHalReg, MS_U32 u32Vector)
411 {
412 MS_U32 status;
413 MS_U32 index;
414
415 _bInFIQ = TRUE;
416
417 #if defined(CONFIG_FRC)//frcr2_integration###
418 status = _IRQ_Read4Byte(REG_FIQ_FINAL_STATUS);
419 index = __mhal_lsbit_index(status);
420 if (index)
421 {
422
423 _IRQ_Write4Byte(REG_C_FIQ_CLR + 0, status);
424 _IRQ_Write4Byte(REG_C_FIQ_CLR + 0, 0);
425
426 do
427 {
428 status &= ~(1 << --index);
429 index += (MS_U32)E_FIQL_START;
430 if (irq_table[index])
431 {
432 _HAL_IRQ_Enable(index, DISABLE);
433 irq_table[index](HWIdx2IntEnum[index]);
434 }
435 index = __mhal_lsbit_index(status);
436 } while (index);
437 }
438 #else
439 status = _IRQ_Read4Byte(REG_FIQ_FINAL_STATUS);
440 index = __mhal_lsbit_index(status);
441 if (index)
442 {
443
444 _IRQ_Write4Byte(REG_C_FIQ_CLR + 0, status);
445 _IRQ_Write4Byte(REG_C_FIQ_CLR + 0, 0);
446
447 do
448 {
449 status &= ~(1 << --index);
450 index += (MS_U32)E_FIQL_START;
451 if (irq_table[index])
452 {
453 _HAL_IRQ_Enable(index, DISABLE);
454 irq_table[index](HWIdx2IntEnum[index]);
455 }
456 index = __mhal_lsbit_index(status);
457 } while (index);
458 }
459
460 status = _IRQ_Read4Byte(REG_C_FIQ_EXP_FINAL_STATUS);
461
462 index = __mhal_lsbit_index(status);
463 if (index)
464 {
465 _IRQ_Write4Byte(REG_C_FIQ_EXP_CLR, status);
466 _IRQ_Write4Byte(REG_C_FIQ_EXP_CLR, 0);
467 do {
468 status &= ~(1 << --index);
469 index += (MS_U32)E_FIQEXPL_START;
470 if (irq_table[index])
471 {
472 _HAL_IRQ_Enable(index, DISABLE);
473 irq_table[index](HWIdx2IntEnum[index]);
474 }
475 index = __mhal_lsbit_index(status);
476 } while (index);
477 }
478
479 status = _IRQ_Read4Byte(REG_C_FIQ_HYP_FINAL_STATUS);
480
481 index = __mhal_lsbit_index(status);
482 if (index)
483 {
484 _IRQ_Write4Byte(REG_C_FIQ_HYP_CLR, status);
485 _IRQ_Write4Byte(REG_C_FIQ_HYP_CLR, 0);
486 do {
487 status &= ~(1 << --index);
488 index += (MS_U32)E_FIQHYPL_START;
489 if (irq_table[index])
490 {
491 _HAL_IRQ_Enable(index, DISABLE);
492 irq_table[index](HWIdx2IntEnum[index]);
493 }
494 index = __mhal_lsbit_index(status);
495 } while (index);
496 }
497 #endif
498
499 _bInFIQ = FALSE;
500 }
501
_HAL_IRQ_IRQHnd(MHAL_SavedRegisters * pHalReg,MS_U32 u32Vector)502 static void _HAL_IRQ_IRQHnd(MHAL_SavedRegisters *pHalReg, MS_U32 u32Vector)
503 {
504 MS_U32 status;
505 MS_U32 index;
506
507 _bInIRQ = TRUE;
508
509 #if defined(CONFIG_FRC)//frcr2_integration###
510 status = _IRQ_Read4Byte(REG_IRQ_FINAL_STATUS);
511 index = __mhal_lsbit_index(status);
512 if (index)
513 {
514 do {
515 status &= ~(1 << --index);
516 index += (MS_U32)E_IRQL_START;
517 if (irq_table[index])
518 {
519 _HAL_IRQ_Enable(index, DISABLE);
520 irq_table[index](HWIdx2IntEnum[index]);
521 }
522 index = __mhal_lsbit_index(status);
523 } while (index);
524 }
525 #else
526 status = _IRQ_Read4Byte(REG_IRQ_FINAL_STATUS);
527 index = __mhal_lsbit_index(status);
528 if (index)
529 {
530 do {
531 status &= ~(1 << --index);
532 index += (MS_U32)E_IRQL_START;
533 if (irq_table[index])
534 {
535 _HAL_IRQ_Enable(index, DISABLE);
536 // This is for UART debug to get CPU registers temp solution.
537 // Todo: Should modify the interface to let CPU registers
538 // pointer pass to Callback funtion
539 if (HWIdx2IntEnum[index] == E_INT_IRQ_UART0)
540 {
541 irq_table[index]((MS_U32)pHalReg);
542 }
543 else
544 {
545 irq_table[index](HWIdx2IntEnum[index]);
546 }
547 }
548 index = __mhal_lsbit_index(status);
549 } while (index);
550 }
551
552 status = _IRQ_Read4Byte(REG_C_IRQ_EXP_FINAL_STATUS);
553 index = __mhal_lsbit_index(status);
554 if (index)
555 {
556 do {
557 status &= ~(1 << --index);
558 index += (MS_U32)E_IRQEXPL_START;
559 if (irq_table[index])
560 {
561 _HAL_IRQ_Enable(index, DISABLE);
562 if (HWIdx2IntEnum[index] == E_INT_IRQ_FRC_INT_FIQ2HST0)//frcr2_integration###
563 {
564 MS_U32 reg = E_IRQ_FIQ_INVALID;
565 MS_U32 status_frc;
566
567 irq_table[index](HWIdx2IntEnum[index]);
568 //clear frc fiq status
569 reg = REG_FRC_C_FIQ_CLR;
570 if((reg-RIUBASE_IRQ_FRC) >= (0x20*2))//clear Host0 status for FRC
571 {
572 reg -= (0x20*2);
573 status_frc = _IRQ_Read4Byte(reg);
574 _IRQ_Write4Byte(reg, status_frc);
575 _IRQ_Write4Byte(reg, 0);
576 }
577 }
578 else
579 {
580 irq_table[index](HWIdx2IntEnum[index]);
581 }
582 }
583 index = __mhal_lsbit_index(status);
584 } while (index);
585 }
586
587 status = _IRQ_Read4Byte(REG_C_IRQ_HYP_FINAL_STATUS);
588 index = __mhal_lsbit_index(status);
589 if (index)
590 {
591 do {
592 status &= ~(1 << --index);
593 index += (MS_U32)E_IRQHYPL_START;
594 if (irq_table[index])
595 {
596 _HAL_IRQ_Enable(index, DISABLE);
597 irq_table[index](HWIdx2IntEnum[index]);
598 }
599 index = __mhal_lsbit_index(status);
600 } while (index);
601 }
602 #endif
603
604 _bInIRQ = FALSE;
605 }
606 #endif
607
_HAL_IRQ_Enable(MS_U32 u32Vector,int enable)608 static void _HAL_IRQ_Enable(MS_U32 u32Vector, int enable)
609 {
610 MS_U32 reg = E_IRQ_FIQ_INVALID;
611 MS_U32 mask;
612 MS_U32 old = 0;
613
614 if ((MS_U32)u32Vector <= COUNTOF(irq_table))
615 {
616 if ( (u32Vector >= E_IRQL_START) && (u32Vector <= E_IRQH_END) )
617 {
618 u32Vector -= E_IRQL_START;
619 reg = REG_C_IRQ_MASK;
620 }
621 else if ( (u32Vector >= E_FIQL_START) && (u32Vector <= E_FIQH_END) )
622 {
623 u32Vector -= E_FIQL_START;
624 reg = REG_C_FIQ_MASK;
625 #if defined(CONFIG_FRC)//frcr2_integration###
626 if(u32Vector==E_IRQ_03)
627 {
628 if((reg-RIUBASE_IRQ_FRC) >= (0x20*2))
629 reg -= (0x20*2);
630 }
631 #endif
632 }
633 else if ( (u32Vector >= E_IRQEXPL_START) && (u32Vector <= E_IRQEXPH_END) )
634 {
635 u32Vector -= E_IRQEXPL_START;
636 reg = REG_C_IRQ_EXP_MASK;
637 }
638 else if ( (u32Vector >= E_FIQEXPL_START) && (u32Vector <= E_FIQEXPH_END) )
639 {
640 u32Vector -= E_FIQEXPL_START;
641 reg = REG_C_FIQ_EXP_MASK;
642 }
643 else if ( (u32Vector >= E_IRQHYPL_START) && (u32Vector <= E_IRQHYPH_END) )
644 {
645 u32Vector -= E_IRQHYPL_START;
646 reg = REG_C_IRQ_HYP_MASK;
647 }
648 else if ( (u32Vector >= E_FIQHYPL_START) && (u32Vector <= E_FIQHYPH_END) )
649 {
650 u32Vector -= E_FIQHYPL_START;
651 reg = REG_C_FIQ_HYP_MASK;
652 }
653
654 if( E_IRQ_FIQ_INVALID == reg )
655 {
656 //printf("_HAL_IRQ_Enable: unknow vector\n");
657 return;
658 }
659
660 __mhal_interrupt_disable(old);
661 mask = _IRQ_Read4Byte(reg);
662 u32Vector = (1 << u32Vector);
663
664 if (enable)
665 mask &= ~u32Vector;
666 else
667 mask |= u32Vector;
668
669 _IRQ_Write4Byte(reg, mask);
670 __mhal_interrupt_restore(old);
671
672 }
673 }
674
675 //-------------------------------------------------------------------------------------------------
676 // Global Functions
677 //-------------------------------------------------------------------------------------------------
HAL_IRQ_Set_IOMap(MS_U32 u32Base)678 void HAL_IRQ_Set_IOMap(MS_U32 u32Base)
679 {
680 _u32MIO_MapBase = u32Base;
681 }
682
683 #if defined(MSOS_TYPE_NUTTX)
_HAL_IRQ_FIQHnd_Nuttx(int irq,void * context)684 int _HAL_IRQ_FIQHnd_Nuttx(int irq, void *context)
685 {
686 _HAL_IRQ_FIQHnd((MHAL_SavedRegisters *)context, irq);
687 return 1;
688 }
689
_HAL_IRQ_IRQHnd_Nuttx(int irq,void * context)690 int _HAL_IRQ_IRQHnd_Nuttx(int irq, void *context)
691 {
692 _HAL_IRQ_IRQHnd((MHAL_SavedRegisters *)context, irq);
693 return 1;
694 }
695 #endif
696
HAL_IRQ_Init(void)697 void HAL_IRQ_Init(void)
698 {
699 HAL_InitIrqTable();
700 #if defined(MCU_ARM_CA12)
701 MsOS_CPU_AttachInterrupt(E_INTERRUPT_FIQ, _HAL_IRQ_FIQHnd_ARM, E_INTERRUPT_FIQ);
702 MsOS_CPU_AttachInterrupt(E_INTERRUPT_IRQ, _HAL_IRQ_IRQHnd_ARM, E_INTERRUPT_IRQ);
703 #else
704 #if defined(MSOS_TYPE_NUTTX)
705 MsOS_CPU_AttachInterrupt(E_INTERRUPT_FIQ, _HAL_IRQ_FIQHnd_Nuttx, E_INTERRUPT_FIQ);
706 MsOS_CPU_AttachInterrupt(E_INTERRUPT_IRQ, _HAL_IRQ_IRQHnd_Nuttx, E_INTERRUPT_IRQ);
707 MsOS_CPU_UnMaskInterrupt(E_INTERRUPT_FIQ);
708 MsOS_CPU_UnMaskInterrupt(E_INTERRUPT_IRQ);
709 #else
710 MsOS_CPU_AttachInterrupt(E_INTERRUPT_FIQ, (mhal_isr_t) _HAL_IRQ_FIQHnd, E_INTERRUPT_FIQ);
711 MsOS_CPU_AttachInterrupt(E_INTERRUPT_IRQ, (mhal_isr_t) _HAL_IRQ_IRQHnd, E_INTERRUPT_IRQ);
712 #endif
713 #endif
714 HAL_IRQ_DetechAll();
715 }
716
HAL_IRQ_Attach(MS_U32 u32Vector,void * pIntCb)717 void HAL_IRQ_Attach(MS_U32 u32Vector, void *pIntCb)
718 {
719 MS_U32 u32VectorIndex = 0;
720
721 u32VectorIndex = (MS_U32)IntEnum2HWIdx[u32Vector];
722
723 if ((MS_U32)u32VectorIndex <= COUNTOF(irq_table))
724 irq_table[u32VectorIndex] = (IRQCb)pIntCb;
725 else
726 printf("%s error vector: %x\n", __FUNCTION__, (unsigned int)u32VectorIndex);
727 }
728
HAL_IRQ_DetechAll()729 void HAL_IRQ_DetechAll()
730 {
731 MS_U16 u16Cnt= 0;
732 for (; u16Cnt <= COUNTOF(irq_table); u16Cnt++)
733 irq_table[u16Cnt] = 0;
734 }
735
HAL_IRQ_Detech(MS_U32 u32Vector)736 void HAL_IRQ_Detech(MS_U32 u32Vector)
737 {
738 MS_U32 u32VectorIndex = 0;
739
740 u32VectorIndex = (MS_U32)IntEnum2HWIdx[u32Vector];
741
742 if ((MS_U32)u32VectorIndex <= COUNTOF(irq_table))
743 irq_table[u32VectorIndex] = 0;
744 else
745 printf("%s error vector: %x\n", __FUNCTION__, (unsigned int)u32Vector);
746 }
747
HAL_IRQ_MaskAll(MS_BOOL bMask)748 void HAL_IRQ_MaskAll(MS_BOOL bMask)
749 {
750 if (bMask)
751 {
752 _u32FIQ_Msk = _IRQ_Read4Byte(REG_C_FIQ_MASK);
753 _u32IRQ_Msk = _IRQ_Read4Byte(REG_C_IRQ_MASK);
754 _u32FIQExp_Msk = _IRQ_Read4Byte(REG_C_FIQ_EXP_MASK);
755 _u32IRQExp_Msk = _IRQ_Read4Byte(REG_C_IRQ_EXP_MASK);
756 _IRQ_Write4Byte(REG_C_FIQ_MASK, 0xFFFFFFFF);
757 _IRQ_Write4Byte(REG_C_IRQ_MASK, 0xFFFFFFFF);
758 _IRQ_Write4Byte(REG_C_FIQ_EXP_MASK, 0xFFFFFFFF);
759 _IRQ_Write4Byte(REG_C_IRQ_EXP_MASK, 0xFFFFFFFF);
760 }
761 else
762 {
763 _IRQ_Write4Byte(REG_C_FIQ_MASK, 0);
764 _IRQ_Write4Byte(REG_C_IRQ_MASK, 0);
765 _IRQ_Write4Byte(REG_C_FIQ_EXP_MASK, 0);
766 _IRQ_Write4Byte(REG_C_IRQ_EXP_MASK, 0);
767 }
768 }
769
HAL_IRQ_Restore()770 void HAL_IRQ_Restore()
771 {
772 _IRQ_Write4Byte(REG_C_FIQ_MASK, _u32FIQ_Msk);
773 _IRQ_Write4Byte(REG_C_IRQ_MASK, _u32IRQ_Msk);
774 _IRQ_Write4Byte(REG_C_FIQ_EXP_MASK, _u32FIQExp_Msk);
775 _IRQ_Write4Byte(REG_C_IRQ_EXP_MASK, _u32IRQExp_Msk);
776 }
777
HAL_IRQ_Mask(MS_U32 u32Vector)778 void HAL_IRQ_Mask(MS_U32 u32Vector)
779 {
780 MS_U32 u32VectorIndex = 0;
781
782 u32VectorIndex = (MS_U32)IntEnum2HWIdx[u32Vector];
783 _HAL_IRQ_Enable(u32VectorIndex, DISABLE);
784 }
785
HAL_IRQ_UnMask(MS_U32 u32Vector)786 void HAL_IRQ_UnMask(MS_U32 u32Vector)
787 {
788 MS_U32 u32VectorIndex = 0;
789
790 u32VectorIndex = (MS_U32)IntEnum2HWIdx[u32Vector];
791 _HAL_IRQ_Enable(u32VectorIndex, ENABLE);
792 }
793
HAL_IRQ_NotifyCpu(IRQ_CPU_TYPE type)794 void HAL_IRQ_NotifyCpu(IRQ_CPU_TYPE type)
795 {
796 type = type;
797 printf("[%s][%d] has not implemented yet\n", __FUNCTION__, __LINE__);
798 #if 0
799 switch (type)
800 {
801 case E_IRQ_CPU0_2_CPU1:
802 _IRQ_WriteByte(REG_SEND_IRQ_FROM_CPU0, BIT(0));
803 _IRQ_WriteByte(REG_SEND_IRQ_FROM_CPU0, 0);
804 break;
805 case E_IRQ_CPU0_2_CPU2:
806 _IRQ_WriteByte(REG_SEND_IRQ_FROM_CPU0, BIT(1));
807 _IRQ_WriteByte(REG_SEND_IRQ_FROM_CPU0, 0);
808 break;
809 case E_IRQ_CPU1_2_CPU0:
810 _IRQ_WriteByte(REG_SEND_IRQ_FROM_CPU1, BIT(0));
811 _IRQ_WriteByte(REG_SEND_IRQ_FROM_CPU1, 0);
812 break;
813 case E_IRQ_CPU1_2_CPU2:
814 _IRQ_WriteByte(REG_SEND_IRQ_FROM_CPU1, BIT(1));
815 _IRQ_WriteByte(REG_SEND_IRQ_FROM_CPU1, 0);
816 break;
817 case E_IRQ_CPU2_2_CPU0:
818 _IRQ_WriteByte(REG_SEND_IRQ_FROM_CPU2, BIT(0));
819 _IRQ_WriteByte(REG_SEND_IRQ_FROM_CPU2, 0);
820 break;
821 case E_IRQ_CPU2_2_CPU1:
822 _IRQ_WriteByte(REG_SEND_IRQ_FROM_CPU2, BIT(1));
823 _IRQ_WriteByte(REG_SEND_IRQ_FROM_CPU2, 0);
824 break;
825 default:
826 break;
827 }
828 #endif
829 }
830
HAL_IRQ_InISR()831 MS_BOOL HAL_IRQ_InISR()
832 {
833 return (_bInIRQ || _bInFIQ);
834 }
835
836 #endif // #if defined (MSOS_TYPE_NOS)
837