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Searched refs:REG_INT_BASE_ADDR (Results 1 – 8 of 8) sorted by relevance

/utopia/UTPA2-700.0.x/mxlib/hal/curry/
H A DregCHIP.h139 #define REG_INT_BASE_ADDR 0x0040 macro
142 #define REG_FIQ_MASK_L (REG_INT_BASE_ADDR + 0x0004)
143 #define REG_FIQ_MASK_H (REG_INT_BASE_ADDR + 0x0005)
144 #define REG_FIQEXP_MASK_L (REG_INT_BASE_ADDR + 0x0006)
145 #define REG_FIQEXP_MASK_H (REG_INT_BASE_ADDR + 0x0007)
147 #define REG_FIQHYP_MASK_L (REG_INT_BASE_ADDR + 0x0004)
148 #define REG_FIQHYP_MASK_H (REG_INT_BASE_ADDR + 0x0005)
149 #define REG_FIQSUP_MASK_L (REG_INT_BASE_ADDR + 0x0006)
150 #define REG_FIQSUP_MASK_H (REG_INT_BASE_ADDR + 0x0007)
152 #define REG_FIQ_CLEAR_L (REG_INT_BASE_ADDR + 0x000c)
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/utopia/UTPA2-700.0.x/mxlib/hal/k7u/
H A DregCHIP.h139 #define REG_INT_BASE_ADDR 0x0040 macro
142 #define REG_FIQ_MASK_L (REG_INT_BASE_ADDR + 0x0004)
143 #define REG_FIQ_MASK_H (REG_INT_BASE_ADDR + 0x0005)
144 #define REG_FIQEXP_MASK_L (REG_INT_BASE_ADDR + 0x0006)
145 #define REG_FIQEXP_MASK_H (REG_INT_BASE_ADDR + 0x0007)
147 #define REG_FIQHYP_MASK_L (REG_INT_BASE_ADDR + 0x0004)
148 #define REG_FIQHYP_MASK_H (REG_INT_BASE_ADDR + 0x0005)
149 #define REG_FIQSUP_MASK_L (REG_INT_BASE_ADDR + 0x0006)
150 #define REG_FIQSUP_MASK_H (REG_INT_BASE_ADDR + 0x0007)
152 #define REG_FIQ_CLEAR_L (REG_INT_BASE_ADDR + 0x000c)
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/utopia/UTPA2-700.0.x/mxlib/hal/k6lite/
H A DregCHIP.h139 #define REG_INT_BASE_ADDR 0x0040 macro
142 #define REG_FIQ_MASK_L (REG_INT_BASE_ADDR + 0x0004)
143 #define REG_FIQ_MASK_H (REG_INT_BASE_ADDR + 0x0005)
144 #define REG_FIQEXP_MASK_L (REG_INT_BASE_ADDR + 0x0006)
145 #define REG_FIQEXP_MASK_H (REG_INT_BASE_ADDR + 0x0007)
147 #define REG_FIQHYP_MASK_L (REG_INT_BASE_ADDR + 0x0004)
148 #define REG_FIQHYP_MASK_H (REG_INT_BASE_ADDR + 0x0005)
149 #define REG_FIQSUP_MASK_L (REG_INT_BASE_ADDR + 0x0006)
150 #define REG_FIQSUP_MASK_H (REG_INT_BASE_ADDR + 0x0007)
152 #define REG_FIQ_CLEAR_L (REG_INT_BASE_ADDR + 0x000c)
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/utopia/UTPA2-700.0.x/mxlib/hal/k6/
H A DregCHIP.h139 #define REG_INT_BASE_ADDR 0x0040 macro
142 #define REG_FIQ_MASK_L (REG_INT_BASE_ADDR + 0x0004)
143 #define REG_FIQ_MASK_H (REG_INT_BASE_ADDR + 0x0005)
144 #define REG_FIQEXP_MASK_L (REG_INT_BASE_ADDR + 0x0006)
145 #define REG_FIQEXP_MASK_H (REG_INT_BASE_ADDR + 0x0007)
147 #define REG_FIQHYP_MASK_L (REG_INT_BASE_ADDR + 0x0004)
148 #define REG_FIQHYP_MASK_H (REG_INT_BASE_ADDR + 0x0005)
149 #define REG_FIQSUP_MASK_L (REG_INT_BASE_ADDR + 0x0006)
150 #define REG_FIQSUP_MASK_H (REG_INT_BASE_ADDR + 0x0007)
152 #define REG_FIQ_CLEAR_L (REG_INT_BASE_ADDR + 0x000c)
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/utopia/UTPA2-700.0.x/mxlib/hal/kano/
H A DregCHIP.h139 #define REG_INT_BASE_ADDR 0x0040 macro
142 #define REG_FIQ_MASK_L (REG_INT_BASE_ADDR + 0x0004)
143 #define REG_FIQ_MASK_H (REG_INT_BASE_ADDR + 0x0005)
144 #define REG_FIQEXP_MASK_L (REG_INT_BASE_ADDR + 0x0006)
145 #define REG_FIQEXP_MASK_H (REG_INT_BASE_ADDR + 0x0007)
147 #define REG_FIQHYP_MASK_L (REG_INT_BASE_ADDR + 0x0004)
148 #define REG_FIQHYP_MASK_H (REG_INT_BASE_ADDR + 0x0005)
149 #define REG_FIQSUP_MASK_L (REG_INT_BASE_ADDR + 0x0006)
150 #define REG_FIQSUP_MASK_H (REG_INT_BASE_ADDR + 0x0007)
152 #define REG_FIQ_CLEAR_L (REG_INT_BASE_ADDR + 0x000c)
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/utopia/UTPA2-700.0.x/mxlib/hal/mustang/
H A DregCHIP.h114 #define REG_INT_BASE_ADDR 0x0020 macro
117 #define REG_INT_BASE_ADDR 0x0040 macro
120 #define REG_FIQ_MASK_L (REG_INT_BASE_ADDR + 0x0004)
121 #define REG_FIQ_MASK_H (REG_INT_BASE_ADDR + 0x0005)
122 #define REG_FIQEXP_MASK_L (REG_INT_BASE_ADDR + 0x0006)
123 #define REG_FIQEXP_MASK_H (REG_INT_BASE_ADDR + 0x0007)
125 #define REG_FIQ_CLEAR_L (REG_INT_BASE_ADDR + 0x000c)
126 #define REG_FIQ_CLEAR_H (REG_INT_BASE_ADDR + 0x000d)
127 #define REG_FIQEXP_CLEAR_L (REG_INT_BASE_ADDR + 0x000e)
128 #define REG_FIQEXP_CLEAR_H (REG_INT_BASE_ADDR + 0x000f)
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/utopia/UTPA2-700.0.x/mxlib/hal/messi/
H A DregCHIP.h114 #define REG_INT_BASE_ADDR 0x0060 macro
117 #define REG_INT_BASE_ADDR 0x0020 macro
120 #define REG_FIQ_MASK_L (REG_INT_BASE_ADDR + 0x0004)
121 #define REG_FIQ_MASK_H (REG_INT_BASE_ADDR + 0x0005)
122 #define REG_FIQEXP_MASK_L (REG_INT_BASE_ADDR + 0x0006)
123 #define REG_FIQEXP_MASK_H (REG_INT_BASE_ADDR + 0x0007)
125 #define REG_FIQ_CLEAR_L (REG_INT_BASE_ADDR + 0x000c)
126 #define REG_FIQ_CLEAR_H (REG_INT_BASE_ADDR + 0x000d)
127 #define REG_FIQEXP_CLEAR_L (REG_INT_BASE_ADDR + 0x000e)
128 #define REG_FIQEXP_CLEAR_H (REG_INT_BASE_ADDR + 0x000f)
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/utopia/UTPA2-700.0.x/mxlib/hal/mainz/
H A DregCHIP.h114 #define REG_INT_BASE_ADDR 0x0060 macro
117 #define REG_INT_BASE_ADDR 0x0020 macro
120 #define REG_FIQ_MASK_L (REG_INT_BASE_ADDR + 0x0004)
121 #define REG_FIQ_MASK_H (REG_INT_BASE_ADDR + 0x0005)
122 #define REG_FIQEXP_MASK_L (REG_INT_BASE_ADDR + 0x0006)
123 #define REG_FIQEXP_MASK_H (REG_INT_BASE_ADDR + 0x0007)
125 #define REG_FIQ_CLEAR_L (REG_INT_BASE_ADDR + 0x000c)
126 #define REG_FIQ_CLEAR_H (REG_INT_BASE_ADDR + 0x000d)
127 #define REG_FIQEXP_CLEAR_L (REG_INT_BASE_ADDR + 0x000e)
128 #define REG_FIQEXP_CLEAR_H (REG_INT_BASE_ADDR + 0x000f)
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