Lines Matching refs:REG_INT_BASE_ADDR
114 #define REG_INT_BASE_ADDR 0x0060 macro
117 #define REG_INT_BASE_ADDR 0x0020 macro
120 #define REG_FIQ_MASK_L (REG_INT_BASE_ADDR + 0x0004)
121 #define REG_FIQ_MASK_H (REG_INT_BASE_ADDR + 0x0005)
122 #define REG_FIQEXP_MASK_L (REG_INT_BASE_ADDR + 0x0006)
123 #define REG_FIQEXP_MASK_H (REG_INT_BASE_ADDR + 0x0007)
125 #define REG_FIQ_CLEAR_L (REG_INT_BASE_ADDR + 0x000c)
126 #define REG_FIQ_CLEAR_H (REG_INT_BASE_ADDR + 0x000d)
127 #define REG_FIQEXP_CLEAR_L (REG_INT_BASE_ADDR + 0x000e)
128 #define REG_FIQEXP_CLEAR_H (REG_INT_BASE_ADDR + 0x000f)
130 #define REG_FIQ_PENDING_L (REG_INT_BASE_ADDR + 0x000c)
131 #define REG_FIQ_PENDING_H (REG_INT_BASE_ADDR + 0x000d)
132 #define REG_FIQEXP_PENDING_L (REG_INT_BASE_ADDR + 0x000e)
133 #define REG_FIQEXP_PENDING_H (REG_INT_BASE_ADDR + 0x000f)
135 #define REG_IRQ_MASK_L (REG_INT_BASE_ADDR + 0x0014)
136 #define REG_IRQ_MASK_H (REG_INT_BASE_ADDR + 0x0015)
137 #define REG_IRQEXP_MASK_L (REG_INT_BASE_ADDR + 0x0016)
138 #define REG_IRQEXP_MASK_H (REG_INT_BASE_ADDR + 0x0017)
140 #define REG_IRQ_PENDING_L (REG_INT_BASE_ADDR + 0x001c)
141 #define REG_IRQ_PENDING_H (REG_INT_BASE_ADDR + 0x001d)
142 #define REG_IRQEXP_PENDING_L (REG_INT_BASE_ADDR + 0x001e)
143 #define REG_IRQEXP_PENDING_H (REG_INT_BASE_ADDR + 0x001f)