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Searched refs:REG_HDMITX_PHY_2E_L (Results 1 – 18 of 18) sorted by relevance

/utopia/UTPA2-700.0.x/modules/hdmi/hal/curry/hdcp/
H A DhalHDCP.c591 …MHalHdcpRegMaskWrite(DEF_HDMITX_PHY_REG_BANK, REG_HDMITX_PHY_2E_L, 0xE800, u32SetStatus? 0xE800: 0… in MHal_HDCP_HDCPTxHDMIStatus()
595 if((MHalHdcpRegRead(DEF_HDMITX_PHY_REG_BANK, REG_HDMITX_PHY_2E_L) &0xE800) == 0xE800) in MHal_HDCP_HDCPTxHDMIStatus()
H A DregHDCP.h294 #define REG_HDMITX_PHY_2E_L 0x2EU macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/k6/hdcp/
H A DhalHDCP.c575 …MHalHdcpRegMaskWrite(DEF_HDMITX_PHY_REG_BANK, REG_HDMITX_PHY_2E_L, 0xE800, u32SetStatus? 0xE800: 0… in MHal_HDCP_HDCPTxHDMIStatus()
579 if((MHalHdcpRegRead(DEF_HDMITX_PHY_REG_BANK, REG_HDMITX_PHY_2E_L) &0xE800) == 0xE800) in MHal_HDCP_HDCPTxHDMIStatus()
H A DregHDCP.h292 #define REG_HDMITX_PHY_2E_L 0x2EU macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/k6lite/hdcp/
H A DhalHDCP.c624 …MHalHdcpRegMaskWrite(DEF_HDMITX_PHY_REG_BANK, REG_HDMITX_PHY_2E_L, 0xE800, u32SetStatus? 0xE800: 0… in MHal_HDCP_HDCPTxHDMIStatus()
628 if((MHalHdcpRegRead(DEF_HDMITX_PHY_REG_BANK, REG_HDMITX_PHY_2E_L) &0xE800) == 0xE800) in MHal_HDCP_HDCPTxHDMIStatus()
H A DregHDCP.h294 #define REG_HDMITX_PHY_2E_L 0x2EU macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7621/hdcp/
H A DhalHDCP.c626 …MHalHdcpRegMaskWrite(DEF_HDMITX_PHY_REG_BANK, REG_HDMITX_PHY_2E_L, 0xE800, u32SetStatus? 0xE800: 0… in MHal_HDCP_HDCPTxHDMIStatus()
630 if((MHalHdcpRegRead(DEF_HDMITX_PHY_REG_BANK, REG_HDMITX_PHY_2E_L) &0xE800) == 0xE800) in MHal_HDCP_HDCPTxHDMIStatus()
H A DregHDCP.h294 #define REG_HDMITX_PHY_2E_L 0x2EU macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maxim/hdcp/
H A DhalHDCP.c688 …MHalHdcpRegMaskWrite(DEF_HDMITX_PHY_REG_BANK, REG_HDMITX_PHY_2E_L, 0xE800, u32SetStatus? 0xE800: 0… in MHal_HDCP_HDCPTxHDMIStatus()
692 if((MHalHdcpRegRead(DEF_HDMITX_PHY_REG_BANK, REG_HDMITX_PHY_2E_L) &0xE800) == 0xE800) in MHal_HDCP_HDCPTxHDMIStatus()
H A DregHDCP.h294 #define REG_HDMITX_PHY_2E_L 0x2EU macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/kano/hdcp/
H A DhalHDCP.c695 …MHalHdcpRegMaskWrite(DEF_HDMITX_PHY_REG_BANK, REG_HDMITX_PHY_2E_L, 0xE800, u32SetStatus? 0xE800: 0… in MHal_HDCP_HDCPTxHDMIStatus()
699 if((MHalHdcpRegRead(DEF_HDMITX_PHY_REG_BANK, REG_HDMITX_PHY_2E_L) &0xE800) == 0xE800) in MHal_HDCP_HDCPTxHDMIStatus()
H A DregHDCP.h294 #define REG_HDMITX_PHY_2E_L 0x2EU macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mooney/hdcp/
H A DregHDCP.h292 #define REG_HDMITX_PHY_2E_L 0x2EU macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mainz/hdcp/
H A DregHDCP.h294 #define REG_HDMITX_PHY_2E_L 0x2EU macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7821/hdcp/
H A DregHDCP.h294 #define REG_HDMITX_PHY_2E_L 0x2EU macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/manhattan/hdcp/
H A DregHDCP.h294 #define REG_HDMITX_PHY_2E_L 0x2EU macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/messi/hdcp/
H A DregHDCP.h294 #define REG_HDMITX_PHY_2E_L 0x2EU macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maserati/hdcp/
H A DregHDCP.h294 #define REG_HDMITX_PHY_2E_L 0x2EU macro