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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 //////////////////////////////////////////////////////////////////////////////////////////////////// 96 // 97 // File name: regAESDMA.h 98 // Description: AESDMA Register Definition 99 // 100 //////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _HDCP_REG_MCU_H_ 103 #define _HDCP_REG_MCU_H_ 104 105 #define DEF_HDCP14_TX_KEY_REG_BANK 0x000000U 106 #define DEF_HDCP22_TX_KEY_REG_BANK 0x072700U // 0x172700U 107 #define DEF_HDCP14_TX_REG_BANK 0x072B00U // 0x172B00U 108 #define DEF_HDCP22_TX_REG_BANK 0x072F00U // 0x172F00U 109 #define DEF_HDMITX_PHY_REG_BANK 0x073000U // 0x173000U 110 111 #define DEF_HDCP14_RX_KEY_REG_BANK 0x000000U 112 #define DEF_HDCP22_RX_KEY_REG_BANK 0x073A00U // 0x173A00U 113 #define DEF_HDCP14_RX_REG_BANK 0x071200U // 0x171200U 114 #define DEF_HDCP22_RX_REG_BANK 0x071200U // 0x171200U 115 116 #define REG_HDCP14_TX_00_L 0x00U 117 #define REG_HDCP14_TX_01_L 0x01U 118 #define REG_HDCP14_TX_02_L 0x02U 119 #define REG_HDCP14_TX_03_L 0x03U 120 #define REG_HDCP14_TX_04_L 0x04U 121 #define REG_HDCP14_TX_05_L 0x05U 122 #define REG_HDCP14_TX_06_L 0x06U 123 #define REG_HDCP14_TX_07_L 0x07U 124 #define REG_HDCP14_TX_08_L 0x08U 125 #define REG_HDCP14_TX_09_L 0x09U 126 #define REG_HDCP14_TX_0A_L 0x0AU 127 #define REG_HDCP14_TX_0B_L 0x0BU 128 #define REG_HDCP14_TX_0C_L 0x0CU 129 #define REG_HDCP14_TX_0D_L 0x0DU 130 #define REG_HDCP14_TX_0E_L 0x0EU 131 #define REG_HDCP14_TX_0F_L 0x0FU 132 #define REG_HDCP14_TX_10_L 0x10U 133 #define REG_HDCP14_TX_11_L 0x11U 134 #define REG_HDCP14_TX_12_L 0x12U 135 #define REG_HDCP14_TX_13_L 0x13U 136 #define REG_HDCP14_TX_14_L 0x14U 137 #define REG_HDCP14_TX_15_L 0x15U 138 #define REG_HDCP14_TX_16_L 0x16U 139 #define REG_HDCP14_TX_17_L 0x17U 140 #define REG_HDCP14_TX_18_L 0x18U 141 #define REG_HDCP14_TX_19_L 0x19U 142 #define REG_HDCP14_TX_1A_L 0x1AU 143 #define REG_HDCP14_TX_1B_L 0x1BU 144 #define REG_HDCP14_TX_1C_L 0x1CU 145 #define REG_HDCP14_TX_1D_L 0x1DU 146 #define REG_HDCP14_TX_1E_L 0x1EU 147 #define REG_HDCP14_TX_1F_L 0x1FU 148 #define REG_HDCP14_TX_20_L 0x20U 149 #define REG_HDCP14_TX_21_L 0x21U 150 #define REG_HDCP14_TX_22_L 0x22U 151 #define REG_HDCP14_TX_23_L 0x23U 152 #define REG_HDCP14_TX_24_L 0x24U 153 #define REG_HDCP14_TX_25_L 0x25U 154 #define REG_HDCP14_TX_26_L 0x26U 155 #define REG_HDCP14_TX_27_L 0x27U 156 #define REG_HDCP14_TX_28_L 0x28U 157 #define REG_HDCP14_TX_29_L 0x29U 158 #define REG_HDCP14_TX_2A_L 0x2AU 159 #define REG_HDCP14_TX_2B_L 0x2BU 160 #define REG_HDCP14_TX_2C_L 0x2CU 161 #define REG_HDCP14_TX_2D_L 0x2DU 162 #define REG_HDCP14_TX_2E_L 0x2EU 163 #define REG_HDCP14_TX_2F_L 0x2FU 164 #define REG_HDCP14_TX_30_L 0x30U 165 #define REG_HDCP14_TX_31_L 0x31U 166 #define REG_HDCP14_TX_32_L 0x32U 167 #define REG_HDCP14_TX_33_L 0x33U 168 #define REG_HDCP14_TX_34_L 0x34U 169 #define REG_HDCP14_TX_35_L 0x35U 170 #define REG_HDCP14_TX_36_L 0x36U 171 #define REG_HDCP14_TX_37_L 0x37U 172 #define REG_HDCP14_TX_38_L 0x38U 173 #define REG_HDCP14_TX_39_L 0x39U 174 #define REG_HDCP14_TX_3A_L 0x3AU 175 #define REG_HDCP14_TX_3B_L 0x3BU 176 #define REG_HDCP14_TX_3C_L 0x3CU 177 #define REG_HDCP14_TX_3D_L 0x3DU 178 #define REG_HDCP14_TX_3E_L 0x3EU 179 #define REG_HDCP14_TX_3F_L 0x3FU 180 181 #define REG_HDCP22_TX_00_L 0x00U 182 #define REG_HDCP22_TX_01_L 0x01U 183 #define REG_HDCP22_TX_02_L 0x02U 184 #define REG_HDCP22_TX_03_L 0x03U 185 #define REG_HDCP22_TX_04_L 0x04U 186 #define REG_HDCP22_TX_05_L 0x05U 187 #define REG_HDCP22_TX_06_L 0x06U 188 #define REG_HDCP22_TX_07_L 0x07U 189 #define REG_HDCP22_TX_08_L 0x08U 190 #define REG_HDCP22_TX_09_L 0x09U 191 #define REG_HDCP22_TX_0A_L 0x0AU 192 #define REG_HDCP22_TX_0B_L 0x0BU 193 #define REG_HDCP22_TX_0C_L 0x0CU 194 #define REG_HDCP22_TX_0D_L 0x0DU 195 #define REG_HDCP22_TX_0E_L 0x0EU 196 #define REG_HDCP22_TX_0F_L 0x0FU 197 #define REG_HDCP22_TX_10_L 0x10U 198 #define REG_HDCP22_TX_11_L 0x11U 199 #define REG_HDCP22_TX_12_L 0x12U 200 #define REG_HDCP22_TX_13_L 0x13U 201 #define REG_HDCP22_TX_14_L 0x14U 202 #define REG_HDCP22_TX_15_L 0x15U 203 #define REG_HDCP22_TX_16_L 0x16U 204 #define REG_HDCP22_TX_17_L 0x17U 205 #define REG_HDCP22_TX_18_L 0x18U 206 #define REG_HDCP22_TX_19_L 0x19U 207 #define REG_HDCP22_TX_1A_L 0x1AU 208 #define REG_HDCP22_TX_1B_L 0x1BU 209 #define REG_HDCP22_TX_1C_L 0x1CU 210 #define REG_HDCP22_TX_1D_L 0x1DU 211 #define REG_HDCP22_TX_1E_L 0x1EU 212 #define REG_HDCP22_TX_1F_L 0x1FU 213 #define REG_HDCP22_TX_20_L 0x20U 214 #define REG_HDCP22_TX_21_L 0x21U 215 #define REG_HDCP22_TX_22_L 0x22U 216 #define REG_HDCP22_TX_23_L 0x23U 217 #define REG_HDCP22_TX_24_L 0x24U 218 #define REG_HDCP22_TX_25_L 0x25U 219 #define REG_HDCP22_TX_26_L 0x26U 220 #define REG_HDCP22_TX_27_L 0x27U 221 #define REG_HDCP22_TX_28_L 0x28U 222 #define REG_HDCP22_TX_29_L 0x29U 223 #define REG_HDCP22_TX_2A_L 0x2AU 224 #define REG_HDCP22_TX_2B_L 0x2BU 225 #define REG_HDCP22_TX_2C_L 0x2CU 226 #define REG_HDCP22_TX_2D_L 0x2DU 227 #define REG_HDCP22_TX_2E_L 0x2EU 228 #define REG_HDCP22_TX_2F_L 0x2FU 229 #define REG_HDCP22_TX_30_L 0x30U 230 #define REG_HDCP22_TX_31_L 0x31U 231 #define REG_HDCP22_TX_32_L 0x32U 232 #define REG_HDCP22_TX_33_L 0x33U 233 #define REG_HDCP22_TX_34_L 0x34U 234 #define REG_HDCP22_TX_35_L 0x35U 235 #define REG_HDCP22_TX_36_L 0x36U 236 #define REG_HDCP22_TX_37_L 0x37U 237 #define REG_HDCP22_TX_38_L 0x38U 238 #define REG_HDCP22_TX_39_L 0x39U 239 #define REG_HDCP22_TX_3A_L 0x3AU 240 #define REG_HDCP22_TX_3B_L 0x3BU 241 #define REG_HDCP22_TX_3C_L 0x3CU 242 #define REG_HDCP22_TX_3D_L 0x3DU 243 #define REG_HDCP22_TX_3E_L 0x3EU 244 #define REG_HDCP22_TX_3F_L 0x3FU 245 246 #define REG_HDMITX_PHY_00_L 0x00U 247 #define REG_HDMITX_PHY_01_L 0x01U 248 #define REG_HDMITX_PHY_02_L 0x02U 249 #define REG_HDMITX_PHY_03_L 0x03U 250 #define REG_HDMITX_PHY_04_L 0x04U 251 #define REG_HDMITX_PHY_05_L 0x05U 252 #define REG_HDMITX_PHY_06_L 0x06U 253 #define REG_HDMITX_PHY_07_L 0x07U 254 #define REG_HDMITX_PHY_08_L 0x08U 255 #define REG_HDMITX_PHY_09_L 0x09U 256 #define REG_HDMITX_PHY_0A_L 0x0AU 257 #define REG_HDMITX_PHY_0B_L 0x0BU 258 #define REG_HDMITX_PHY_0C_L 0x0CU 259 #define REG_HDMITX_PHY_0D_L 0x0DU 260 #define REG_HDMITX_PHY_0E_L 0x0EU 261 #define REG_HDMITX_PHY_0F_L 0x0FU 262 #define REG_HDMITX_PHY_10_L 0x10U 263 #define REG_HDMITX_PHY_11_L 0x11U 264 #define REG_HDMITX_PHY_12_L 0x12U 265 #define REG_HDMITX_PHY_13_L 0x13U 266 #define REG_HDMITX_PHY_14_L 0x14U 267 #define REG_HDMITX_PHY_15_L 0x15U 268 #define REG_HDMITX_PHY_16_L 0x16U 269 #define REG_HDMITX_PHY_17_L 0x17U 270 #define REG_HDMITX_PHY_18_L 0x18U 271 #define REG_HDMITX_PHY_19_L 0x19U 272 #define REG_HDMITX_PHY_1A_L 0x1AU 273 #define REG_HDMITX_PHY_1B_L 0x1BU 274 #define REG_HDMITX_PHY_1C_L 0x1CU 275 #define REG_HDMITX_PHY_1D_L 0x1DU 276 #define REG_HDMITX_PHY_1E_L 0x1EU 277 #define REG_HDMITX_PHY_1F_L 0x1FU 278 #define REG_HDMITX_PHY_20_L 0x20U 279 #define REG_HDMITX_PHY_21_L 0x21U 280 #define REG_HDMITX_PHY_22_L 0x22U 281 #define REG_HDMITX_PHY_23_L 0x23U 282 #define REG_HDMITX_PHY_24_L 0x24U 283 #define REG_HDMITX_PHY_25_L 0x25U 284 #define REG_HDMITX_PHY_26_L 0x26U 285 #define REG_HDMITX_PHY_27_L 0x27U 286 #define REG_HDMITX_PHY_28_L 0x28U 287 #define REG_HDMITX_PHY_29_L 0x29U 288 #define REG_HDMITX_PHY_2A_L 0x2AU 289 #define REG_HDMITX_PHY_2B_L 0x2BU 290 #define REG_HDMITX_PHY_2C_L 0x2CU 291 #define REG_HDMITX_PHY_2D_L 0x2DU 292 #define REG_HDMITX_PHY_2E_L 0x2EU 293 #define REG_HDMITX_PHY_2F_L 0x2FU 294 #define REG_HDMITX_PHY_30_L 0x30U 295 #define REG_HDMITX_PHY_31_L 0x31U 296 #define REG_HDMITX_PHY_32_L 0x32U 297 #define REG_HDMITX_PHY_33_L 0x33U 298 #define REG_HDMITX_PHY_34_L 0x34U 299 #define REG_HDMITX_PHY_35_L 0x35U 300 #define REG_HDMITX_PHY_36_L 0x36U 301 #define REG_HDMITX_PHY_37_L 0x37U 302 #define REG_HDMITX_PHY_38_L 0x38U 303 #define REG_HDMITX_PHY_39_L 0x39U 304 #define REG_HDMITX_PHY_3A_L 0x3AU 305 #define REG_HDMITX_PHY_3B_L 0x3BU 306 #define REG_HDMITX_PHY_3C_L 0x3CU 307 #define REG_HDMITX_PHY_3D_L 0x3DU 308 #define REG_HDMITX_PHY_3E_L 0x3EU 309 #define REG_HDMITX_PHY_3F_L 0x3FU 310 311 #endif // #ifndef _HDCP_REG_MCU_H_ 312