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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 //////////////////////////////////////////////////////////////////////////////////////////////////// 96 // 97 // File name: regAESDMA.h 98 // Description: AESDMA Register Definition 99 // 100 //////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _HDCP_REG_MCU_H_ 103 #define _HDCP_REG_MCU_H_ 104 105 #define DEF_HDCP14_TX_KEY_REG_BANK 0x000000U 106 #define DEF_HDCP22_TX_KEY_REG_BANK 0x073F00U // 0x173F00U 107 #define DEF_HDCP14_TX_REG_BANK 0x072B00U // 0x172B00U 108 #define DEF_HDCP22_TX_REG_BANK 0x072F00U // 0x172F00U 109 #define DEF_HDMITX_PHY_REG_BANK 0x073000U // 0x173000U 110 #define DEF_HDCPKEY_REG_BANK 0x000000U 111 #define DEF_COMBO_GP_TOP_REG_BANK 0x000000U 112 113 #define DEF_HDCP14_RX_KEY_REG_BANK 0x000000U 114 #define DEF_HDCP22_RX_KEY_REG_BANK 0x073F00U // 0x173F00U 115 #define DEF_HDCP14_RX_REG_BANK 0x072200U // 0x172200U 116 #define DEF_HDCP22_RX_REG_BANK 0x072200U // 0x172200U 117 118 #define REG_HDCP14_TX_00_L 0x00U 119 #define REG_HDCP14_TX_01_L 0x01U 120 #define REG_HDCP14_TX_02_L 0x02U 121 #define REG_HDCP14_TX_03_L 0x03U 122 #define REG_HDCP14_TX_04_L 0x04U 123 #define REG_HDCP14_TX_05_L 0x05U 124 #define REG_HDCP14_TX_06_L 0x06U 125 #define REG_HDCP14_TX_07_L 0x07U 126 #define REG_HDCP14_TX_08_L 0x08U 127 #define REG_HDCP14_TX_09_L 0x09U 128 #define REG_HDCP14_TX_0A_L 0x0AU 129 #define REG_HDCP14_TX_0B_L 0x0BU 130 #define REG_HDCP14_TX_0C_L 0x0CU 131 #define REG_HDCP14_TX_0D_L 0x0DU 132 #define REG_HDCP14_TX_0E_L 0x0EU 133 #define REG_HDCP14_TX_0F_L 0x0FU 134 #define REG_HDCP14_TX_10_L 0x10U 135 #define REG_HDCP14_TX_11_L 0x11U 136 #define REG_HDCP14_TX_12_L 0x12U 137 #define REG_HDCP14_TX_13_L 0x13U 138 #define REG_HDCP14_TX_14_L 0x14U 139 #define REG_HDCP14_TX_15_L 0x15U 140 #define REG_HDCP14_TX_16_L 0x16U 141 #define REG_HDCP14_TX_17_L 0x17U 142 #define REG_HDCP14_TX_18_L 0x18U 143 #define REG_HDCP14_TX_19_L 0x19U 144 #define REG_HDCP14_TX_1A_L 0x1AU 145 #define REG_HDCP14_TX_1B_L 0x1BU 146 #define REG_HDCP14_TX_1C_L 0x1CU 147 #define REG_HDCP14_TX_1D_L 0x1DU 148 #define REG_HDCP14_TX_1E_L 0x1EU 149 #define REG_HDCP14_TX_1F_L 0x1FU 150 #define REG_HDCP14_TX_20_L 0x20U 151 #define REG_HDCP14_TX_21_L 0x21U 152 #define REG_HDCP14_TX_22_L 0x22U 153 #define REG_HDCP14_TX_23_L 0x23U 154 #define REG_HDCP14_TX_24_L 0x24U 155 #define REG_HDCP14_TX_25_L 0x25U 156 #define REG_HDCP14_TX_26_L 0x26U 157 #define REG_HDCP14_TX_27_L 0x27U 158 #define REG_HDCP14_TX_28_L 0x28U 159 #define REG_HDCP14_TX_29_L 0x29U 160 #define REG_HDCP14_TX_2A_L 0x2AU 161 #define REG_HDCP14_TX_2B_L 0x2BU 162 #define REG_HDCP14_TX_2C_L 0x2CU 163 #define REG_HDCP14_TX_2D_L 0x2DU 164 #define REG_HDCP14_TX_2E_L 0x2EU 165 #define REG_HDCP14_TX_2F_L 0x2FU 166 #define REG_HDCP14_TX_30_L 0x30U 167 #define REG_HDCP14_TX_31_L 0x31U 168 #define REG_HDCP14_TX_32_L 0x32U 169 #define REG_HDCP14_TX_33_L 0x33U 170 #define REG_HDCP14_TX_34_L 0x34U 171 #define REG_HDCP14_TX_35_L 0x35U 172 #define REG_HDCP14_TX_36_L 0x36U 173 #define REG_HDCP14_TX_37_L 0x37U 174 #define REG_HDCP14_TX_38_L 0x38U 175 #define REG_HDCP14_TX_39_L 0x39U 176 #define REG_HDCP14_TX_3A_L 0x3AU 177 #define REG_HDCP14_TX_3B_L 0x3BU 178 #define REG_HDCP14_TX_3C_L 0x3CU 179 #define REG_HDCP14_TX_3D_L 0x3DU 180 #define REG_HDCP14_TX_3E_L 0x3EU 181 #define REG_HDCP14_TX_3F_L 0x3FU 182 183 #define REG_HDCP22_TX_00_L 0x00U 184 #define REG_HDCP22_TX_01_L 0x01U 185 #define REG_HDCP22_TX_02_L 0x02U 186 #define REG_HDCP22_TX_03_L 0x03U 187 #define REG_HDCP22_TX_04_L 0x04U 188 #define REG_HDCP22_TX_05_L 0x05U 189 #define REG_HDCP22_TX_06_L 0x06U 190 #define REG_HDCP22_TX_07_L 0x07U 191 #define REG_HDCP22_TX_08_L 0x08U 192 #define REG_HDCP22_TX_09_L 0x09U 193 #define REG_HDCP22_TX_0A_L 0x0AU 194 #define REG_HDCP22_TX_0B_L 0x0BU 195 #define REG_HDCP22_TX_0C_L 0x0CU 196 #define REG_HDCP22_TX_0D_L 0x0DU 197 #define REG_HDCP22_TX_0E_L 0x0EU 198 #define REG_HDCP22_TX_0F_L 0x0FU 199 #define REG_HDCP22_TX_10_L 0x10U 200 #define REG_HDCP22_TX_11_L 0x11U 201 #define REG_HDCP22_TX_12_L 0x12U 202 #define REG_HDCP22_TX_13_L 0x13U 203 #define REG_HDCP22_TX_14_L 0x14U 204 #define REG_HDCP22_TX_15_L 0x15U 205 #define REG_HDCP22_TX_16_L 0x16U 206 #define REG_HDCP22_TX_17_L 0x17U 207 #define REG_HDCP22_TX_18_L 0x18U 208 #define REG_HDCP22_TX_19_L 0x19U 209 #define REG_HDCP22_TX_1A_L 0x1AU 210 #define REG_HDCP22_TX_1B_L 0x1BU 211 #define REG_HDCP22_TX_1C_L 0x1CU 212 #define REG_HDCP22_TX_1D_L 0x1DU 213 #define REG_HDCP22_TX_1E_L 0x1EU 214 #define REG_HDCP22_TX_1F_L 0x1FU 215 #define REG_HDCP22_TX_20_L 0x20U 216 #define REG_HDCP22_TX_21_L 0x21U 217 #define REG_HDCP22_TX_22_L 0x22U 218 #define REG_HDCP22_TX_23_L 0x23U 219 #define REG_HDCP22_TX_24_L 0x24U 220 #define REG_HDCP22_TX_25_L 0x25U 221 #define REG_HDCP22_TX_26_L 0x26U 222 #define REG_HDCP22_TX_27_L 0x27U 223 #define REG_HDCP22_TX_28_L 0x28U 224 #define REG_HDCP22_TX_29_L 0x29U 225 #define REG_HDCP22_TX_2A_L 0x2AU 226 #define REG_HDCP22_TX_2B_L 0x2BU 227 #define REG_HDCP22_TX_2C_L 0x2CU 228 #define REG_HDCP22_TX_2D_L 0x2DU 229 #define REG_HDCP22_TX_2E_L 0x2EU 230 #define REG_HDCP22_TX_2F_L 0x2FU 231 #define REG_HDCP22_TX_30_L 0x30U 232 #define REG_HDCP22_TX_31_L 0x31U 233 #define REG_HDCP22_TX_32_L 0x32U 234 #define REG_HDCP22_TX_33_L 0x33U 235 #define REG_HDCP22_TX_34_L 0x34U 236 #define REG_HDCP22_TX_35_L 0x35U 237 #define REG_HDCP22_TX_36_L 0x36U 238 #define REG_HDCP22_TX_37_L 0x37U 239 #define REG_HDCP22_TX_38_L 0x38U 240 #define REG_HDCP22_TX_39_L 0x39U 241 #define REG_HDCP22_TX_3A_L 0x3AU 242 #define REG_HDCP22_TX_3B_L 0x3BU 243 #define REG_HDCP22_TX_3C_L 0x3CU 244 #define REG_HDCP22_TX_3D_L 0x3DU 245 #define REG_HDCP22_TX_3E_L 0x3EU 246 #define REG_HDCP22_TX_3F_L 0x3FU 247 248 #define REG_HDMITX_PHY_00_L 0x00U 249 #define REG_HDMITX_PHY_01_L 0x01U 250 #define REG_HDMITX_PHY_02_L 0x02U 251 #define REG_HDMITX_PHY_03_L 0x03U 252 #define REG_HDMITX_PHY_04_L 0x04U 253 #define REG_HDMITX_PHY_05_L 0x05U 254 #define REG_HDMITX_PHY_06_L 0x06U 255 #define REG_HDMITX_PHY_07_L 0x07U 256 #define REG_HDMITX_PHY_08_L 0x08U 257 #define REG_HDMITX_PHY_09_L 0x09U 258 #define REG_HDMITX_PHY_0A_L 0x0AU 259 #define REG_HDMITX_PHY_0B_L 0x0BU 260 #define REG_HDMITX_PHY_0C_L 0x0CU 261 #define REG_HDMITX_PHY_0D_L 0x0DU 262 #define REG_HDMITX_PHY_0E_L 0x0EU 263 #define REG_HDMITX_PHY_0F_L 0x0FU 264 #define REG_HDMITX_PHY_10_L 0x10U 265 #define REG_HDMITX_PHY_11_L 0x11U 266 #define REG_HDMITX_PHY_12_L 0x12U 267 #define REG_HDMITX_PHY_13_L 0x13U 268 #define REG_HDMITX_PHY_14_L 0x14U 269 #define REG_HDMITX_PHY_15_L 0x15U 270 #define REG_HDMITX_PHY_16_L 0x16U 271 #define REG_HDMITX_PHY_17_L 0x17U 272 #define REG_HDMITX_PHY_18_L 0x18U 273 #define REG_HDMITX_PHY_19_L 0x19U 274 #define REG_HDMITX_PHY_1A_L 0x1AU 275 #define REG_HDMITX_PHY_1B_L 0x1BU 276 #define REG_HDMITX_PHY_1C_L 0x1CU 277 #define REG_HDMITX_PHY_1D_L 0x1DU 278 #define REG_HDMITX_PHY_1E_L 0x1EU 279 #define REG_HDMITX_PHY_1F_L 0x1FU 280 #define REG_HDMITX_PHY_20_L 0x20U 281 #define REG_HDMITX_PHY_21_L 0x21U 282 #define REG_HDMITX_PHY_22_L 0x22U 283 #define REG_HDMITX_PHY_23_L 0x23U 284 #define REG_HDMITX_PHY_24_L 0x24U 285 #define REG_HDMITX_PHY_25_L 0x25U 286 #define REG_HDMITX_PHY_26_L 0x26U 287 #define REG_HDMITX_PHY_27_L 0x27U 288 #define REG_HDMITX_PHY_28_L 0x28U 289 #define REG_HDMITX_PHY_29_L 0x29U 290 #define REG_HDMITX_PHY_2A_L 0x2AU 291 #define REG_HDMITX_PHY_2B_L 0x2BU 292 #define REG_HDMITX_PHY_2C_L 0x2CU 293 #define REG_HDMITX_PHY_2D_L 0x2DU 294 #define REG_HDMITX_PHY_2E_L 0x2EU 295 #define REG_HDMITX_PHY_2F_L 0x2FU 296 #define REG_HDMITX_PHY_30_L 0x30U 297 #define REG_HDMITX_PHY_31_L 0x31U 298 #define REG_HDMITX_PHY_32_L 0x32U 299 #define REG_HDMITX_PHY_33_L 0x33U 300 #define REG_HDMITX_PHY_34_L 0x34U 301 #define REG_HDMITX_PHY_35_L 0x35U 302 #define REG_HDMITX_PHY_36_L 0x36U 303 #define REG_HDMITX_PHY_37_L 0x37U 304 #define REG_HDMITX_PHY_38_L 0x38U 305 #define REG_HDMITX_PHY_39_L 0x39U 306 #define REG_HDMITX_PHY_3A_L 0x3AU 307 #define REG_HDMITX_PHY_3B_L 0x3BU 308 #define REG_HDMITX_PHY_3C_L 0x3CU 309 #define REG_HDMITX_PHY_3D_L 0x3DU 310 #define REG_HDMITX_PHY_3E_L 0x3EU 311 #define REG_HDMITX_PHY_3F_L 0x3FU 312 313 #define REG_HDCPKEY_BANK_00_L 0x00U 314 #define REG_HDCPKEY_BANK_01_L 0x01U 315 #define REG_HDCPKEY_BANK_02_L 0x02U 316 #define REG_HDCPKEY_BANK_03_L 0x03U 317 #define REG_HDCPKEY_BANK_04_L 0x04U 318 #define REG_HDCPKEY_BANK_05_L 0x05U 319 #define REG_HDCPKEY_BANK_06_L 0x06U 320 #define REG_HDCPKEY_BANK_07_L 0x07U 321 #define REG_HDCPKEY_BANK_08_L 0x08U 322 #define REG_HDCPKEY_BANK_09_L 0x09U 323 #define REG_HDCPKEY_BANK_0A_L 0x0AU 324 #define REG_HDCPKEY_BANK_0B_L 0x0BU 325 #define REG_HDCPKEY_BANK_0C_L 0x0CU 326 #define REG_HDCPKEY_BANK_0D_L 0x0DU 327 #define REG_HDCPKEY_BANK_0E_L 0x0EU 328 #define REG_HDCPKEY_BANK_0F_L 0x0FU 329 #define REG_HDCPKEY_BANK_10_L 0x10U 330 #define REG_HDCPKEY_BANK_11_L 0x11U 331 #define REG_HDCPKEY_BANK_12_L 0x12U 332 #define REG_HDCPKEY_BANK_13_L 0x13U 333 #define REG_HDCPKEY_BANK_14_L 0x14U 334 #define REG_HDCPKEY_BANK_15_L 0x15U 335 #define REG_HDCPKEY_BANK_16_L 0x16U 336 #define REG_HDCPKEY_BANK_17_L 0x17U 337 #define REG_HDCPKEY_BANK_18_L 0x18U 338 #define REG_HDCPKEY_BANK_19_L 0x19U 339 #define REG_HDCPKEY_BANK_1A_L 0x1AU 340 #define REG_HDCPKEY_BANK_1B_L 0x1BU 341 #define REG_HDCPKEY_BANK_1C_L 0x1CU 342 #define REG_HDCPKEY_BANK_1D_L 0x1DU 343 #define REG_HDCPKEY_BANK_1E_L 0x1EU 344 #define REG_HDCPKEY_BANK_1F_L 0x1FU 345 #define REG_HDCPKEY_BANK_20_L 0x20U 346 #define REG_HDCPKEY_BANK_21_L 0x21U 347 #define REG_HDCPKEY_BANK_22_L 0x22U 348 #define REG_HDCPKEY_BANK_23_L 0x23U 349 #define REG_HDCPKEY_BANK_24_L 0x24U 350 #define REG_HDCPKEY_BANK_25_L 0x25U 351 #define REG_HDCPKEY_BANK_26_L 0x26U 352 #define REG_HDCPKEY_BANK_27_L 0x27U 353 #define REG_HDCPKEY_BANK_28_L 0x28U 354 #define REG_HDCPKEY_BANK_29_L 0x29U 355 #define REG_HDCPKEY_BANK_2A_L 0x2AU 356 #define REG_HDCPKEY_BANK_2B_L 0x2BU 357 #define REG_HDCPKEY_BANK_2C_L 0x2CU 358 #define REG_HDCPKEY_BANK_2D_L 0x2DU 359 #define REG_HDCPKEY_BANK_2E_L 0x2EU 360 #define REG_HDCPKEY_BANK_2F_L 0x2FU 361 #define REG_HDCPKEY_BANK_30_L 0x30U 362 #define REG_HDCPKEY_BANK_31_L 0x31U 363 #define REG_HDCPKEY_BANK_32_L 0x32U 364 #define REG_HDCPKEY_BANK_33_L 0x33U 365 #define REG_HDCPKEY_BANK_34_L 0x34U 366 #define REG_HDCPKEY_BANK_35_L 0x35U 367 #define REG_HDCPKEY_BANK_36_L 0x36U 368 #define REG_HDCPKEY_BANK_37_L 0x37U 369 #define REG_HDCPKEY_BANK_38_L 0x38U 370 #define REG_HDCPKEY_BANK_39_L 0x39U 371 #define REG_HDCPKEY_BANK_3A_L 0x3AU 372 #define REG_HDCPKEY_BANK_3B_L 0x3BU 373 #define REG_HDCPKEY_BANK_3C_L 0x3CU 374 #define REG_HDCPKEY_BANK_3D_L 0x3DU 375 #define REG_HDCPKEY_BANK_3E_L 0x3EU 376 #define REG_HDCPKEY_BANK_3F_L 0x3FU 377 378 #define REG_COMBO_GP_TOP_00_L 0x00U 379 #define REG_COMBO_GP_TOP_01_L 0x01U 380 #define REG_COMBO_GP_TOP_02_L 0x02U 381 #define REG_COMBO_GP_TOP_03_L 0x03U 382 #define REG_COMBO_GP_TOP_04_L 0x04U 383 #define REG_COMBO_GP_TOP_05_L 0x05U 384 #define REG_COMBO_GP_TOP_06_L 0x06U 385 #define REG_COMBO_GP_TOP_07_L 0x07U 386 #define REG_COMBO_GP_TOP_08_L 0x08U 387 #define REG_COMBO_GP_TOP_09_L 0x09U 388 #define REG_COMBO_GP_TOP_0A_L 0x0AU 389 #define REG_COMBO_GP_TOP_0B_L 0x0BU 390 #define REG_COMBO_GP_TOP_0C_L 0x0CU 391 #define REG_COMBO_GP_TOP_0D_L 0x0DU 392 #define REG_COMBO_GP_TOP_0E_L 0x0EU 393 #define REG_COMBO_GP_TOP_0F_L 0x0FU 394 #define REG_COMBO_GP_TOP_10_L 0x10U 395 #define REG_COMBO_GP_TOP_11_L 0x11U 396 #define REG_COMBO_GP_TOP_12_L 0x12U 397 #define REG_COMBO_GP_TOP_13_L 0x13U 398 #define REG_COMBO_GP_TOP_14_L 0x14U 399 #define REG_COMBO_GP_TOP_15_L 0x15U 400 #define REG_COMBO_GP_TOP_16_L 0x16U 401 #define REG_COMBO_GP_TOP_17_L 0x17U 402 #define REG_COMBO_GP_TOP_18_L 0x18U 403 #define REG_COMBO_GP_TOP_19_L 0x19U 404 #define REG_COMBO_GP_TOP_1A_L 0x1AU 405 #define REG_COMBO_GP_TOP_1B_L 0x1BU 406 #define REG_COMBO_GP_TOP_1C_L 0x1CU 407 #define REG_COMBO_GP_TOP_1D_L 0x1DU 408 #define REG_COMBO_GP_TOP_1E_L 0x1EU 409 #define REG_COMBO_GP_TOP_1F_L 0x1FU 410 #define REG_COMBO_GP_TOP_20_L 0x20U 411 #define REG_COMBO_GP_TOP_21_L 0x21U 412 #define REG_COMBO_GP_TOP_22_L 0x22U 413 #define REG_COMBO_GP_TOP_23_L 0x23U 414 #define REG_COMBO_GP_TOP_24_L 0x24U 415 #define REG_COMBO_GP_TOP_25_L 0x25U 416 #define REG_COMBO_GP_TOP_26_L 0x26U 417 #define REG_COMBO_GP_TOP_27_L 0x27U 418 #define REG_COMBO_GP_TOP_28_L 0x28U 419 #define REG_COMBO_GP_TOP_29_L 0x29U 420 #define REG_COMBO_GP_TOP_2A_L 0x2AU 421 #define REG_COMBO_GP_TOP_2B_L 0x2BU 422 #define REG_COMBO_GP_TOP_2C_L 0x2CU 423 #define REG_COMBO_GP_TOP_2D_L 0x2DU 424 #define REG_COMBO_GP_TOP_2E_L 0x2EU 425 #define REG_COMBO_GP_TOP_2F_L 0x2FU 426 #define REG_COMBO_GP_TOP_30_L 0x30U 427 #define REG_COMBO_GP_TOP_31_L 0x31U 428 #define REG_COMBO_GP_TOP_32_L 0x32U 429 #define REG_COMBO_GP_TOP_33_L 0x33U 430 #define REG_COMBO_GP_TOP_34_L 0x34U 431 #define REG_COMBO_GP_TOP_35_L 0x35U 432 #define REG_COMBO_GP_TOP_36_L 0x36U 433 #define REG_COMBO_GP_TOP_37_L 0x37U 434 #define REG_COMBO_GP_TOP_38_L 0x38U 435 #define REG_COMBO_GP_TOP_39_L 0x39U 436 #define REG_COMBO_GP_TOP_3A_L 0x3AU 437 #define REG_COMBO_GP_TOP_3B_L 0x3BU 438 #define REG_COMBO_GP_TOP_3C_L 0x3CU 439 #define REG_COMBO_GP_TOP_3D_L 0x3DU 440 #define REG_COMBO_GP_TOP_3E_L 0x3EU 441 #define REG_COMBO_GP_TOP_3F_L 0x3FU 442 #define REG_COMBO_GP_TOP_40_L 0x40U 443 444 #endif // #ifndef _HDCP_REG_MCU_H_ 445