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93 ////////////////////////////////////////////////////////////////////////////////
94
95 ////////////////////////////////////////////////////////////////////////////////////////////////////
96 // file halHDCP.c
97 // @brief HDCP HAL
98 // @author MStar Semiconductor,Inc.
99 ////////////////////////////////////////////////////////////////////////////////////////////////////
100 /*********************************************************************/
101 /* */
102 /* Includes */
103 /* */
104 /*********************************************************************/
105 #include <stdio.h>
106 #include <string.h>
107 #include "MsCommon.h"
108 #include "MsTypes.h"
109 #include "regHDCP.h"
110 #include "halHDCP.h"
111 #include "drvCPU.h"
112
113 #ifndef HAL_HDCP_C
114 #define HAL_HDCP_C
115
116 /*********************************************************************/
117 /* */
118 /* Defines */
119 /* */
120 /*********************************************************************/
121 #define DEF_HDCP_TX_FUNC_EN 1
122
123 #if(defined(CONFIG_MLOG))
124 #include "ULog.h"
125
126 #define HalHDCPLogInfo(format, args...) ULOGI("HDCP", format, ##args)
127 #define HalHDCPLogWarning(format, args...) ULOGW("HDCP", format, ##args)
128 #define HalHDCPLogDebug(format, args...) ULOGD("HDCP", format, ##args)
129 #define HalHDCPLogError(format, args...) ULOGE("HDCP", format, ##args)
130 #define HalHDCPLogFatal(format, args...) ULOGF("HDCP", format, ##args)
131
132 #else
133
134 #define HalHDCPLogInfo(format, args...) printf(format, ##args)
135 #define HalHDCPLogWarning(format, args...) printf(format, ##args)
136 #define HalHDCPLogDebug(format, args...) printf(format, ##args)
137 #define HalHDCPLogError(format, args...) printf(format, ##args)
138 #define HalHDCPLogFatal(format, args...) printf(format, ##args)
139
140 #endif
141
142
143 #define DEF_SIZE_OF_KSXORLC128 16
144 #define DEF_SIZE_OF_RIV 8
145 #define DEF_SIZE_OF_HDCP1X_KEY 304
146
147 MS_VIRT _gHDCPRegBase = 0x00U;
148 MS_VIRT _gHDCPPMRegBase = 0x00U;
149
150 #define HDCPREG(bank, addr) (*((volatile MS_U16 *)((_gHDCPRegBase + (bank << 1U)) + (addr << 2U))))
151 #define HDCPPMREG(bank, addr) (*((volatile MS_U16 *)((_gHDCPPMRegBase + (bank << 1U)) + (addr << 2U))))
152
153 #define DEF_HDCP14_M0_SIZE 64U //bytes
154
155 /*********************************************************************/
156 /* */
157 /* Global */
158 /* */
159 /*********************************************************************/
160 MS_U8 gu8Hdcp1xKey[DEF_SIZE_OF_HDCP1X_KEY]= {0x00};
161 static MS_BOOL gbIsKmNewMode = FALSE;
162
163 /*********************************************************************/
164 /* */
165 /* Functions */
166 /* */
167 /*********************************************************************/
168 /*********************************************************************/
169 /* */
170 /* Internal */
171 /* */
172 /*********************************************************************/
173
MHalHdcpRegRead(MS_U32 bank,MS_U16 address)174 MS_U16 MHalHdcpRegRead(MS_U32 bank, MS_U16 address)
175 {
176 return HDCPREG(bank, address);
177 }
178
MHalHdcpRegWrite(MS_U32 bank,MS_U16 address,MS_U16 reg_data)179 void MHalHdcpRegWrite(MS_U32 bank, MS_U16 address, MS_U16 reg_data)
180 {
181 HDCPREG(bank, address) = reg_data;
182 }
183
MHalHdcpRegMaskWrite(MS_U32 bank,MS_U16 address,MS_U16 reg_mask,MS_U16 reg_data)184 void MHalHdcpRegMaskWrite(MS_U32 bank, MS_U16 address, MS_U16 reg_mask, MS_U16 reg_data)
185 {
186 MS_U16 reg_value;
187
188 reg_value = (HDCPREG(bank, address) & (~reg_mask)) | (reg_data & reg_mask);
189 HDCPREG(bank, address) = reg_value;
190 }
191
MHalHdcpPMRegRead(MS_U32 bank,MS_U16 address)192 MS_U16 MHalHdcpPMRegRead(MS_U32 bank, MS_U16 address)
193 {
194 return HDCPPMREG(bank, address);
195 }
196
MHalHdcpPMRegWrite(MS_U32 bank,MS_U16 address,MS_U16 reg_data)197 void MHalHdcpPMRegWrite(MS_U32 bank, MS_U16 address, MS_U16 reg_data)
198 {
199 HDCPPMREG(bank, address) = reg_data;
200 }
201
MHalHdcpPMRegMaskWrite(MS_U32 bank,MS_U16 address,MS_U16 reg_mask,MS_U16 reg_data)202 void MHalHdcpPMRegMaskWrite(MS_U32 bank, MS_U16 address, MS_U16 reg_mask, MS_U16 reg_data)
203 {
204 MS_U16 reg_value;
205
206 reg_value = (HDCPPMREG(bank, address) & (~reg_mask)) | (reg_data & reg_mask);
207 HDCPPMREG(bank, address) = reg_value;
208 }
209
210 /*********************************************************************/
211 /* */
212 /* External */
213 /* */
214 /*********************************************************************/
MHal_HDCP_HDCP14TxInitHdcp(MS_U8 u8PortIdx)215 void MHal_HDCP_HDCP14TxInitHdcp(MS_U8 u8PortIdx)
216 {
217 u8PortIdx &= 0x0F;
218
219 //TBD: get bank offset by port index
220 MHalHdcpRegMaskWrite(DEF_HDCP14_TX_REG_BANK, 0x0001, 0x8000, 0x8000); // Enable HDCP encryption
221 MHalHdcpRegMaskWrite(DEF_HDCP14_TX_REG_BANK, 0x0002, 0x001C, 0x0000); //[4]: 1: km new mode; 0: km old mode
222 }
223
MHal_HDCP_HDCP14TxLoadKey(MS_U8 * pu8KeyData,MS_BOOL bUseKmNewMode)224 void MHal_HDCP_HDCP14TxLoadKey(MS_U8* pu8KeyData, MS_BOOL bUseKmNewMode)
225 {
226 gbIsKmNewMode = bUseKmNewMode;
227 if (pu8KeyData != NULL)
228 memcpy(gu8Hdcp1xKey, pu8KeyData, DEF_SIZE_OF_HDCP1X_KEY);
229 }
230
MHal_HDCP_HDCP14TxSetAuthPass(MS_U8 u8PortIdx)231 void MHal_HDCP_HDCP14TxSetAuthPass(MS_U8 u8PortIdx)
232 {
233 u8PortIdx &= 0x0F;
234
235 //TBD: get bank offset by port index
236 MHalHdcpRegMaskWrite(DEF_HDCP14_TX_REG_BANK, 0x0002, 0x000F, 0x000C);
237 }
238
MHal_HDCP_HDCP14TxEnableENC_EN(MS_U8 u8PortIdx,MS_BOOL bEnable)239 void MHal_HDCP_HDCP14TxEnableENC_EN(MS_U8 u8PortIdx, MS_BOOL bEnable)
240 {
241 u8PortIdx &= 0x0F;
242
243 if (bEnable == TRUE)
244 MHalHdcpRegMaskWrite(DEF_HDCP14_TX_REG_BANK, 0x0002, 0x0008, 0x0008);
245 else
246 MHalHdcpRegMaskWrite(DEF_HDCP14_TX_REG_BANK, 0x0002, 0x0008, 0x0000);
247 }
248
MHal_HDCP_HDCP14TxProcessAn(MS_U8 u8PortIdx,MS_BOOL bUseInternalAn,MS_U8 * pu8An)249 void MHal_HDCP_HDCP14TxProcessAn(MS_U8 u8PortIdx, MS_BOOL bUseInternalAn, MS_U8* pu8An)
250 {
251 MS_U8 i = 0;
252 u8PortIdx &= 0x0F;
253
254 if (bUseInternalAn == TRUE)
255 {
256 MHalHdcpRegMaskWrite(DEF_HDCP14_TX_REG_BANK, 0x0001, 0x0100, 0x0100);
257 MHalHdcpRegMaskWrite(DEF_HDCP14_TX_REG_BANK, 0x0002, 0x0002, 0x0002);
258 MHalHdcpRegMaskWrite(DEF_HDCP14_TX_REG_BANK, 0x0002, 0x0002, 0x0000);
259
260 MsOS_DelayTaskUs(1);
261
262 for ( i = 0; i < 4; i++ )
263 {
264 *(pu8An + 2*i) = MHalHdcpRegRead(DEF_HDCP14_TX_REG_BANK, 0x0008 + i) & 0x00FF;
265 *(pu8An + 2*i + 1) = (MHalHdcpRegRead(DEF_HDCP14_TX_REG_BANK, 0x0008 + i) & 0xFF00) >> 8;
266 }
267 }
268 else
269 {
270 MHalHdcpRegMaskWrite(DEF_HDCP14_TX_REG_BANK, 0x0001, 0x0100, 0x0000);
271
272 for ( i = 0; i < 4; i++ )
273 {
274 MHalHdcpRegWrite(DEF_HDCP14_TX_REG_BANK, 0x0008 + i, ((*(pu8An + 2*i + 1) << 8) | (*(pu8An + 2*i))));
275 }
276 }
277 }
278
279
MHal_HDCP_HDCP14TxGetAKSV(MS_U8 u8PortIdx,MS_U8 * pu8Aksv)280 void MHal_HDCP_HDCP14TxGetAKSV(MS_U8 u8PortIdx, MS_U8* pu8Aksv)
281 {
282 MS_U8 u8ByteCnt = 0;
283
284 u8PortIdx &= 0x0F;
285
286 for (u8ByteCnt = 0; u8ByteCnt < 5; u8ByteCnt++ )
287 {
288 *(pu8Aksv + u8ByteCnt) = gu8Hdcp1xKey[u8ByteCnt];
289 }
290 }
291
292
MHal_HDCP_HDCP14TxCompareRi(MS_U8 u8PortIdx,MS_U8 * pu8SinkRi)293 MS_BOOL MHal_HDCP_HDCP14TxCompareRi(MS_U8 u8PortIdx, MS_U8* pu8SinkRi)
294 {
295 MS_BOOL bRet = FALSE;
296 MS_U16 u16SrcRi = 0x0000;
297 MS_U16 ulSinkRi = *pu8SinkRi;
298 u8PortIdx &= 0x0F;
299
300 do
301 {
302 u16SrcRi = MHalHdcpRegRead(DEF_HDCP14_TX_REG_BANK, 0x0000);
303
304 if(u16SrcRi == ulSinkRi)
305 {
306 bRet = TRUE;
307 break;
308 }
309
310 u16SrcRi = MHalHdcpRegRead(DEF_HDCP14_TX_REG_BANK, 0x0000);
311
312 if(u16SrcRi == ulSinkRi)
313 {
314 bRet = TRUE;
315 break;
316 }
317
318 } while (FALSE);
319
320 return bRet;
321 }
322
323
MHal_HDCP_HDCP14TxConfigMode(MS_U8 u8PortIdx,MS_U8 u8Mode)324 void MHal_HDCP_HDCP14TxConfigMode(MS_U8 u8PortIdx, MS_U8 u8Mode)
325 {
326 u8PortIdx &= 0x0F;
327
328 MHalHdcpRegMaskWrite(DEF_HDCP14_TX_REG_BANK, 0x0001, 0x0E00, u8Mode << 8);
329 }
330
331
MHal_HDCP_HDCP14TxGenerateCipher(MS_U8 u8PortIdx,MS_U8 * pu8Bksv)332 void MHal_HDCP_HDCP14TxGenerateCipher(MS_U8 u8PortIdx, MS_U8* pu8Bksv)
333 {
334 #define DEF_HDCP1X_KEY_OFFSET 8U
335
336 MS_U8 u8Lm[7] = {0};
337 MS_U8 u8ByteCnt = 0;
338 MS_U8 u8BitCnt = 0;
339 MS_U8 u8LmCnt = 0;
340 MS_U8 u8CarryBit = 0;
341 MS_U8 u8Seed = 0;
342 MS_U8 u8Tmp = 0;
343 MS_U16 u16Offset = 0;
344
345 for (u8ByteCnt = 0; u8ByteCnt < 5; u8ByteCnt++)
346 {
347 for (u8BitCnt = 0; u8BitCnt < 8; u8BitCnt++)
348 {
349 if (*(pu8Bksv + u8ByteCnt) & (1 << u8BitCnt))
350 {
351 u8CarryBit = 0;
352 u16Offset = (u8ByteCnt * 8 + u8BitCnt) * 7 + DEF_HDCP1X_KEY_OFFSET;
353
354 for (u8LmCnt = 0; u8LmCnt < 7; u8LmCnt++)
355 {
356 u8Seed = (u8LmCnt + gu8Hdcp1xKey[7]) % 7;
357 u8Tmp = gu8Hdcp1xKey[u16Offset + u8LmCnt] ^ gu8Hdcp1xKey[u8Seed];
358
359 u8Lm[u8LmCnt] = u8Lm[u8LmCnt] + u8Tmp + u8CarryBit;
360 if (((u8CarryBit == 0) && (u8Lm[u8LmCnt] >= u8Tmp)) || ((u8CarryBit == 1) && (u8Lm[u8LmCnt] > u8Tmp)))
361 u8CarryBit = 0;
362 else
363 u8CarryBit = 1;
364 }
365 }
366 }
367 }
368
369 u8Tmp = gu8Hdcp1xKey[288];
370
371 for (u8LmCnt = 0; u8LmCnt < 7; u8LmCnt++)
372 {
373 if (u8LmCnt < 6)
374 u8Lm[u8LmCnt] = u8Lm[u8LmCnt] ^ u8Tmp;
375 else
376 u8Lm[u8LmCnt] = u8Lm[u8LmCnt] ^ (~u8Tmp);
377
378 if (u8LmCnt % 2 != 0)
379 MHalHdcpRegWrite(DEF_HDCP14_TX_REG_BANK, 0x0004 + (u8LmCnt/2), (u8Lm[u8LmCnt] << 8) | u8Lm[u8LmCnt - 1]);
380 }
381
382 MHalHdcpRegWrite(DEF_HDCP14_TX_REG_BANK, 0x0007, (u8Tmp << 8) | u8Lm[6]);
383
384 #undef DEF_HDCP1X_KEY_OFFSET
385
386 }
387
MHal_HDCP_HDCP14TxProcessR0(MS_U8 u8PortIdx)388 MS_BOOL MHal_HDCP_HDCP14TxProcessR0(MS_U8 u8PortIdx)
389 {
390 MS_U8 u8Cnt = 0;
391
392 MHalHdcpRegMaskWrite(DEF_HDCP14_TX_REG_BANK, 0x0002, 0x000F, 0x0000);
393 MHalHdcpRegMaskWrite(DEF_HDCP14_TX_REG_BANK, 0x0002, 0x000F, 0x0001);
394 MHalHdcpRegMaskWrite(DEF_HDCP14_TX_REG_BANK, 0x0002, 0x000F, 0x0000);
395
396 while (u8Cnt-- && !(MHalHdcpRegRead(DEF_HDCP14_TX_REG_BANK, 0x0002) & 0x0100));
397
398 return ((u8Cnt == 0) ? FALSE : TRUE);
399 }
400
MHal_HDCP_HDCP14TxGetM0(MS_U8 u8PortIdx,MS_U8 * pu8M0)401 void MHal_HDCP_HDCP14TxGetM0(MS_U8 u8PortIdx, MS_U8* pu8M0)
402 {
403 #define DEF_HDCP1X_M0_SIZE 8
404 unsigned char u8DataCnt = 0;
405 MS_U16 u16BKOffset = 0x00;
406 MS_U16 u16RegVal = 0x00;
407
408 u8PortIdx &= 0x0F;
409
410 for ( u8DataCnt = 0; u8DataCnt < (DEF_HDCP1X_M0_SIZE>>1); u8DataCnt++ )
411 {
412 u16RegVal = MHalHdcpRegRead(DEF_HDCP14_TX_REG_BANK + u16BKOffset, 0x0C + u8DataCnt);
413 *(pu8M0 + 2*u8DataCnt) = (MS_U8)(u16RegVal & 0x00FF);
414 *(pu8M0 + 2*u8DataCnt + 1) = (MS_U8)((u16RegVal & 0xFF00)>>8);
415
416 }
417 #undef DEF_HDCP1X_M0_SIZE
418 }
419
MHal_HDCP_HDCP14GetM0(MS_U8 u8PortIdx,MS_U8 * pu8Data)420 void MHal_HDCP_HDCP14GetM0(MS_U8 u8PortIdx, MS_U8 *pu8Data)
421 {
422 MS_U8 cnt = 0x00;
423 MS_U16 u16BKOffset = 0x00;
424
425 u8PortIdx &= 0x0F;
426 u16BKOffset = u8PortIdx * 0x300;
427
428 for ( cnt = 0; cnt < (DEF_HDCP14_M0_SIZE >> 4); cnt++ )
429 {
430 MS_U16 u16tmpData = 0x00;
431
432 u16tmpData = MHalHdcpRegRead(DEF_HDCP14_RX_REG_BANK + u16BKOffset, 0x0E + cnt);
433
434 *(pu8Data + cnt*2) = (MS_U8)(u16tmpData & 0x00FF);
435 *(pu8Data + cnt*2 + 1) = (MS_U8)((u16tmpData & 0xFF00) >> 8);
436 }
437 }
438
MHal_HDCP_HDCP14FillKey(MS_U8 * pu8KeyData)439 void MHal_HDCP_HDCP14FillKey(MS_U8 *pu8KeyData)
440 {
441 MS_U16 ustemp = 0;
442
443 MHalHdcpRegMaskWrite(DEF_HDCPKEY_REG_BANK, REG_HDCPKEY_BANK_02_L, BIT(8), BIT(8));
444
445 // HDCP key
446 MHalHdcpRegMaskWrite(DEF_COMBO_GP_TOP_REG_BANK, REG_COMBO_GP_TOP_40_L, BIT(3)|BIT(2)|BIT(0), BIT(3)|BIT(2)|BIT(0)); // [2]: CPU write enable, [3]: 0: 74 RAM, 1 :HDCP RAM
447 // burst write from address 0x05
448 MHalHdcpRegMaskWrite(DEF_HDCPKEY_REG_BANK, REG_HDCPKEY_BANK_00_L, 0x05, BMASK(9:0)); // address
449
450 for(ustemp = 0; ustemp < 284; ustemp++)
451 {
452 MHalHdcpRegMaskWrite(DEF_HDCPKEY_REG_BANK, REG_HDCPKEY_BANK_01_L, *(pu8KeyData +ustemp), BMASK(7:0)); // data
453 }
454
455 MHalHdcpRegMaskWrite(DEF_COMBO_GP_TOP_REG_BANK, REG_COMBO_GP_TOP_40_L, 0, BIT(3)|BIT(2)|BIT(0)); // [2]: CPU write enable, [3]: 0: 74 RAM, 1 :HDCP RAM
456 }
457
MHal_HDCP_SetBank(MS_U32 u32NonPmBankAddr,MS_U32 u32PmBankAddr)458 void MHal_HDCP_SetBank(MS_U32 u32NonPmBankAddr, MS_U32 u32PmBankAddr)
459 {
460 HalHDCPLogInfo("u32NonPmBankAddr = 0x%X, u32PmBankAddr = 0x%X\r\n", (unsigned int)u32NonPmBankAddr, (unsigned int)u32PmBankAddr);
461 _gHDCPRegBase = u32NonPmBankAddr;
462 _gHDCPPMRegBase = u32PmBankAddr;
463 }
464
MHal_HDCP_HDCP2TxInit(MS_U8 u8PortIdx,MS_BOOL bEnable)465 void MHal_HDCP_HDCP2TxInit(MS_U8 u8PortIdx, MS_BOOL bEnable)
466 {
467 MS_U16 u16BKOffset = 0x00;
468
469 MHalHdcpRegMaskWrite(DEF_HDCP22_TX_REG_BANK + u16BKOffset, 0x0000, 0x11, bEnable ? 0x11 : 0x00); // bit 0: enable hdcp22; bit 4: enable EESS
470 if (bEnable)
471 {
472 MHalHdcpRegMaskWrite(DEF_HDCP22_TX_REG_BANK + u16BKOffset, 0x0000, 0x02, 0x02); //reset hdcp22 FSM
473 MHalHdcpRegMaskWrite(DEF_HDCP22_TX_REG_BANK + u16BKOffset, 0x0000, 0x02, 0x00);
474 }
475 }
476
MHal_HDCP_HDCP2TxEnableEncrypt(MS_U8 u8PortIdx,MS_BOOL bEnable)477 void MHal_HDCP_HDCP2TxEnableEncrypt(MS_U8 u8PortIdx, MS_BOOL bEnable)
478 {
479 MS_U16 u16BKOffset = 0x00;
480
481 MHalHdcpRegMaskWrite(DEF_HDCP22_TX_REG_BANK + u16BKOffset, 0x0000, 0x04, bEnable ? 0x04 : 0x00); //bit 2: authentication pass
482 MHalHdcpRegMaskWrite(DEF_HDCP22_TX_REG_BANK + u16BKOffset, 0x0000, 0x08, bEnable ? 0x08 : 0x00); //bit 3: enable hdcp22 to issue encryption enable signal
483 }
484
MHal_HDCP_HDCP2TxFillCipherKey(MS_U8 u8PortIdx,MS_U8 * pu8Riv,MS_U8 * pu8KsXORLC128)485 void MHal_HDCP_HDCP2TxFillCipherKey(MS_U8 u8PortIdx, MS_U8 *pu8Riv, MS_U8 *pu8KsXORLC128)
486 {
487 MS_U8 cnt = 0;
488 MS_U16 u16BKOffset = 0x00;
489 //MS_U16 u16RegOffset = 0x00;
490
491
492 //Ks^LC128
493 for ( cnt = 0; cnt < (DEF_SIZE_OF_KSXORLC128>>1); cnt++)
494 MHalHdcpRegWrite(DEF_HDCP22_TX_KEY_REG_BANK + u16BKOffset, 0x60 + (DEF_SIZE_OF_KSXORLC128 >> 1) - 1 - cnt, *(pu8KsXORLC128 + cnt*2 + 1)|(*(pu8KsXORLC128 + cnt*2)<<8));
495
496 //Riv
497 for ( cnt = 0; cnt < (DEF_SIZE_OF_RIV>>1); cnt++)
498 MHalHdcpRegWrite(DEF_HDCP22_TX_KEY_REG_BANK + u16BKOffset, 0x68 + (DEF_SIZE_OF_RIV >> 1) - 1 - cnt, *(pu8Riv + cnt*2 + 1)|(*(pu8Riv + cnt*2)<<8));
499
500 }
501
MHal_HDCP_HDCP2TxGetCipherState(MS_U8 u8PortIdx,MS_U8 * pu8State)502 void MHal_HDCP_HDCP2TxGetCipherState(MS_U8 u8PortIdx, MS_U8 *pu8State)
503 {
504 MS_U16 u16BKOffset = 0x00;
505 //MS_U16 u16RegOffset = 0x00;
506
507 *pu8State = MHalHdcpRegRead(DEF_HDCP22_TX_REG_BANK + u16BKOffset, 0x00) & 0x0C;
508 }
509
MHal_HDCP_HDCP2TxSetAuthPass(MS_U8 u8PortIdx,MS_BOOL bEnable)510 void MHal_HDCP_HDCP2TxSetAuthPass(MS_U8 u8PortIdx, MS_BOOL bEnable)
511 {
512 MS_U16 u16BKOffset = 0x00;
513
514 MHalHdcpRegMaskWrite(DEF_HDCP22_TX_REG_BANK + u16BKOffset, 0x0000, 0x04, bEnable ? 0x04 : 0x00); //bit 2: authentication pass
515 }
516
MHal_HDCP_HDCP2RxInit(MS_U8 u8PortIdx)517 void MHal_HDCP_HDCP2RxInit(MS_U8 u8PortIdx)
518 {
519 MS_U16 u16BKOffset = 0x00;
520
521 u16BKOffset = u8PortIdx * 0x300;
522 // [1] Enable auto-clear SKE status when receiving ake_init; [2] Enable auto-clear SKE status when no hdcp22 capability
523 MHalHdcpRegMaskWrite(DEF_HDCP22_RX_REG_BANK + u16BKOffset, 0x4E, 0x0006, 0x0006);
524 }
525
MHal_HDCP_HDCP2RxProcessCipher(MS_U8 u8PortIdx,MS_U8 * pu8Riv,MS_U8 * pu8ContentKey)526 void MHal_HDCP_HDCP2RxProcessCipher(MS_U8 u8PortIdx, MS_U8* pu8Riv, MS_U8 *pu8ContentKey)
527 {
528 MS_U8 cnt = 0;
529 MS_U16 u16BKOffset = 0x00;
530 MS_U16 u16RegOffset = 0x00;
531
532 u16BKOffset = u8PortIdx * 0x300;
533 u16RegOffset = u8PortIdx * 0x0C;
534
535 HalHDCPLogDebug("%s:: PortIdx : BKOffset : RegOffset = 0x%X : 0x%X : 0x%X\r\n", __FUNCTION__, u8PortIdx, u16BKOffset, u16RegOffset);
536
537 //Ks^LC128
538 for ( cnt = 0; cnt < (DEF_SIZE_OF_KSXORLC128>>1); cnt++)
539 MHalHdcpRegWrite(DEF_HDCP22_RX_KEY_REG_BANK, u16RegOffset + 0x30 + (DEF_SIZE_OF_KSXORLC128 >> 1) - 1 - cnt, *(pu8ContentKey + cnt*2 + 1)|(*(pu8ContentKey + cnt*2)<<8));
540
541 //Riv
542 for ( cnt = 0; cnt < (DEF_SIZE_OF_RIV>>1); cnt++)
543 MHalHdcpRegWrite(DEF_HDCP22_RX_KEY_REG_BANK, u16RegOffset + 0x38 + (DEF_SIZE_OF_RIV >> 1) - 1 - cnt, *(pu8Riv + cnt*2 + 1)|(*(pu8Riv + cnt*2)<<8));
544
545 //Set SKE successful
546 MHalHdcpRegMaskWrite(DEF_HDCP22_RX_REG_BANK + u16BKOffset, 0x4E, 0x0001, 0x0001);
547 }
548
MHal_HDCP_HDCP2RxSetSKEPass(MS_U8 u8PortIdx,MS_BOOL bEnable)549 void MHal_HDCP_HDCP2RxSetSKEPass(MS_U8 u8PortIdx, MS_BOOL bEnable)
550 {
551 MS_U16 u16BKOffset = 0x00;
552
553 u16BKOffset = u8PortIdx * 0x300;
554 //Set SKE successful
555 MHalHdcpRegMaskWrite(DEF_HDCP22_RX_REG_BANK + u16BKOffset, 0x4E, 0x0001, bEnable ? 0x0001 : 0x0000);
556 }
557
MHal_HDCP_HDCP2RxFillCipherKey(MS_U8 u8PortIdx,MS_U8 * pu8Riv,MS_U8 * pu8ContentKey)558 void MHal_HDCP_HDCP2RxFillCipherKey(MS_U8 u8PortIdx, MS_U8* pu8Riv, MS_U8 *pu8ContentKey)
559 {
560 MS_U8 cnt = 0;
561 MS_U16 u16BKOffset = 0x00;
562 MS_U16 u16RegOffset = 0x00;
563
564 //Ks^LC128
565 for ( cnt = 0; cnt < (DEF_SIZE_OF_KSXORLC128>>1); cnt++)
566 MHalHdcpRegWrite(DEF_HDCP22_RX_KEY_REG_BANK + u16BKOffset, u16RegOffset + 0x30 + (DEF_SIZE_OF_KSXORLC128 >> 1) - 1 - cnt, *(pu8ContentKey + cnt*2 + 1)|(*(pu8ContentKey + cnt*2)<<8));
567
568 //Riv
569 for ( cnt = 0; cnt < (DEF_SIZE_OF_RIV>>1); cnt++)
570 MHalHdcpRegWrite(DEF_HDCP22_RX_KEY_REG_BANK + u16BKOffset, u16RegOffset + 0x38 + (DEF_SIZE_OF_RIV >> 1) - 1 - cnt, *(pu8Riv + cnt*2 + 1)|(*(pu8Riv + cnt*2)<<8));
571 }
572
MHal_HDCP_HDCP2RxGetCipherState(MS_U8 u8PortIdx,MS_U8 * pu8State)573 void MHal_HDCP_HDCP2RxGetCipherState(MS_U8 u8PortIdx, MS_U8 *pu8State)
574 {
575 MS_U16 u16BKOffset = 0x00;
576 //MS_U16 u16RegOffset = 0x00;
577
578 u16BKOffset = u8PortIdx * 0x300;
579
580 *pu8State = MHalHdcpRegRead(DEF_HDCP22_RX_REG_BANK + u16BKOffset, 0x4E) & 0x01;
581 }
582
MHal_HDCP_HDCP1TxEncrytionStatus(MS_U8 u8PortIdx,MS_U8 u8SetStatusFlag,MS_U32 u32SetStatus)583 MS_U32 MHal_HDCP_HDCP1TxEncrytionStatus(MS_U8 u8PortIdx, MS_U8 u8SetStatusFlag, MS_U32 u32SetStatus)
584 {
585 MS_U32 u32GetStatus = 0;
586
587 if(u8SetStatusFlag) // Set HDCP1 encrytion status
588 {
589 MHalHdcpRegMaskWrite(DEF_HDCP14_TX_REG_BANK, REG_HDCP14_TX_02_L, BIT(3), u32SetStatus? BIT(3): 0); //bit 3: enable hdcp14 to issue encryption enable signal
590 }
591
592 // Get HDCP1 encrytion status
593 if(MHalHdcpRegRead(DEF_HDCP14_TX_REG_BANK, REG_HDCP14_TX_02_L) &BIT(3))
594 {
595 u32GetStatus = TRUE;
596 }
597
598 return u32GetStatus;
599 }
600
MHal_HDCP_HDCP2TxEncrytionStatus(MS_U8 u8PortIdx,MS_U8 u8SetStatusFlag,MS_U32 u32SetStatus)601 MS_U32 MHal_HDCP_HDCP2TxEncrytionStatus(MS_U8 u8PortIdx, MS_U8 u8SetStatusFlag, MS_U32 u32SetStatus)
602 {
603 MS_U32 u32GetStatus = 0;
604
605 if(u8SetStatusFlag) // Set HDCP2 encrytion status
606 {
607 MHalHdcpRegMaskWrite(DEF_HDCP22_TX_REG_BANK, REG_HDCP22_TX_00_L, BIT(3), u32SetStatus? BIT(3): 0); //bit 3: enable hdcp22 to issue encryption enable signal
608 }
609
610 // Get HDCP2 encrytion status
611 if(MHalHdcpRegRead(DEF_HDCP22_TX_REG_BANK, REG_HDCP22_TX_00_L) &BIT(3))
612 {
613 u32GetStatus = TRUE;
614 }
615
616 return u32GetStatus;
617 }
618
MHal_HDCP_HDCPTxHDMIStatus(MS_U8 u8PortIdx,MS_U8 u8SetStatusFlag,MS_U32 u32SetStatus)619 MS_U32 MHal_HDCP_HDCPTxHDMIStatus(MS_U8 u8PortIdx, MS_U8 u8SetStatusFlag, MS_U32 u32SetStatus)
620 {
621 MS_U32 u32GetStatus = 0;
622
623 if(u8SetStatusFlag) // Set HDNI status
624 {
625 MHalHdcpRegMaskWrite(DEF_HDMITX_PHY_REG_BANK, REG_HDMITX_PHY_39_L, 0xFFFF, u32SetStatus? 0xF000: 0xFFFF);
626 MHalHdcpRegMaskWrite(DEF_HDMITX_PHY_REG_BANK, REG_HDMITX_PHY_2E_L, 0xE800, u32SetStatus? 0xE800: 0x0000);
627 }
628
629 // Get HDNI status
630 if((MHalHdcpRegRead(DEF_HDMITX_PHY_REG_BANK, REG_HDMITX_PHY_2E_L) &0xE800) == 0xE800)
631 {
632 u32GetStatus = TRUE;
633 }
634
635 return u32GetStatus;
636 }
637
638 #endif //#ifndef HAL_HDCP_C
639