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Searched refs:REG_C_IRQ_HYP_FINAL_STATUS (Results 1 – 22 of 22) sorted by relevance

/utopia/UTPA2-700.0.x/modules/irq/hal/M7821/irq/
H A DregIRQ.h216 #define REG_C_IRQ_HYP_FINAL_STATUS REG_FRC_C_IRQ_HYP_FINAL_STATUS macro
237 #define REG_C_IRQ_HYP_FINAL_STATUS REG_AEON_C_IRQ_HYP_FINAL_STATUS macro
262 #define REG_C_IRQ_HYP_FINAL_STATUS REG_MIPS_C_IRQ_HYP_FINAL_STATUS macro
288 #define REG_C_IRQ_HYP_FINAL_STATUS REG_MIPS_C_IRQ_HYP_FINAL_STATUS macro
312 #define REG_C_IRQ_HYP_FINAL_STATUS REG_MIPS_C_IRQ_HYP_FINAL_STATUS macro
335 #define REG_C_IRQ_HYP_FINAL_STATUS REG_MIPS_C_IRQ_HYP_FINAL_STATUS macro
359 #define REG_C_IRQ_HYP_FINAL_STATUS REG_MIPS_C_IRQ_HYP_FINAL_STATUS macro
382 #define REG_C_IRQ_HYP_FINAL_STATUS REG_MIPS_C_IRQ_HYP_FINAL_STATUS macro
H A DhalIRQ.c593 status = _IRQ_Read4Byte(REG_C_IRQ_HYP_FINAL_STATUS); in _HAL_IRQ_IRQHnd()
/utopia/UTPA2-700.0.x/modules/irq/hal/macan/irq/
H A DregIRQ.h216 #define REG_C_IRQ_HYP_FINAL_STATUS REG_FRC_C_IRQ_HYP_FINAL_STATUS macro
237 #define REG_C_IRQ_HYP_FINAL_STATUS REG_AEON_C_IRQ_HYP_FINAL_STATUS macro
262 #define REG_C_IRQ_HYP_FINAL_STATUS REG_MIPS_C_IRQ_HYP_FINAL_STATUS macro
288 #define REG_C_IRQ_HYP_FINAL_STATUS REG_MIPS_C_IRQ_HYP_FINAL_STATUS macro
312 #define REG_C_IRQ_HYP_FINAL_STATUS REG_MIPS_C_IRQ_HYP_FINAL_STATUS macro
335 #define REG_C_IRQ_HYP_FINAL_STATUS REG_MIPS_C_IRQ_HYP_FINAL_STATUS macro
359 #define REG_C_IRQ_HYP_FINAL_STATUS REG_MIPS_C_IRQ_HYP_FINAL_STATUS macro
382 #define REG_C_IRQ_HYP_FINAL_STATUS REG_MIPS_C_IRQ_HYP_FINAL_STATUS macro
H A DhalIRQ.c587 status = _IRQ_Read4Byte(REG_C_IRQ_HYP_FINAL_STATUS); in _HAL_IRQ_IRQHnd()
/utopia/UTPA2-700.0.x/modules/irq/hal/maserati/irq/
H A DregIRQ.h216 #define REG_C_IRQ_HYP_FINAL_STATUS REG_FRC_C_IRQ_HYP_FINAL_STATUS macro
237 #define REG_C_IRQ_HYP_FINAL_STATUS REG_AEON_C_IRQ_HYP_FINAL_STATUS macro
262 #define REG_C_IRQ_HYP_FINAL_STATUS REG_MIPS_C_IRQ_HYP_FINAL_STATUS macro
288 #define REG_C_IRQ_HYP_FINAL_STATUS REG_MIPS_C_IRQ_HYP_FINAL_STATUS macro
312 #define REG_C_IRQ_HYP_FINAL_STATUS REG_MIPS_C_IRQ_HYP_FINAL_STATUS macro
335 #define REG_C_IRQ_HYP_FINAL_STATUS REG_MIPS_C_IRQ_HYP_FINAL_STATUS macro
359 #define REG_C_IRQ_HYP_FINAL_STATUS REG_MIPS_C_IRQ_HYP_FINAL_STATUS macro
H A DhalIRQ.c591 status = _IRQ_Read4Byte(REG_C_IRQ_HYP_FINAL_STATUS); in _HAL_IRQ_IRQHnd()
/utopia/UTPA2-700.0.x/modules/irq/hal/manhattan/irq/
H A DregIRQ.h216 #define REG_C_IRQ_HYP_FINAL_STATUS REG_FRC_C_IRQ_HYP_FINAL_STATUS macro
237 #define REG_C_IRQ_HYP_FINAL_STATUS REG_AEON_C_IRQ_HYP_FINAL_STATUS macro
262 #define REG_C_IRQ_HYP_FINAL_STATUS REG_MIPS_C_IRQ_HYP_FINAL_STATUS macro
288 #define REG_C_IRQ_HYP_FINAL_STATUS REG_MIPS_C_IRQ_HYP_FINAL_STATUS macro
312 #define REG_C_IRQ_HYP_FINAL_STATUS REG_MIPS_C_IRQ_HYP_FINAL_STATUS macro
335 #define REG_C_IRQ_HYP_FINAL_STATUS REG_MIPS_C_IRQ_HYP_FINAL_STATUS macro
359 #define REG_C_IRQ_HYP_FINAL_STATUS REG_MIPS_C_IRQ_HYP_FINAL_STATUS macro
H A DhalIRQ.c587 status = _IRQ_Read4Byte(REG_C_IRQ_HYP_FINAL_STATUS); in _HAL_IRQ_IRQHnd()
/utopia/UTPA2-700.0.x/modules/irq/hal/maxim/irq/
H A DregIRQ.h216 #define REG_C_IRQ_HYP_FINAL_STATUS REG_FRC_C_IRQ_HYP_FINAL_STATUS macro
237 #define REG_C_IRQ_HYP_FINAL_STATUS REG_AEON_C_IRQ_HYP_FINAL_STATUS macro
262 #define REG_C_IRQ_HYP_FINAL_STATUS REG_MIPS_C_IRQ_HYP_FINAL_STATUS macro
288 #define REG_C_IRQ_HYP_FINAL_STATUS REG_MIPS_C_IRQ_HYP_FINAL_STATUS macro
312 #define REG_C_IRQ_HYP_FINAL_STATUS REG_MIPS_C_IRQ_HYP_FINAL_STATUS macro
335 #define REG_C_IRQ_HYP_FINAL_STATUS REG_MIPS_C_IRQ_HYP_FINAL_STATUS macro
359 #define REG_C_IRQ_HYP_FINAL_STATUS REG_MIPS_C_IRQ_HYP_FINAL_STATUS macro
H A DhalIRQ.c591 status = _IRQ_Read4Byte(REG_C_IRQ_HYP_FINAL_STATUS); in _HAL_IRQ_IRQHnd()
/utopia/UTPA2-700.0.x/modules/irq/hal/M7621/irq/
H A DregIRQ.h216 #define REG_C_IRQ_HYP_FINAL_STATUS REG_FRC_C_IRQ_HYP_FINAL_STATUS macro
237 #define REG_C_IRQ_HYP_FINAL_STATUS REG_AEON_C_IRQ_HYP_FINAL_STATUS macro
262 #define REG_C_IRQ_HYP_FINAL_STATUS REG_MIPS_C_IRQ_HYP_FINAL_STATUS macro
288 #define REG_C_IRQ_HYP_FINAL_STATUS REG_MIPS_C_IRQ_HYP_FINAL_STATUS macro
312 #define REG_C_IRQ_HYP_FINAL_STATUS REG_MIPS_C_IRQ_HYP_FINAL_STATUS macro
335 #define REG_C_IRQ_HYP_FINAL_STATUS REG_MIPS_C_IRQ_HYP_FINAL_STATUS macro
359 #define REG_C_IRQ_HYP_FINAL_STATUS REG_MIPS_C_IRQ_HYP_FINAL_STATUS macro
H A DhalIRQ.c591 status = _IRQ_Read4Byte(REG_C_IRQ_HYP_FINAL_STATUS); in _HAL_IRQ_IRQHnd()
/utopia/UTPA2-700.0.x/modules/irq/hal/kano/irq/
H A DregIRQ.h174 #define REG_C_IRQ_HYP_FINAL_STATUS REG_AEON_C_IRQ_HYP_FINAL_STATUS macro
196 #define REG_C_IRQ_HYP_FINAL_STATUS REG_MIPS_C_IRQ_HYP_FINAL_STATUS macro
H A DhalIRQ.c539 status = _IRQ_Read4Byte(REG_C_IRQ_HYP_FINAL_STATUS); in _HAL_IRQ_IRQHnd()
/utopia/UTPA2-700.0.x/modules/irq/hal/k7u/irq/
H A DregIRQ.h174 #define REG_C_IRQ_HYP_FINAL_STATUS REG_AEON_C_IRQ_HYP_FINAL_STATUS macro
196 #define REG_C_IRQ_HYP_FINAL_STATUS REG_MIPS_C_IRQ_HYP_FINAL_STATUS macro
H A DhalIRQ.c539 status = _IRQ_Read4Byte(REG_C_IRQ_HYP_FINAL_STATUS); in _HAL_IRQ_IRQHnd()
/utopia/UTPA2-700.0.x/modules/irq/hal/k6lite/irq/
H A DregIRQ.h174 #define REG_C_IRQ_HYP_FINAL_STATUS REG_AEON_C_IRQ_HYP_FINAL_STATUS macro
196 #define REG_C_IRQ_HYP_FINAL_STATUS REG_MIPS_C_IRQ_HYP_FINAL_STATUS macro
H A DhalIRQ.c539 status = _IRQ_Read4Byte(REG_C_IRQ_HYP_FINAL_STATUS); in _HAL_IRQ_IRQHnd()
/utopia/UTPA2-700.0.x/modules/irq/hal/curry/irq/
H A DregIRQ.h174 #define REG_C_IRQ_HYP_FINAL_STATUS REG_AEON_C_IRQ_HYP_FINAL_STATUS macro
196 #define REG_C_IRQ_HYP_FINAL_STATUS REG_MIPS_C_IRQ_HYP_FINAL_STATUS macro
H A DhalIRQ.c539 status = _IRQ_Read4Byte(REG_C_IRQ_HYP_FINAL_STATUS); in _HAL_IRQ_IRQHnd()
/utopia/UTPA2-700.0.x/modules/irq/hal/k6/irq/
H A DregIRQ.h174 #define REG_C_IRQ_HYP_FINAL_STATUS REG_AEON_C_IRQ_HYP_FINAL_STATUS macro
196 #define REG_C_IRQ_HYP_FINAL_STATUS REG_MIPS_C_IRQ_HYP_FINAL_STATUS macro
H A DhalIRQ.c539 status = _IRQ_Read4Byte(REG_C_IRQ_HYP_FINAL_STATUS); in _HAL_IRQ_IRQHnd()