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Searched refs:REG_C_FIQ_HYP_CLR (Results 1 – 22 of 22) sorted by relevance

/utopia/UTPA2-700.0.x/modules/irq/hal/M7821/irq/
H A DregIRQ.h209 #define REG_C_FIQ_HYP_CLR REG_FRC_C_FIQ_HYP_CLR macro
230 #define REG_C_FIQ_HYP_CLR REG_AEON_C_FIQ_HYP_CLR macro
255 #define REG_C_FIQ_HYP_CLR REG_MIPS_C_FIQ_HYP_CLR macro
281 #define REG_C_FIQ_HYP_CLR REG_MIPS_C_FIQ_HYP_CLR macro
305 #define REG_C_FIQ_HYP_CLR REG_MIPS_C_FIQ_HYP_CLR macro
328 #define REG_C_FIQ_HYP_CLR REG_MIPS_C_FIQ_HYP_CLR macro
352 #define REG_C_FIQ_HYP_CLR REG_MIPS_C_FIQ_HYP_CLR macro
375 #define REG_C_FIQ_HYP_CLR REG_MIPS_C_FIQ_HYP_CLR macro
H A DhalIRQ.c490 _IRQ_Write4Byte(REG_C_FIQ_HYP_CLR, status); in _HAL_IRQ_FIQHnd()
491 _IRQ_Write4Byte(REG_C_FIQ_HYP_CLR, 0); in _HAL_IRQ_FIQHnd()
/utopia/UTPA2-700.0.x/modules/irq/hal/macan/irq/
H A DregIRQ.h209 #define REG_C_FIQ_HYP_CLR REG_FRC_C_FIQ_HYP_CLR macro
230 #define REG_C_FIQ_HYP_CLR REG_AEON_C_FIQ_HYP_CLR macro
255 #define REG_C_FIQ_HYP_CLR REG_MIPS_C_FIQ_HYP_CLR macro
281 #define REG_C_FIQ_HYP_CLR REG_MIPS_C_FIQ_HYP_CLR macro
305 #define REG_C_FIQ_HYP_CLR REG_MIPS_C_FIQ_HYP_CLR macro
328 #define REG_C_FIQ_HYP_CLR REG_MIPS_C_FIQ_HYP_CLR macro
352 #define REG_C_FIQ_HYP_CLR REG_MIPS_C_FIQ_HYP_CLR macro
375 #define REG_C_FIQ_HYP_CLR REG_MIPS_C_FIQ_HYP_CLR macro
H A DhalIRQ.c484 _IRQ_Write4Byte(REG_C_FIQ_HYP_CLR, status); in _HAL_IRQ_FIQHnd()
485 _IRQ_Write4Byte(REG_C_FIQ_HYP_CLR, 0); in _HAL_IRQ_FIQHnd()
/utopia/UTPA2-700.0.x/modules/irq/hal/maserati/irq/
H A DregIRQ.h209 #define REG_C_FIQ_HYP_CLR REG_FRC_C_FIQ_HYP_CLR macro
230 #define REG_C_FIQ_HYP_CLR REG_AEON_C_FIQ_HYP_CLR macro
255 #define REG_C_FIQ_HYP_CLR REG_MIPS_C_FIQ_HYP_CLR macro
281 #define REG_C_FIQ_HYP_CLR REG_MIPS_C_FIQ_HYP_CLR macro
305 #define REG_C_FIQ_HYP_CLR REG_MIPS_C_FIQ_HYP_CLR macro
328 #define REG_C_FIQ_HYP_CLR REG_MIPS_C_FIQ_HYP_CLR macro
352 #define REG_C_FIQ_HYP_CLR REG_MIPS_C_FIQ_HYP_CLR macro
H A DhalIRQ.c488 _IRQ_Write4Byte(REG_C_FIQ_HYP_CLR, status); in _HAL_IRQ_FIQHnd()
489 _IRQ_Write4Byte(REG_C_FIQ_HYP_CLR, 0); in _HAL_IRQ_FIQHnd()
/utopia/UTPA2-700.0.x/modules/irq/hal/manhattan/irq/
H A DregIRQ.h209 #define REG_C_FIQ_HYP_CLR REG_FRC_C_FIQ_HYP_CLR macro
230 #define REG_C_FIQ_HYP_CLR REG_AEON_C_FIQ_HYP_CLR macro
255 #define REG_C_FIQ_HYP_CLR REG_MIPS_C_FIQ_HYP_CLR macro
281 #define REG_C_FIQ_HYP_CLR REG_MIPS_C_FIQ_HYP_CLR macro
305 #define REG_C_FIQ_HYP_CLR REG_MIPS_C_FIQ_HYP_CLR macro
328 #define REG_C_FIQ_HYP_CLR REG_MIPS_C_FIQ_HYP_CLR macro
352 #define REG_C_FIQ_HYP_CLR REG_MIPS_C_FIQ_HYP_CLR macro
H A DhalIRQ.c484 _IRQ_Write4Byte(REG_C_FIQ_HYP_CLR, status); in _HAL_IRQ_FIQHnd()
485 _IRQ_Write4Byte(REG_C_FIQ_HYP_CLR, 0); in _HAL_IRQ_FIQHnd()
/utopia/UTPA2-700.0.x/modules/irq/hal/maxim/irq/
H A DregIRQ.h209 #define REG_C_FIQ_HYP_CLR REG_FRC_C_FIQ_HYP_CLR macro
230 #define REG_C_FIQ_HYP_CLR REG_AEON_C_FIQ_HYP_CLR macro
255 #define REG_C_FIQ_HYP_CLR REG_MIPS_C_FIQ_HYP_CLR macro
281 #define REG_C_FIQ_HYP_CLR REG_MIPS_C_FIQ_HYP_CLR macro
305 #define REG_C_FIQ_HYP_CLR REG_MIPS_C_FIQ_HYP_CLR macro
328 #define REG_C_FIQ_HYP_CLR REG_MIPS_C_FIQ_HYP_CLR macro
352 #define REG_C_FIQ_HYP_CLR REG_MIPS_C_FIQ_HYP_CLR macro
H A DhalIRQ.c488 _IRQ_Write4Byte(REG_C_FIQ_HYP_CLR, status); in _HAL_IRQ_FIQHnd()
489 _IRQ_Write4Byte(REG_C_FIQ_HYP_CLR, 0); in _HAL_IRQ_FIQHnd()
/utopia/UTPA2-700.0.x/modules/irq/hal/M7621/irq/
H A DregIRQ.h209 #define REG_C_FIQ_HYP_CLR REG_FRC_C_FIQ_HYP_CLR macro
230 #define REG_C_FIQ_HYP_CLR REG_AEON_C_FIQ_HYP_CLR macro
255 #define REG_C_FIQ_HYP_CLR REG_MIPS_C_FIQ_HYP_CLR macro
281 #define REG_C_FIQ_HYP_CLR REG_MIPS_C_FIQ_HYP_CLR macro
305 #define REG_C_FIQ_HYP_CLR REG_MIPS_C_FIQ_HYP_CLR macro
328 #define REG_C_FIQ_HYP_CLR REG_MIPS_C_FIQ_HYP_CLR macro
352 #define REG_C_FIQ_HYP_CLR REG_MIPS_C_FIQ_HYP_CLR macro
H A DhalIRQ.c488 _IRQ_Write4Byte(REG_C_FIQ_HYP_CLR, status); in _HAL_IRQ_FIQHnd()
489 _IRQ_Write4Byte(REG_C_FIQ_HYP_CLR, 0); in _HAL_IRQ_FIQHnd()
/utopia/UTPA2-700.0.x/modules/irq/hal/kano/irq/
H A DregIRQ.h167 #define REG_C_FIQ_HYP_CLR REG_AEON_C_FIQ_HYP_CLR macro
189 #define REG_C_FIQ_HYP_CLR REG_MIPS_C_FIQ_HYP_CLR macro
H A DhalIRQ.c463 _IRQ_Write4Byte(REG_C_FIQ_HYP_CLR, status); in _HAL_IRQ_FIQHnd()
464 _IRQ_Write4Byte(REG_C_FIQ_HYP_CLR, 0); in _HAL_IRQ_FIQHnd()
/utopia/UTPA2-700.0.x/modules/irq/hal/k7u/irq/
H A DregIRQ.h167 #define REG_C_FIQ_HYP_CLR REG_AEON_C_FIQ_HYP_CLR macro
189 #define REG_C_FIQ_HYP_CLR REG_MIPS_C_FIQ_HYP_CLR macro
H A DhalIRQ.c463 _IRQ_Write4Byte(REG_C_FIQ_HYP_CLR, status); in _HAL_IRQ_FIQHnd()
464 _IRQ_Write4Byte(REG_C_FIQ_HYP_CLR, 0); in _HAL_IRQ_FIQHnd()
/utopia/UTPA2-700.0.x/modules/irq/hal/k6lite/irq/
H A DregIRQ.h167 #define REG_C_FIQ_HYP_CLR REG_AEON_C_FIQ_HYP_CLR macro
189 #define REG_C_FIQ_HYP_CLR REG_MIPS_C_FIQ_HYP_CLR macro
H A DhalIRQ.c463 _IRQ_Write4Byte(REG_C_FIQ_HYP_CLR, status); in _HAL_IRQ_FIQHnd()
464 _IRQ_Write4Byte(REG_C_FIQ_HYP_CLR, 0); in _HAL_IRQ_FIQHnd()
/utopia/UTPA2-700.0.x/modules/irq/hal/curry/irq/
H A DregIRQ.h167 #define REG_C_FIQ_HYP_CLR REG_AEON_C_FIQ_HYP_CLR macro
189 #define REG_C_FIQ_HYP_CLR REG_MIPS_C_FIQ_HYP_CLR macro
H A DhalIRQ.c463 _IRQ_Write4Byte(REG_C_FIQ_HYP_CLR, status); in _HAL_IRQ_FIQHnd()
464 _IRQ_Write4Byte(REG_C_FIQ_HYP_CLR, 0); in _HAL_IRQ_FIQHnd()
/utopia/UTPA2-700.0.x/modules/irq/hal/k6/irq/
H A DregIRQ.h167 #define REG_C_FIQ_HYP_CLR REG_AEON_C_FIQ_HYP_CLR macro
189 #define REG_C_FIQ_HYP_CLR REG_MIPS_C_FIQ_HYP_CLR macro
H A DhalIRQ.c463 _IRQ_Write4Byte(REG_C_FIQ_HYP_CLR, status); in _HAL_IRQ_FIQHnd()
464 _IRQ_Write4Byte(REG_C_FIQ_HYP_CLR, 0); in _HAL_IRQ_FIQHnd()