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Searched refs:REG_C_FIQ_EXP_FINAL_STATUS (Results 1 – 25 of 32) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/irq/hal/M7821/irq/
H A DregIRQ.h206 #define REG_C_FIQ_EXP_FINAL_STATUS REG_FRC_C_FIQ_EXP_FINAL_STATUS macro
227 #define REG_C_FIQ_EXP_FINAL_STATUS REG_AEON_C_FIQ_EXP_FINAL_STATUS macro
252 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS macro
278 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS macro
302 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS macro
325 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS macro
349 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS macro
372 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS macro
H A DhalIRQ.c353 status = _IRQ_Read4Byte(REG_C_FIQ_EXP_FINAL_STATUS); in _HAL_IRQ_FIQHnd_ARM()
466 status = _IRQ_Read4Byte(REG_C_FIQ_EXP_FINAL_STATUS); in _HAL_IRQ_FIQHnd()
/utopia/UTPA2-700.0.x/modules/irq/hal/macan/irq/
H A DregIRQ.h206 #define REG_C_FIQ_EXP_FINAL_STATUS REG_FRC_C_FIQ_EXP_FINAL_STATUS macro
227 #define REG_C_FIQ_EXP_FINAL_STATUS REG_AEON_C_FIQ_EXP_FINAL_STATUS macro
252 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS macro
278 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS macro
302 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS macro
325 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS macro
349 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS macro
372 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS macro
H A DhalIRQ.c347 status = _IRQ_Read4Byte(REG_C_FIQ_EXP_FINAL_STATUS); in _HAL_IRQ_FIQHnd_ARM()
460 status = _IRQ_Read4Byte(REG_C_FIQ_EXP_FINAL_STATUS); in _HAL_IRQ_FIQHnd()
/utopia/UTPA2-700.0.x/modules/irq/hal/maserati/irq/
H A DregIRQ.h206 #define REG_C_FIQ_EXP_FINAL_STATUS REG_FRC_C_FIQ_EXP_FINAL_STATUS macro
227 #define REG_C_FIQ_EXP_FINAL_STATUS REG_AEON_C_FIQ_EXP_FINAL_STATUS macro
252 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS macro
278 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS macro
302 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS macro
325 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS macro
349 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS macro
/utopia/UTPA2-700.0.x/modules/irq/hal/manhattan/irq/
H A DregIRQ.h206 #define REG_C_FIQ_EXP_FINAL_STATUS REG_FRC_C_FIQ_EXP_FINAL_STATUS macro
227 #define REG_C_FIQ_EXP_FINAL_STATUS REG_AEON_C_FIQ_EXP_FINAL_STATUS macro
252 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS macro
278 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS macro
302 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS macro
325 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS macro
349 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS macro
/utopia/UTPA2-700.0.x/modules/irq/hal/maxim/irq/
H A DregIRQ.h206 #define REG_C_FIQ_EXP_FINAL_STATUS REG_FRC_C_FIQ_EXP_FINAL_STATUS macro
227 #define REG_C_FIQ_EXP_FINAL_STATUS REG_AEON_C_FIQ_EXP_FINAL_STATUS macro
252 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS macro
278 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS macro
302 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS macro
325 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS macro
349 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS macro
H A DhalIRQ.c351 status = _IRQ_Read4Byte(REG_C_FIQ_EXP_FINAL_STATUS); in _HAL_IRQ_FIQHnd_ARM()
464 status = _IRQ_Read4Byte(REG_C_FIQ_EXP_FINAL_STATUS); in _HAL_IRQ_FIQHnd()
/utopia/UTPA2-700.0.x/modules/irq/hal/M7621/irq/
H A DregIRQ.h206 #define REG_C_FIQ_EXP_FINAL_STATUS REG_FRC_C_FIQ_EXP_FINAL_STATUS macro
227 #define REG_C_FIQ_EXP_FINAL_STATUS REG_AEON_C_FIQ_EXP_FINAL_STATUS macro
252 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS macro
278 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS macro
302 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS macro
325 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS macro
349 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS macro
H A DhalIRQ.c351 status = _IRQ_Read4Byte(REG_C_FIQ_EXP_FINAL_STATUS); in _HAL_IRQ_FIQHnd_ARM()
464 status = _IRQ_Read4Byte(REG_C_FIQ_EXP_FINAL_STATUS); in _HAL_IRQ_FIQHnd()
/utopia/UTPA2-700.0.x/modules/irq/hal/mustang/irq/
H A DregIRQ.h160 #define REG_C_FIQ_EXP_FINAL_STATUS REG_AEON_C_FIQ_EXP_FINAL_STATUS macro
177 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS macro
195 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS macro
211 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS macro
227 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS macro
/utopia/UTPA2-700.0.x/modules/irq/hal/maldives/irq/
H A DregIRQ.h160 #define REG_C_FIQ_EXP_FINAL_STATUS REG_AEON_C_FIQ_EXP_FINAL_STATUS macro
177 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS macro
195 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS macro
211 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS macro
227 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS macro
/utopia/UTPA2-700.0.x/modules/irq/hal/mainz/irq/
H A DregIRQ.h151 #define REG_C_FIQ_EXP_FINAL_STATUS REG_AEON_C_FIQ_EXP_FINAL_STATUS macro
167 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS macro
/utopia/UTPA2-700.0.x/modules/irq/hal/mooney/irq/
H A DregIRQ.h151 #define REG_C_FIQ_EXP_FINAL_STATUS REG_AEON_C_FIQ_EXP_FINAL_STATUS macro
167 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS macro
/utopia/UTPA2-700.0.x/modules/irq/hal/messi/irq/
H A DregIRQ.h151 #define REG_C_FIQ_EXP_FINAL_STATUS REG_AEON_C_FIQ_EXP_FINAL_STATUS macro
167 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS macro
/utopia/UTPA2-700.0.x/modules/irq/hal/kano/irq/
H A DregIRQ.h164 #define REG_C_FIQ_EXP_FINAL_STATUS REG_AEON_C_FIQ_EXP_FINAL_STATUS macro
186 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS macro
H A DhalIRQ.c348 status = _IRQ_Read4Byte(REG_C_FIQ_EXP_FINAL_STATUS); in _HAL_IRQ_FIQHnd_ARM()
439 status = _IRQ_Read4Byte(REG_C_FIQ_EXP_FINAL_STATUS); in _HAL_IRQ_FIQHnd()
/utopia/UTPA2-700.0.x/modules/irq/hal/k7u/irq/
H A DregIRQ.h164 #define REG_C_FIQ_EXP_FINAL_STATUS REG_AEON_C_FIQ_EXP_FINAL_STATUS macro
186 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS macro
H A DhalIRQ.c348 status = _IRQ_Read4Byte(REG_C_FIQ_EXP_FINAL_STATUS); in _HAL_IRQ_FIQHnd_ARM()
439 status = _IRQ_Read4Byte(REG_C_FIQ_EXP_FINAL_STATUS); in _HAL_IRQ_FIQHnd()
/utopia/UTPA2-700.0.x/modules/irq/hal/k6lite/irq/
H A DregIRQ.h164 #define REG_C_FIQ_EXP_FINAL_STATUS REG_AEON_C_FIQ_EXP_FINAL_STATUS macro
186 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS macro
H A DhalIRQ.c348 status = _IRQ_Read4Byte(REG_C_FIQ_EXP_FINAL_STATUS); in _HAL_IRQ_FIQHnd_ARM()
439 status = _IRQ_Read4Byte(REG_C_FIQ_EXP_FINAL_STATUS); in _HAL_IRQ_FIQHnd()
/utopia/UTPA2-700.0.x/modules/irq/hal/curry/irq/
H A DregIRQ.h164 #define REG_C_FIQ_EXP_FINAL_STATUS REG_AEON_C_FIQ_EXP_FINAL_STATUS macro
186 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS macro
H A DhalIRQ.c348 status = _IRQ_Read4Byte(REG_C_FIQ_EXP_FINAL_STATUS); in _HAL_IRQ_FIQHnd_ARM()
439 status = _IRQ_Read4Byte(REG_C_FIQ_EXP_FINAL_STATUS); in _HAL_IRQ_FIQHnd()
/utopia/UTPA2-700.0.x/modules/irq/hal/k6/irq/
H A DregIRQ.h164 #define REG_C_FIQ_EXP_FINAL_STATUS REG_AEON_C_FIQ_EXP_FINAL_STATUS macro
186 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS macro
H A DhalIRQ.c348 status = _IRQ_Read4Byte(REG_C_FIQ_EXP_FINAL_STATUS); in _HAL_IRQ_FIQHnd_ARM()
439 status = _IRQ_Read4Byte(REG_C_FIQ_EXP_FINAL_STATUS); in _HAL_IRQ_FIQHnd()

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