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Searched refs:REG_C_FIQ_EXP_CLR (Results 1 – 25 of 32) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/irq/hal/M7821/irq/
H A DregIRQ.h205 #define REG_C_FIQ_EXP_CLR REG_FRC_C_FIQ_EXP_CLR macro
226 #define REG_C_FIQ_EXP_CLR REG_AEON_C_FIQ_EXP_CLR macro
251 #define REG_C_FIQ_EXP_CLR REG_MIPS_C_FIQ_EXP_CLR macro
277 #define REG_C_FIQ_EXP_CLR REG_MIPS_C_FIQ_EXP_CLR macro
301 #define REG_C_FIQ_EXP_CLR REG_MIPS_C_FIQ_EXP_CLR macro
324 #define REG_C_FIQ_EXP_CLR REG_MIPS_C_FIQ_EXP_CLR macro
348 #define REG_C_FIQ_EXP_CLR REG_MIPS_C_FIQ_EXP_CLR macro
371 #define REG_C_FIQ_EXP_CLR REG_MIPS_C_FIQ_EXP_CLR macro
H A DhalIRQ.c358 _IRQ_Write4Byte(REG_C_FIQ_EXP_CLR, status); in _HAL_IRQ_FIQHnd_ARM()
359 _IRQ_Write4Byte(REG_C_FIQ_EXP_CLR, 0); in _HAL_IRQ_FIQHnd_ARM()
471 _IRQ_Write4Byte(REG_C_FIQ_EXP_CLR, status); in _HAL_IRQ_FIQHnd()
472 _IRQ_Write4Byte(REG_C_FIQ_EXP_CLR, 0); in _HAL_IRQ_FIQHnd()
/utopia/UTPA2-700.0.x/modules/irq/hal/macan/irq/
H A DregIRQ.h205 #define REG_C_FIQ_EXP_CLR REG_FRC_C_FIQ_EXP_CLR macro
226 #define REG_C_FIQ_EXP_CLR REG_AEON_C_FIQ_EXP_CLR macro
251 #define REG_C_FIQ_EXP_CLR REG_MIPS_C_FIQ_EXP_CLR macro
277 #define REG_C_FIQ_EXP_CLR REG_MIPS_C_FIQ_EXP_CLR macro
301 #define REG_C_FIQ_EXP_CLR REG_MIPS_C_FIQ_EXP_CLR macro
324 #define REG_C_FIQ_EXP_CLR REG_MIPS_C_FIQ_EXP_CLR macro
348 #define REG_C_FIQ_EXP_CLR REG_MIPS_C_FIQ_EXP_CLR macro
371 #define REG_C_FIQ_EXP_CLR REG_MIPS_C_FIQ_EXP_CLR macro
H A DhalIRQ.c352 _IRQ_Write4Byte(REG_C_FIQ_EXP_CLR, status); in _HAL_IRQ_FIQHnd_ARM()
353 _IRQ_Write4Byte(REG_C_FIQ_EXP_CLR, 0); in _HAL_IRQ_FIQHnd_ARM()
465 _IRQ_Write4Byte(REG_C_FIQ_EXP_CLR, status); in _HAL_IRQ_FIQHnd()
466 _IRQ_Write4Byte(REG_C_FIQ_EXP_CLR, 0); in _HAL_IRQ_FIQHnd()
/utopia/UTPA2-700.0.x/modules/irq/hal/maserati/irq/
H A DregIRQ.h205 #define REG_C_FIQ_EXP_CLR REG_FRC_C_FIQ_EXP_CLR macro
226 #define REG_C_FIQ_EXP_CLR REG_AEON_C_FIQ_EXP_CLR macro
251 #define REG_C_FIQ_EXP_CLR REG_MIPS_C_FIQ_EXP_CLR macro
277 #define REG_C_FIQ_EXP_CLR REG_MIPS_C_FIQ_EXP_CLR macro
301 #define REG_C_FIQ_EXP_CLR REG_MIPS_C_FIQ_EXP_CLR macro
324 #define REG_C_FIQ_EXP_CLR REG_MIPS_C_FIQ_EXP_CLR macro
348 #define REG_C_FIQ_EXP_CLR REG_MIPS_C_FIQ_EXP_CLR macro
H A DhalIRQ.c356 _IRQ_Write4Byte(REG_C_FIQ_EXP_CLR, status); in _HAL_IRQ_FIQHnd_ARM()
357 _IRQ_Write4Byte(REG_C_FIQ_EXP_CLR, 0); in _HAL_IRQ_FIQHnd_ARM()
469 _IRQ_Write4Byte(REG_C_FIQ_EXP_CLR, status); in _HAL_IRQ_FIQHnd()
470 _IRQ_Write4Byte(REG_C_FIQ_EXP_CLR, 0); in _HAL_IRQ_FIQHnd()
/utopia/UTPA2-700.0.x/modules/irq/hal/manhattan/irq/
H A DregIRQ.h205 #define REG_C_FIQ_EXP_CLR REG_FRC_C_FIQ_EXP_CLR macro
226 #define REG_C_FIQ_EXP_CLR REG_AEON_C_FIQ_EXP_CLR macro
251 #define REG_C_FIQ_EXP_CLR REG_MIPS_C_FIQ_EXP_CLR macro
277 #define REG_C_FIQ_EXP_CLR REG_MIPS_C_FIQ_EXP_CLR macro
301 #define REG_C_FIQ_EXP_CLR REG_MIPS_C_FIQ_EXP_CLR macro
324 #define REG_C_FIQ_EXP_CLR REG_MIPS_C_FIQ_EXP_CLR macro
348 #define REG_C_FIQ_EXP_CLR REG_MIPS_C_FIQ_EXP_CLR macro
H A DhalIRQ.c352 _IRQ_Write4Byte(REG_C_FIQ_EXP_CLR, status); in _HAL_IRQ_FIQHnd_ARM()
353 _IRQ_Write4Byte(REG_C_FIQ_EXP_CLR, 0); in _HAL_IRQ_FIQHnd_ARM()
465 _IRQ_Write4Byte(REG_C_FIQ_EXP_CLR, status); in _HAL_IRQ_FIQHnd()
466 _IRQ_Write4Byte(REG_C_FIQ_EXP_CLR, 0); in _HAL_IRQ_FIQHnd()
/utopia/UTPA2-700.0.x/modules/irq/hal/maxim/irq/
H A DregIRQ.h205 #define REG_C_FIQ_EXP_CLR REG_FRC_C_FIQ_EXP_CLR macro
226 #define REG_C_FIQ_EXP_CLR REG_AEON_C_FIQ_EXP_CLR macro
251 #define REG_C_FIQ_EXP_CLR REG_MIPS_C_FIQ_EXP_CLR macro
277 #define REG_C_FIQ_EXP_CLR REG_MIPS_C_FIQ_EXP_CLR macro
301 #define REG_C_FIQ_EXP_CLR REG_MIPS_C_FIQ_EXP_CLR macro
324 #define REG_C_FIQ_EXP_CLR REG_MIPS_C_FIQ_EXP_CLR macro
348 #define REG_C_FIQ_EXP_CLR REG_MIPS_C_FIQ_EXP_CLR macro
H A DhalIRQ.c356 _IRQ_Write4Byte(REG_C_FIQ_EXP_CLR, status); in _HAL_IRQ_FIQHnd_ARM()
357 _IRQ_Write4Byte(REG_C_FIQ_EXP_CLR, 0); in _HAL_IRQ_FIQHnd_ARM()
469 _IRQ_Write4Byte(REG_C_FIQ_EXP_CLR, status); in _HAL_IRQ_FIQHnd()
470 _IRQ_Write4Byte(REG_C_FIQ_EXP_CLR, 0); in _HAL_IRQ_FIQHnd()
/utopia/UTPA2-700.0.x/modules/irq/hal/M7621/irq/
H A DregIRQ.h205 #define REG_C_FIQ_EXP_CLR REG_FRC_C_FIQ_EXP_CLR macro
226 #define REG_C_FIQ_EXP_CLR REG_AEON_C_FIQ_EXP_CLR macro
251 #define REG_C_FIQ_EXP_CLR REG_MIPS_C_FIQ_EXP_CLR macro
277 #define REG_C_FIQ_EXP_CLR REG_MIPS_C_FIQ_EXP_CLR macro
301 #define REG_C_FIQ_EXP_CLR REG_MIPS_C_FIQ_EXP_CLR macro
324 #define REG_C_FIQ_EXP_CLR REG_MIPS_C_FIQ_EXP_CLR macro
348 #define REG_C_FIQ_EXP_CLR REG_MIPS_C_FIQ_EXP_CLR macro
H A DhalIRQ.c356 _IRQ_Write4Byte(REG_C_FIQ_EXP_CLR, status); in _HAL_IRQ_FIQHnd_ARM()
357 _IRQ_Write4Byte(REG_C_FIQ_EXP_CLR, 0); in _HAL_IRQ_FIQHnd_ARM()
469 _IRQ_Write4Byte(REG_C_FIQ_EXP_CLR, status); in _HAL_IRQ_FIQHnd()
470 _IRQ_Write4Byte(REG_C_FIQ_EXP_CLR, 0); in _HAL_IRQ_FIQHnd()
/utopia/UTPA2-700.0.x/modules/irq/hal/mustang/irq/
H A DregIRQ.h159 #define REG_C_FIQ_EXP_CLR REG_AEON_C_FIQ_EXP_CLR macro
176 #define REG_C_FIQ_EXP_CLR REG_MIPS_C_FIQ_EXP_CLR macro
194 #define REG_C_FIQ_EXP_CLR REG_MIPS_C_FIQ_EXP_CLR macro
210 #define REG_C_FIQ_EXP_CLR REG_MIPS_C_FIQ_EXP_CLR macro
226 #define REG_C_FIQ_EXP_CLR REG_MIPS_C_FIQ_EXP_CLR macro
/utopia/UTPA2-700.0.x/modules/irq/hal/maldives/irq/
H A DregIRQ.h159 #define REG_C_FIQ_EXP_CLR REG_AEON_C_FIQ_EXP_CLR macro
176 #define REG_C_FIQ_EXP_CLR REG_MIPS_C_FIQ_EXP_CLR macro
194 #define REG_C_FIQ_EXP_CLR REG_MIPS_C_FIQ_EXP_CLR macro
210 #define REG_C_FIQ_EXP_CLR REG_MIPS_C_FIQ_EXP_CLR macro
226 #define REG_C_FIQ_EXP_CLR REG_MIPS_C_FIQ_EXP_CLR macro
/utopia/UTPA2-700.0.x/modules/irq/hal/k6/irq/
H A DhalIRQ.c353 _IRQ_Write4Byte(REG_C_FIQ_EXP_CLR, status); in _HAL_IRQ_FIQHnd_ARM()
354 _IRQ_Write4Byte(REG_C_FIQ_EXP_CLR, 0); in _HAL_IRQ_FIQHnd_ARM()
444 _IRQ_Write4Byte(REG_C_FIQ_EXP_CLR, status); in _HAL_IRQ_FIQHnd()
445 _IRQ_Write4Byte(REG_C_FIQ_EXP_CLR, 0); in _HAL_IRQ_FIQHnd()
/utopia/UTPA2-700.0.x/modules/irq/hal/k6lite/irq/
H A DhalIRQ.c353 _IRQ_Write4Byte(REG_C_FIQ_EXP_CLR, status); in _HAL_IRQ_FIQHnd_ARM()
354 _IRQ_Write4Byte(REG_C_FIQ_EXP_CLR, 0); in _HAL_IRQ_FIQHnd_ARM()
444 _IRQ_Write4Byte(REG_C_FIQ_EXP_CLR, status); in _HAL_IRQ_FIQHnd()
445 _IRQ_Write4Byte(REG_C_FIQ_EXP_CLR, 0); in _HAL_IRQ_FIQHnd()
H A DregIRQ.h163 #define REG_C_FIQ_EXP_CLR REG_AEON_C_FIQ_EXP_CLR macro
185 #define REG_C_FIQ_EXP_CLR REG_MIPS_C_FIQ_EXP_CLR macro
/utopia/UTPA2-700.0.x/modules/irq/hal/kano/irq/
H A DhalIRQ.c353 _IRQ_Write4Byte(REG_C_FIQ_EXP_CLR, status); in _HAL_IRQ_FIQHnd_ARM()
354 _IRQ_Write4Byte(REG_C_FIQ_EXP_CLR, 0); in _HAL_IRQ_FIQHnd_ARM()
444 _IRQ_Write4Byte(REG_C_FIQ_EXP_CLR, status); in _HAL_IRQ_FIQHnd()
445 _IRQ_Write4Byte(REG_C_FIQ_EXP_CLR, 0); in _HAL_IRQ_FIQHnd()
H A DregIRQ.h163 #define REG_C_FIQ_EXP_CLR REG_AEON_C_FIQ_EXP_CLR macro
185 #define REG_C_FIQ_EXP_CLR REG_MIPS_C_FIQ_EXP_CLR macro
/utopia/UTPA2-700.0.x/modules/irq/hal/k7u/irq/
H A DhalIRQ.c353 _IRQ_Write4Byte(REG_C_FIQ_EXP_CLR, status); in _HAL_IRQ_FIQHnd_ARM()
354 _IRQ_Write4Byte(REG_C_FIQ_EXP_CLR, 0); in _HAL_IRQ_FIQHnd_ARM()
444 _IRQ_Write4Byte(REG_C_FIQ_EXP_CLR, status); in _HAL_IRQ_FIQHnd()
445 _IRQ_Write4Byte(REG_C_FIQ_EXP_CLR, 0); in _HAL_IRQ_FIQHnd()
H A DregIRQ.h163 #define REG_C_FIQ_EXP_CLR REG_AEON_C_FIQ_EXP_CLR macro
185 #define REG_C_FIQ_EXP_CLR REG_MIPS_C_FIQ_EXP_CLR macro
/utopia/UTPA2-700.0.x/modules/irq/hal/curry/irq/
H A DhalIRQ.c353 _IRQ_Write4Byte(REG_C_FIQ_EXP_CLR, status); in _HAL_IRQ_FIQHnd_ARM()
354 _IRQ_Write4Byte(REG_C_FIQ_EXP_CLR, 0); in _HAL_IRQ_FIQHnd_ARM()
444 _IRQ_Write4Byte(REG_C_FIQ_EXP_CLR, status); in _HAL_IRQ_FIQHnd()
445 _IRQ_Write4Byte(REG_C_FIQ_EXP_CLR, 0); in _HAL_IRQ_FIQHnd()
/utopia/UTPA2-700.0.x/modules/irq/hal/mainz/irq/
H A DregIRQ.h150 #define REG_C_FIQ_EXP_CLR REG_AEON_C_FIQ_EXP_CLR macro
166 #define REG_C_FIQ_EXP_CLR REG_MIPS_C_FIQ_EXP_CLR macro
/utopia/UTPA2-700.0.x/modules/irq/hal/mooney/irq/
H A DregIRQ.h150 #define REG_C_FIQ_EXP_CLR REG_AEON_C_FIQ_EXP_CLR macro
166 #define REG_C_FIQ_EXP_CLR REG_MIPS_C_FIQ_EXP_CLR macro
/utopia/UTPA2-700.0.x/modules/irq/hal/messi/irq/
H A DregIRQ.h150 #define REG_C_FIQ_EXP_CLR REG_AEON_C_FIQ_EXP_CLR macro
166 #define REG_C_FIQ_EXP_CLR REG_MIPS_C_FIQ_EXP_CLR macro

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