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Searched refs:REG_BDMA_SRC_SEL (Results 1 – 10 of 10) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6/ca2/
H A DregCA.h185 #define REG_BDMA_SRC_SEL (REG_BDMA_BASE + 0x2*4) macro
H A DhalCA.c1026 REG32(REG_BDMA_SRC_SEL) = 0x0940; //MIU0 to Sec_51 in HAL_CA_BGC_LoadFW()
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k7u/ca2/
H A DregCA.h185 #define REG_BDMA_SRC_SEL (REG_BDMA_BASE + 0x2*4) macro
H A DhalCA.c1023 REG32(REG_BDMA_SRC_SEL) = 0x0940; //MIU0 to Sec_51 in HAL_CA_BGC_LoadFW()
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6lite/ca2/
H A DregCA.h185 #define REG_BDMA_SRC_SEL (REG_BDMA_BASE + 0x2*4) macro
H A DhalCA.c1019 REG32(REG_BDMA_SRC_SEL) = 0x0940; //MIU0 to Sec_51 in HAL_CA_BGC_LoadFW()
/utopia/UTPA2-700.0.x/modules/dscmb/hal/curry/ca2/
H A DregCA.h185 #define REG_BDMA_SRC_SEL (REG_BDMA_BASE + 0x2*4) macro
H A DhalCA.c1020 REG32(REG_BDMA_SRC_SEL) = 0x0940; //MIU0 to Sec_51 in HAL_CA_BGC_LoadFW()
/utopia/UTPA2-700.0.x/modules/dscmb/hal/kano/ca2/
H A DregCA.h185 #define REG_BDMA_SRC_SEL (REG_BDMA_BASE + 0x2*4) macro
H A DhalCA.c1023 REG32(REG_BDMA_SRC_SEL) = 0x0940; //MIU0 to Sec_51 in HAL_CA_BGC_LoadFW()