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77 //<MStar Software>
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93 ////////////////////////////////////////////////////////////////////////////////
94
95 ////////////////////////////////////////////////////////////////////////////////////////////////////
96 // file halCA.c
97 // @brief CA HAL
98 // @author MStar Semiconductor,Inc.
99 ////////////////////////////////////////////////////////////////////////////////////////////////////
100 #ifdef MSOS_TYPE_LINUX_KERNEL
101 #include <linux/string.h>
102 #else
103 #include "string.h"
104 #endif
105
106 #include "MsCommon.h"
107 #include "regCA.h"
108 #include "drvCA.h"
109 #include "halCA.h"
110
111 #include <drvSYS.h>
112
113 // #undef MS_DEBUG_MSG
114 // #define MS_DEBUG_MSG(x) x
115
116 //--------------------------------------------------------------------------------------------------
117 // Driver Compiler Option
118 //--------------------------------------------------------------------------------------------------
119
120 //--------------------------------------------------------------------------------------------------
121 // Global Definition
122 //--------------------------------------------------------------------------------------------------
123 #define MAX_RESERVED_SIZE 128
124
125 //--------------------------------------------------------------------------------------------------
126 // CA Hardware Abstraction Layer
127 //--------------------------------------------------------------------------------------------------
128 static MS_VIRT _u32REGBase = 0;
129 static MS_VIRT _u32REGPMBase = 0;
130 static MS_VIRT _u32REG_OTP_Base = 0;
131 static MS_VIRT _u32REG_RSA_Base = 0;
132
133 #define REG16(addr) (*(volatile unsigned short *)(_u32REGBase + (addr)))
134 #define REG16_WRITE(addr, value, mask) do { REG16(addr) = (REG16(addr) & ~(mask)) | ((value) & (mask)); } while(0)
135
136 #define REG32(addr) (*(volatile unsigned *)(_u32REGBase + (addr)))
137 #define REG32_WRITE(addr, value, mask) do { REG32(addr) = (REG32(addr) & ~(mask)) | ((value) & (mask)); } while(0)
138
139 #define REG32_PM(addr) (*(volatile unsigned *)(_u32REGPMBase + (addr)))
140 #define REG16_PM(addr) (*(volatile unsigned short *)(_u32REGPMBase + (addr)))
141
142 #ifdef CA_NO_PRINTF
143 #define HAL_CA_DEBUG(fmt, args...)
144 #else
145 #define HAL_CA_DEBUG(fmt, args...) do{ \
146 printf("[%s][%d]"fmt"\n", __FUNCTION__, __LINE__, ## args);}\
147 while(0)
148 #endif
bitmask(unsigned hi,unsigned lo)149 static unsigned bitmask(unsigned hi, unsigned lo)
150 {
151 unsigned x, s = hi - lo + 1;
152 // printf("hi=%d lo=%d size=%d\n", hi, lo, s);
153
154 if(s >= sizeof(unsigned) * 8)
155 x = (unsigned)-1;
156 else
157 x = (1U << s) - 1;
158 return x << lo;
159 }
160
161 struct {
162 MS_U32 u32Addr;
163 MS_U32 u32Hi;
164 MS_U32 u32Lo;
165 } _HAL_CA_OTP_Addr[] = {
166 //Parse from otp mapping
167 [U_OTP_CA_reserved0] = {0x003500, 255, 0},
168 [U_OTP_CA_reserved1] = {0x003520, 255, 0},
169 [U_OTP_CA_reserved2] = {0x003540, 255, 0},
170 [U_OTP_CA_reserved3] = {0x003560, 255, 0},
171 [U_OTP_CA_reserved4] = {0x003580, 255, 0},
172 [U_OTP_CA_reserved5] = {0x0035A0, 255, 0},
173 [U_OTP_CA_reserved6] = {0x0035C0, 255, 0},
174 [U_OTP_CA_reserved7] = {0x0035E0, 255, 0},
175 [U_OTP_CA_reserved8] = {0x003600, 255, 0},
176 [U_OTP_CA_reserved9] = {0x003620, 255, 0},
177 [U_OTP_CA_reserved10] = {0x003640, 255, 0},
178 [U_OTP_CA_reserved11] = {0x003660, 255, 0},
179 [U_OTP_CA_reserved12] = {0x003680, 255, 0},
180 [U_OTP_CA_reserved13] = {0x0036A0, 255, 0},
181 [U_OTP_CA_reserved14] = {0x0036C0, 255, 0},
182 [U_OTP_CA_reserved15] = {0x0036E0, 255, 0},
183 [U_OTP_Chip_Extension_ID] = {0x003700, 127, 0},
184 [U_OTP_PVConfiguration] = {0x003710, 23, 0},
185 [U_OTP_EncryptLoader_Key_sel] = {0x003710, 27, 24},
186 [U_OTP_EncryptLoader_KL_level] = {0x003710, 29, 28},
187 [U_OTP_SW_Reserved0] = {0x003710, 31, 30},
188 [U_OTP_EncryptLoader_ForceEnc] = {0x003714, 1, 0},
189 [U_OTP_SW_Reserved1] = {0x003714, 31, 2},
190 [U_OTP_HASH0_VER_REF] = {0x003718, 31, 0},
191 [U_OTP_HASH1_VER_REF] = {0x00371C, 31, 0},
192 [U_OTP_HASH2_VER_REF] = {0x003720, 31, 0},
193 [U_OTP_SW_Reserved2] = {0x003724, 31, 0},
194 [U_OTP_Versioning] = {0x003728, 511, 0},
195 [U_OTP_Preenablement_0] = {0x003768, 31, 0},
196 [U_OTP_Preenablement_1] = {0x00376C, 31, 0},
197 [U_OTP_Preenablement_2] = {0x003770, 31, 0},
198 [U_OTP_Preenablement_3] = {0x003774, 31, 0},
199 [U_OTP_Preenablement_4] = {0x003778, 31, 0},
200 [U_OTP_Preenablement_5] = {0x00377C, 31, 0},
201 [U_OTP_Preenablement_6] = {0x003780, 31, 0},
202 [U_OTP_Preenablement_7] = {0x003784, 31, 0},
203 [U_OTP_CAdata_0] = {0x003788, 31, 0},
204 [U_OTP_CAdata_1] = {0x00378C, 31, 0},
205 [U_OTP_CAdata_2] = {0x003790, 31, 0},
206 [U_OTP_CAdata_3] = {0x003794, 31, 0},
207 [U_OTP_CAdata_4] = {0x003798, 31, 0},
208 [U_OTP_CAdata_5] = {0x00379C, 31, 0},
209 [U_OTP_CAdata_6] = {0x0037A0, 31, 0},
210 [U_OTP_CAdata_7] = {0x0037A4, 31, 0},
211 [U_OTP_CAdata_8] = {0x0037A8, 31, 0},
212 [U_OTP_CAdata_9] = {0x0037AC, 31, 0},
213 [U_OTP_CAdata_10] = {0x0037B0, 31, 0},
214 [U_OTP_CAdata_11] = {0x0037B4, 31, 0},
215 [U_OTP_CAdata_12] = {0x0037B8, 31, 0},
216 [U_OTP_CAdata_13] = {0x0037BC, 31, 0},
217 [U_OTP_CAdata_14] = {0x0037C0, 31, 0},
218 [U_OTP_CAdata_15] = {0x0037C4, 31, 0},
219 [U_OTP_CAdata_16] = {0x0037C8, 31, 0},
220 [U_OTP_CAdata_17] = {0x0037CC, 31, 0},
221 [U_OTP_CAdata_18] = {0x0037D0, 31, 0},
222 [U_OTP_CAdata_19] = {0x0037D4, 31, 0},
223 [U_OTP_CAdata_20] = {0x0037D8, 31, 0},
224 [U_OTP_CAdata_21] = {0x0037DC, 31, 0},
225 [U_OTP_CAdata_22] = {0x0037E0, 31, 0},
226 [U_OTP_CAdata_23] = {0x0037E4, 31, 0},
227 [U_OTP_CAdata_24] = {0x0037E8, 31, 0},
228 [U_OTP_CAdata_25] = {0x0037EC, 31, 0},
229 [U_OTP_CAdata_26] = {0x0037F0, 31, 0},
230 [U_OTP_CAdata_27] = {0x0037F4, 31, 0},
231 [U_OTP_CAdata_28] = {0x0037F8, 31, 0},
232 [U_OTP_CAdata_29] = {0x0037FC, 31, 0},
233 [U_OTP_CAdata_30] = {0x003800, 31, 0},
234 [U_OTP_CAdata_31] = {0x003804, 31, 0},
235 [U_OTP_CAdata_32] = {0x003808, 31, 0},
236 [U_OTP_CAdata_33] = {0x00380C, 31, 0},
237 [U_OTP_CAdata_34] = {0x003810, 31, 0},
238 [U_OTP_CAdata_35] = {0x003814, 31, 0},
239 [U_OTP_CAdata_36] = {0x003818, 31, 0},
240 [U_OTP_CAdata_37] = {0x00381C, 31, 0},
241 [U_OTP_forbid_SCPU2DRAM] = {0x003820, 3, 0},
242 [U_OTP_forbid_SCPUQMEM_to_DRAM] = {0x003820, 7, 4},
243 [U_OTP_forbid_CryptoDMA_keyslot_QMEM] = {0x003820, 11, 8},
244 [U_OTP_forbid_SCPU2UART] = {0x003820, 15, 12},
245 [U_OTP_IXSC_config1] = {0x003820, 19, 16},
246 [U_OTP_IXSC_config2] = {0x003820, 23, 20},
247 [U_OTP_IXSC_config3] = {0x003820, 27, 24},
248 [U_OTP_IXSC_config4] = {0x003820, 31, 28},
249 [U_OTP_LockWord_Preenablement_0_W] = {0x003824, 1, 0},
250 [U_OTP_LockWord_Preenablement_1_W] = {0x003824, 3, 2},
251 [U_OTP_LockWord_Preenablement_2_W] = {0x003824, 5, 4},
252 [U_OTP_LockWord_Preenablement_3_W] = {0x003824, 7, 6},
253 [U_OTP_LockWord_Preenablement_4_W] = {0x003824, 9, 8},
254 [U_OTP_LockWord_Preenablement_5_W] = {0x003824, 11, 10},
255 [U_OTP_LockWord_Preenablement_6_W] = {0x003824, 13, 12},
256 [U_OTP_LockWord_Preenablement_7_W] = {0x003824, 15, 14},
257 [U_OTP_Test_Switch] = {0x003824, 23, 16},
258 [U_OTP_IXSC_Reserved0] = {0x003824, 31, 24},
259 [U_OTP_NOCS3_00] = {0x003828, 383, 0},
260 [U_OTP_NOCS3_01] = {0x003858, 383, 0},
261 [U_OTP_NOCS3_02] = {0x003888, 127, 0},
262 [U_OTP_NOCS3_03] = {0x003898, 127, 0},
263 [U_OTP_MSID] = {0x0038A8, 31, 0},
264 [U_OTP_CFG_STB_CA_SN] = {0x0038AC, 31, 0},
265 [U_OTP_RSA_0] = {0x0039B0, 2047, 0},
266 [U_OTP_RSA_1] = {0x003628, 2047, 0},
267 [U_OTP_RSA_0_integrity_chk] = {0x003AB0, 1, 0},
268 [U_OTP_RSA_1_integrity_chk] = {0x003AB0, 3, 2},
269 [U_OTP_ena_ACPUUseHWRSAKey] = {0x003AB0, 7, 4},
270 [U_OTP_forbid_ACPUReadRSAKey0] = {0x003AB0, 10, 8},
271 [U_OTP_forbid_ACPUReadRSAKey1] = {0x003AB0, 13, 11},
272 [U_OTP_forbid_ACPUWrite_Versioning] = {0x003AB0, 15, 14},
273 [U_OTP_forbid_ACPURead_Versioning] = {0x003AB0, 17, 16},
274 [U_OTP_RSA_Reserved0] = {0x003AB0, 31, 18},
275 [U_OTP_RSA_0_CRC] = {0x003AB4, 15, 0},
276 [U_OTP_RSA_1_CRC] = {0x003AB4, 31, 16},
277 [U_OTP_PGMask0] = {0x003AB8, 31, 0},
278 [U_OTP_PGMask1] = {0x003ABC, 31, 0},
279 [U_OTP_PGMask2] = {0x003AC0, 31, 0},
280 [U_OTP_PGMask3] = {0x003AC4, 31, 0},
281 [U_OTP_PGMask4] = {0x003AC8, 31, 0},
282 [U_OTP_PGMask5] = {0x003ACC, 31, 0},
283 [U_OTP_PGMask6] = {0x003AD0, 31, 0},
284 [U_OTP_PGMask7] = {0x003AD4, 31, 0},
285 [U_OTP_PGMask8] = {0x003AD8, 31, 0},
286 [U_OTP_PGMask9] = {0x003ADC, 31, 0},
287 [U_OTP_PGMask10] = {0x003AE0, 31, 0},
288 [U_OTP_PGMask11] = {0x003AE4, 31, 0},
289 [U_OTP_PGMask12] = {0x003AE8, 31, 0},
290 [U_OTP_PGMask13] = {0x003AEC, 31, 0},
291 [U_OTP_PGMask14] = {0x003AF0, 31, 0},
292 [U_OTP_PGMask15] = {0x003AF4, 31, 0},
293 [U_OTP_PGMask16] = {0x003AF8, 31, 0},
294 [U_OTP_PGMask17] = {0x003AFC, 31, 0},
295 [U_OTP_v_PubOtpOID] = {0x003B00, 15, 0},
296 [U_OTP_NDS_Reserved0] = {0x003B00, 31, 16},
297 [U_OTP_v_PubOtpVID] = {0x003B04, 15, 0},
298 [U_OTP_NDS_Reserved1] = {0x003B04, 31, 16},
299 [U_OTP_v_PubOtpGP] = {0x003B08, 15, 0},
300 [U_OTP_LockWord_GP_group_W] = {0x003B08, 31, 16},
301 [U_OTP_v_PubOtpBID] = {0x003B0C, 3, 0},
302 [U_OTP_NDS_Reserved2] = {0x003B0C, 31, 4},
303 [U_OTP_v_PubOtpRsaIndex] = {0x003B10, 3, 0},
304 [U_OTP_NDS_Reserved3] = {0x003B10, 31, 4},
305 [U_OTP_v_PubOtpMinConfVer] = {0x003B14, 7, 0},
306 [U_OTP_NDS_Reserved4] = {0x003B14, 31, 8},
307 [U_OTP_VenderConstSel] = {0x003B18, 2, 0},
308 [U_OTP_NDS_Reserved5] = {0x003B18, 31, 3},
309 [U_OTP_LockWord_NDS_Key1] = {0x003B1C, 2, 0},
310 [U_OTP_LockWord_NDS_Key2] = {0x003B1C, 5, 3},
311 [U_OTP_LockWord_NDS_Key3] = {0x003B1C, 8, 6},
312 [U_OTP_LockWord_NDS_Key4] = {0x003B1C, 11, 9},
313 [U_OTP_LockWord_NDS_Key5] = {0x003B1C, 14, 12},
314 [U_OTP_LockWord_NDS_Key6] = {0x003B1C, 17, 15},
315 [U_OTP_LockWord_NDS_Key7] = {0x003B1C, 20, 18},
316 [U_OTP_LockWord_NDS_Key8] = {0x003B1C, 23, 21},
317 [U_OTP_NDSKeyValid] = {0x003B1C, 31, 24},
318 [U_OTP_forbid_NSK_wr_sck] = {0x003B20, 7, 0},
319 [U_OTP_UseCheckSum] = {0x003B20, 15, 8},
320 [U_OTP_allow_NDSKey_BlankChk] = {0x003B20, 17, 16},
321 [U_OTP_allow_ProgFail_RuinNDSKey] = {0x003B20, 19, 18},
322 [U_OTP_allow_NDSReadKeyWait200ms] = {0x003B20, 21, 20},
323 [U_OTP_allow_ReadErrorRstOtp] = {0x003B20, 23, 22},
324 [U_OTP_allow_illegalNDSFlagChk] = {0x003B20, 27, 24},
325 [U_OTP_allow_Rst_NDS_SCFlag_ParityFail] = {0x003B20, 31, 28},
326 [U_OTP_ena_ACPUUseNSK2] = {0x003B24, 3, 0},
327 [U_OTP_ena_DBUSUseNSK2] = {0x003B24, 7, 4},
328 [U_OTP_ena_ForceOneMilSec] = {0x003B24, 11, 8},
329 [U_OTP_allow_SCCheck] = {0x003B24, 15, 12},
330 [U_OTP_ena_TestRCFreq] = {0x003B24, 19, 16},
331 [U_OTP_ena_SWRN] = {0x003B24, 23, 20},
332 [U_OTP_ena_NSKSeedPRNG] = {0x003B24, 27, 24},
333 [U_OTP_OTPWritePWDProtect] = {0x003B24, 31, 28},
334 [U_OTP_NDS_keysel] = {0x003B28, 5, 0},
335 [U_OTP_allow_NSK2_PWD_Mode] = {0x003B28, 7, 6},
336 [U_OTP_ena_EMMFilter] = {0x003B28, 11, 8},
337 [U_OTP_ena_TestGenIN] = {0x003B28, 15, 12},
338 [U_OTP_RCFreq_map] = {0x003B28, 20, 16},
339 [U_OTP_NDS_Reserved6] = {0x003B28, 31, 21},
340 [U_OTP_allow_SkipBadNVBit] = {0x003B2C, 1, 0},
341 [U_OTP_allow_NDSSC_ReadFail_BadPkt] = {0x003B2C, 3, 2},
342 [U_OTP_allow_RANDOM_keybus] = {0x003B2C, 5, 4},
343 [U_OTP_allow_RANDOM_byteacc] = {0x003B2C, 7, 6},
344 [U_OTP_allow_NDS_Rd55AA] = {0x003B2C, 9, 8},
345 [U_OTP_allow_NDS_Parity_chk] = {0x003B2C, 11, 10},
346 [U_OTP_allow_NDS_KeyRd55AA] = {0x003B2C, 13, 12},
347 [U_OTP_forbid_OTPBuiltInTest] = {0x003B2C, 15, 14},
348 [U_OTP_forbid_Kilo_ProgRepair] = {0x003B2C, 17, 16},
349 [U_OTP_NDS_Reserved7] = {0x003B2C, 31, 18},
350 [U_OTP_NVCOUNT] = {0x003B30, 1023, 0},
351 [U_OTP_NDS_SecretKey1] = {0x003BB0, 127, 0},
352 [U_OTP_NDS_SecretKey2] = {0x003BC0, 127, 0},
353 [U_OTP_NDS_SecretKey3] = {0x003BD0, 127, 0},
354 [U_OTP_NDS_SecretKey4] = {0x003BE0, 127, 0},
355 [U_OTP_NDS_SecretKey5] = {0x003BF0, 127, 0},
356 [U_OTP_NDS_SecretKey6] = {0x003C00, 127, 0},
357 [U_OTP_NDS_SecretKey7] = {0x003C10, 127, 0},
358 [U_OTP_NDS_SecretKey8] = {0x003C20, 127, 0},
359 [U_OTP_NDSKey1Chksum] = {0x003C30, 7, 0},
360 [U_OTP_NDSKey1Tag] = {0x003C30, 15, 8},
361 [U_OTP_NDSKey2Chksum] = {0x003C30, 23, 16},
362 [U_OTP_NDSKey2Tag] = {0x003C30, 31, 24},
363 [U_OTP_NDSKey3Chksum] = {0x003C34, 7, 0},
364 [U_OTP_NDSKey3Tag] = {0x003C34, 15, 8},
365 [U_OTP_NDSKey4Chksum] = {0x003C34, 23, 16},
366 [U_OTP_NDSKey4Tag] = {0x003C34, 31, 24},
367 [U_OTP_NDSKey5Chksum] = {0x003C38, 7, 0},
368 [U_OTP_NDSKey5Tag] = {0x003C38, 15, 8},
369 [U_OTP_NDSKey6Chksum] = {0x003C38, 23, 16},
370 [U_OTP_NDSKey6Tag] = {0x003C38, 31, 24},
371 [U_OTP_NDSKey7Chksum] = {0x003C3C, 7, 0},
372 [U_OTP_NDSKey7Tag] = {0x003C3C, 15, 8},
373 [U_OTP_NDSKey8Chksum] = {0x003C3C, 23, 16},
374 [U_OTP_NDSKey8Tag] = {0x003C3C, 31, 24},
375 [U_OTP_NDS_Key1_CRC] = {0x003C40, 15, 0},
376 [U_OTP_NDS_Key2_CRC] = {0x003C40, 31, 16},
377 [U_OTP_NDS_Key3_CRC] = {0x003C44, 15, 0},
378 [U_OTP_NDS_Key4_CRC] = {0x003C44, 31, 16},
379 [U_OTP_NDS_Key5_CRC] = {0x003C48, 15, 0},
380 [U_OTP_NDS_Key6_CRC] = {0x003C48, 31, 16},
381 [U_OTP_NDS_Key7_CRC] = {0x003C4C, 15, 0},
382 [U_OTP_NDS_Key8_CRC] = {0x003C4C, 31, 16},
383 [U_OTP_NDS_ESCK_Key1_obfuscation] = {0x003C50, 1, 0},
384 [U_OTP_NDS_Key1_integrity_chk] = {0x003C50, 3, 2},
385 [U_OTP_NDS_ESCK_Key2_obfuscation] = {0x003C50, 5, 4},
386 [U_OTP_NDS_Key2_integrity_chk] = {0x003C50, 7, 6},
387 [U_OTP_NDS_ESCK_Key3_obfuscation] = {0x003C50, 9, 8},
388 [U_OTP_NDS_Key3_integrity_chk] = {0x003C50, 11, 10},
389 [U_OTP_NDS_ESCK_Key4_obfuscation] = {0x003C50, 13, 12},
390 [U_OTP_NDS_Key4_integrity_chk] = {0x003C50, 15, 14},
391 [U_OTP_NDS_ESCK_Key5_obfuscation] = {0x003C50, 17, 16},
392 [U_OTP_NDS_Key5_integrity_chk] = {0x003C50, 19, 18},
393 [U_OTP_NDS_ESCK_Key6_obfuscation] = {0x003C50, 21, 20},
394 [U_OTP_NDS_Key6_integrity_chk] = {0x003C50, 23, 22},
395 [U_OTP_NDS_ESCK_Key7_obfuscation] = {0x003C50, 25, 24},
396 [U_OTP_NDS_Key7_integrity_chk] = {0x003C50, 27, 26},
397 [U_OTP_NDS_ESCK_Key8_obfuscation] = {0x003C50, 29, 28},
398 [U_OTP_NDS_Key8_integrity_chk] = {0x003C50, 31, 30},
399 [U_OTP_EJTAG_MODE_Parity_bit] = {0x003C54, 0, 0},
400 [U_OTP_I2C_MODE_Parity_bit] = {0x003C54, 1, 1},
401 [U_OTP_SCAN_MODE_Parity_bit] = {0x003C54, 2, 2},
402 [U_OTP_VenderConstSel_Parity_bit] = {0x003C54, 3, 3},
403 [U_OTP_v_PubOtpRsaIndex_Parity_bit] = {0x003C54, 4, 4},
404 [U_OTP_NDS_ESCK_Key1_obfuscation_Parity_bit] = {0x003C54, 5, 5},
405 [U_OTP_NDS_ESCK_Key2_obfuscation_Parity_bit] = {0x003C54, 6, 6},
406 [U_OTP_NDS_ESCK_Key3_obfuscation_Parity_bit] = {0x003C54, 7, 7},
407 [U_OTP_NDS_ESCK_Key4_obfuscation_Parity_bit] = {0x003C54, 8, 8},
408 [U_OTP_NDS_ESCK_Key5_obfuscation_Parity_bit] = {0x003C54, 9, 9},
409 [U_OTP_NDS_ESCK_Key6_obfuscation_Parity_bit] = {0x003C54, 10, 10},
410 [U_OTP_NDS_ESCK_Key7_obfuscation_Parity_bit] = {0x003C54, 11, 11},
411 [U_OTP_NDS_ESCK_Key8_obfuscation_Parity_bit] = {0x003C54, 12, 12},
412 [U_OTP_allow_ReadErrorRstOtp_Parity_bit] = {0x003C54, 13, 13},
413 [U_OTP_ena_ACPUUseNSK2_Parity_bit] = {0x003C54, 14, 14},
414 [U_OTP_BootMode_Parity_bit] = {0x003C54, 15, 15},
415 [U_OTP_ena_ACPU2KT_Parity_bit] = {0x003C54, 16, 16},
416 [U_OTP_ena_EMMFilter_Parity_bit] = {0x003C54, 17, 17},
417 [U_OTP_allow_NDS_Rd55AA_Parity_bit] = {0x003C54, 18, 18},
418 [U_OTP_forbid_OTPBuiltInTest_Parity_bit] = {0x003C54, 19, 19},
419 [U_OTP_allow_NSK_RNG_ROSC_Parity_bit] = {0x003C54, 20, 20},
420 [U_OTP_SecretAreaEnable_Parity_bit] = {0x003C54, 21, 21},
421 [U_OTP_forbid_SW_SPSD_Key_Parity_bit] = {0x003C54, 22, 22},
422 [U_OTP_allow_OTP_BgCRC_Parity_bit] = {0x003C54, 23, 23},
423 [U_OTP_forbid_USBSlaveMode_Parity_bit] = {0x003C54, 24, 24},
424 [U_OTP_OTPWritePWDProtect_Parity_bit] = {0x003C54, 25, 25},
425 [U_OTP_ena_NSK2_Parity_bit] = {0x003C54, 26, 26},
426 [U_OTP_NDS_Reserved8] = {0x003C54, 31, 27},
427 [U_OTP_ena_ESAAlgo_invalidate] = {0x003C58, 3, 0},
428 [U_OTP_ena_LocalAlgo_Invalidate] = {0x003C58, 7, 4},
429 [U_OTP_ContentProtEn] = {0x003C58, 11, 8},
430 [U_OTP_concurrency_configuration] = {0x003C58, 13, 12},
431 [U_OTP_allow_NSK_RNG_ROSC] = {0x003C58, 15, 14},
432 [U_OTP_nds_fc_disable] = {0x003C58, 16, 16},
433 [U_OTP_NDS_CPNR0_sel] = {0x003C58, 17, 17},
434 [U_OTP_NDS_CPNR_off] = {0x003C58, 18, 18},
435 [U_OTP_NDS_Reserved9] = {0x003C58, 31, 19},
436 [U_OTP_PM51_ST_ADDR] = {0x003C5C, 11, 0},
437 [U_OTP_PM51_ED_ADDR] = {0x003C5C, 23, 12},
438 [U_OTP_forbid_PM51ReadOTP] = {0x003C5C, 25, 24},
439 [U_OTP_forbid_PM51WriteOTP] = {0x003C5C, 27, 26},
440 [U_OTP_allow_PM51] = {0x003C5C, 29, 28},
441 [U_OTP_PM51_SW_R2] = {0x003C5C, 31, 30},
442 [U_OTP_forbid_CLK_SEED_TEST] = {0x003C60, 0, 0},
443 [U_OTP_MOBF_TOP_use_DES] = {0x003C60, 1, 1},
444 [U_OTP_OBFUSCATEVideoStream] = {0x003C60, 3, 2},
445 [U_OTP_forbid_EJTAG_Pinshare] = {0x003C60, 5, 4},
446 [U_OTP_allow_clear_sram] = {0x003C60, 6, 6},
447 [U_OTP_forbid_dft_md_sram] = {0x003C60, 7, 7},
448 [U_OTP_LINK_ISOEN2GPIO4] = {0x003C60, 8, 8},
449 [U_OTP_PM_SLEEP_WR_PROT_EN] = {0x003C60, 9, 9},
450 [U_OTP_PWR_HW_RST_MODE_EN] = {0x003C60, 10, 10},
451 [U_OTP_ISOC_TST_DIG_EN_GATE] = {0x003C60, 11, 11},
452 [U_OTP_OTHERS_Reserved0] = {0x003C60, 15, 12},
453 [U_OTP_Rsv_Feature] = {0x003C60, 31, 16},
454 [U_OTP_forbid_CA_MCM] = {0x003C64, 2, 0},
455 [U_OTP_forbid_DIAMOND_PMU] = {0x003C64, 5, 3},
456 [U_OTP_allow_force_dual_core] = {0x003C64, 6, 6},
457 [U_OTP_disable_jpi] = {0x003C64, 7, 7},
458 [U_OTP_forbid_DIG_PMU] = {0x003C64, 10, 8},
459 [U_OTP_forbid_WHOLECHIP_alive_when_NOCORE_alive] = {0x003C64, 13, 11},
460 [U_OTP_OTHERS_Reserved2] = {0x003C64, 15, 14},
461 [U_OTP_allow_CORE0_always_alive] = {0x003C64, 18, 16},
462 [U_OTP_allow_NONCORE0_default_reset] = {0x003C64, 21, 19},
463 [U_OTP_pwrgd_int_en] = {0x003C64, 22, 22},
464 [U_OTP_OTHERS_Reserved3] = {0x003C64, 31, 23},
465 [U_OTP_LOGICBIST_SCAN_OUT_CRC32] = {0x003C68, 31, 0},
466 [U_OTP_OTHERS_Reserved4] = {0x003C6C, 31, 0},
467 [U_OTP_RC_OPTION] = {0x003C70, 7, 0},
468 [U_OTP_RC_OPTION_EN] = {0x003C70, 8, 8},
469 [U_OTP_GCR_TRVBG] = {0x003C70, 14, 9},
470 [U_OTP_OTHERS_Reserved5] = {0x003C70, 15, 15},
471 [U_OTP_TEST_Status_TE] = {0x003C70, 23, 16},
472 [U_OTP_TEST_Status] = {0x003C70, 31, 24},
473 [U_OTP_ena_PVRNS2S] = {0x003C74, 3, 0},
474 [U_OTP_ena_PVRS2NS] = {0x003C74, 7, 4},
475 [U_OTP_ena_PlayBackRec0] = {0x003C74, 11, 8},
476 [U_OTP_ena_PlayBackRec1] = {0x003C74, 15, 12},
477 [U_OTP_ena_PlayBackRec2] = {0x003C74, 19, 16},
478 [U_OTP_ena_PlayBackRec3] = {0x003C74, 23, 20},
479 [U_OTP_ena_PlayBackRec4] = {0x003C74, 27, 24},
480 [U_OTP_ena_PlayBackRec5] = {0x003C74, 31, 28},
481 [U_OTP_ena_PVR_secure_protect_0] = {0x003C78, 3, 0},
482 [U_OTP_ena_PVR_secure_protect_1] = {0x003C78, 7, 4},
483 [U_OTP_ena_VQ_secure_protect_0] = {0x003C78, 11, 8},
484 [U_OTP_TSP_Reserved0] = {0x003C78, 15, 12},
485 [U_OTP_dis_TSO] = {0x003C78, 19, 16},
486 [U_OTP_ena_TS2TSO_0] = {0x003C78, 23, 20},
487 [U_OTP_ena_TS2TSO_1] = {0x003C78, 27, 24},
488 [U_OTP_ena_TSO_SecRange] = {0x003C78, 31, 28},
489 [U_OTP_CAVIDEnforcedTS0] = {0x003C7C, 5, 0},
490 [U_OTP_CAVIDEnforcedTS1] = {0x003C7C, 11, 6},
491 [U_OTP_CAVIDEnforcedTS2] = {0x003C7C, 17, 12},
492 [U_OTP_CAVIDEnforcedTS3] = {0x003C7C, 23, 18},
493 [U_OTP_CAVIDEnforcedTS4] = {0x003C7C, 29, 24},
494 [U_OTP_TSP_Reserved1] = {0x003C7C, 31, 30},
495 [U_OTP_CAVIDEnforcedTS5] = {0x003C80, 5, 0},
496 [U_OTP_ForbidAVtoSec] = {0x003C80, 6, 6},
497 [U_OTP_TSP_Reserved2] = {0x003C80, 7, 7},
498 [U_OTP_dis_clear_stream_to_PVR] = {0x003C80, 11, 8},
499 [U_OTP_forbid_SW_SPSD_Key] = {0x003C80, 13, 12},
500 [U_OTP_forbid_KL_SPSD_Key] = {0x003C80, 15, 14},
501 [U_OTP_allow_TSPCPUCodeProt] = {0x003C80, 17, 16},
502 [U_OTP_TSP_Reserved3] = {0x003C80, 31, 18},
503 [U_OTP_ena_KeyLadder_0_lock] = {0x003C84, 3, 0},
504 [U_OTP_ena_KeyLadder_1_lock] = {0x003C84, 7, 4},
505 [U_OTP_ena_NSK2_lock] = {0x003C84, 11, 8},
506 [U_OTP_ena_CERT_IP_lock] = {0x003C84, 15, 12},
507 [U_OTP_ena_DMA_lock] = {0x003C84, 19, 16},
508 [U_OTP_ena_SCPU_lock] = {0x003C84, 23, 20},
509 [U_OTP_Dlock_Reserved0] = {0x003C84, 31, 24},
510 [U_OTP_ena_ACPU2KT_lock] = {0x003C88, 3, 0},
511 [U_OTP_ena_NSK2KT_lock] = {0x003C88, 7, 4},
512 [U_OTP_ena_KL2KT_lock] = {0x003C88, 11, 8},
513 [U_OTP_ena_SCPU2KT_lock] = {0x003C88, 15, 12},
514 [U_OTP_ena_ACPU2DMA_lock] = {0x003C88, 19, 16},
515 [U_OTP_ena_DMA_DESBasedCipher_lock] = {0x003C88, 23, 20},
516 [U_OTP_Dlock_Reserved1] = {0x003C88, 31, 24},
517 [U_OTP_ena_LSACPCM_lock] = {0x003C8C, 3, 0},
518 [U_OTP_ena_AESBasedCipher_lock] = {0x003C8C, 7, 4},
519 [U_OTP_ena_DESBasedCipher_lock] = {0x003C8C, 11, 8},
520 [U_OTP_ena_3DESBasedCipher_lock] = {0x003C8C, 15, 12},
521 [U_OTP_ena_Multi2BasedCipher_lock] = {0x003C8C, 19, 16},
522 [U_OTP_ena_DVBCSA2ConfCipher_lock] = {0x003C8C, 23, 20},
523 [U_OTP_ena_DVBCSA2Cipher_lock] = {0x003C8C, 27, 24},
524 [U_OTP_ena_DVBCSA3BasedCipher_lock] = {0x003C8C, 31, 28},
525 [U_OTP_dis_kl0_hostkey_lock] = {0x003C90, 3, 0},
526 [U_OTP_dis_kl1_hostkey_lock] = {0x003C90, 7, 4},
527 [U_OTP_NDSKeyValid_lock] = {0x003C90, 11, 8},
528 [U_OTP_RC_OPTION_lock] = {0x003C90, 15, 12},
529 [U_OTP_Dlock_Reserved2] = {0x003C90, 31, 16},
530 [U_OTP_Dlock_Reserved3] = {0x003C94, 31, 0},
531 [U_OTP_LockWord_CA_reserved0_W] = {0x003C98, 1, 0},
532 [U_OTP_LockWord_CA_reserved1_W] = {0x003C98, 3, 2},
533 [U_OTP_LockWord_CA_reserved2_W] = {0x003C98, 5, 4},
534 [U_OTP_LockWord_CA_reserved3_W] = {0x003C98, 7, 6},
535 [U_OTP_LockWord_CA_reserved4_W] = {0x003C98, 9, 8},
536 [U_OTP_LockWord_CA_reserved5_W] = {0x003C98, 11, 10},
537 [U_OTP_LockWord_CA_reserved6_W] = {0x003C98, 13, 12},
538 [U_OTP_LockWord_CA_reserved7_W] = {0x003C98, 15, 14},
539 [U_OTP_LockWord_CA_reserved8_W] = {0x003C98, 17, 16},
540 [U_OTP_LockWord_CA_reserved9_W] = {0x003C98, 19, 18},
541 [U_OTP_LockWord_CA_reserved10_W] = {0x003C98, 21, 20},
542 [U_OTP_LockWord_CA_reserved11_W] = {0x003C98, 23, 22},
543 [U_OTP_LockWord_CA_reserved12_W] = {0x003C98, 25, 24},
544 [U_OTP_LockWord_CA_reserved13_W] = {0x003C98, 27, 26},
545 [U_OTP_LockWord_CA_reserved14_W] = {0x003C98, 29, 28},
546 [U_OTP_LockWord_CA_reserved15_W] = {0x003C98, 31, 30},
547 [U_OTP_LockWord_RSA_0_W] = {0x003C9C, 1, 0},
548 [U_OTP_LockWord_RSA_1_W] = {0x003C9C, 3, 2},
549 [U_OTP_LockWord_RSA_CTRL_W] = {0x003C9C, 5, 4},
550 [U_OTP_LockWord_IXSC_Config_W] = {0x003C9C, 7, 6},
551 [U_OTP_LockWord_v_PubOtpOID_W] = {0x003C9C, 9, 8},
552 [U_OTP_LockWord_v_PubOtpVID_W] = {0x003C9C, 11, 10},
553 [U_OTP_LockWord_v_PubOtpBID_W] = {0x003C9C, 13, 12},
554 [U_OTP_LockWord_v_PubOtpRsaIndex_W] = {0x003C9C, 15, 14},
555 [U_OTP_LockWord_v_PubOtpMinConfVer_W] = {0x003C9C, 17, 16},
556 [U_OTP_LockWord_VenderConstSel_W] = {0x003C9C, 19, 18},
557 [U_OTP_LockWord_NDS_info_W] = {0x003C9C, 21, 20},
558 [U_OTP_LockWord_PM51_W] = {0x003C9C, 23, 22},
559 [U_OTP_LockWord_OTHERS_W] = {0x003C9C, 25, 24},
560 [U_OTP_LockWord_Reserved0] = {0x003C9C, 31, 26},
561 [U_OTP_LockWord_NOCS3_MEM0_W] = {0x003CA0, 1, 0},
562 [U_OTP_LockWord_NOCS3_MEM1_W] = {0x003CA0, 3, 2},
563 [U_OTP_LockWord_NOCS3_MEM2_W] = {0x003CA0, 5, 4},
564 [U_OTP_LockWord_NOCS3_MEM3_W] = {0x003CA0, 7, 6},
565 [U_OTP_LockWord_MSID_W] = {0x003CA0, 9, 8},
566 [U_OTP_LockWord_CFG_STB_CA_SN_W] = {0x003CA0, 11, 10},
567 [U_OTP_LockWord_TSP_W] = {0x003CA0, 13, 12},
568 [U_OTP_LockWord_PGMask_W] = {0x003CA0, 15, 14},
569 [U_OTP_LockWord_ClkDet_Para_W] = {0x003CA0, 17, 16},
570 [U_OTP_LockWord_OTP_CTRL_W] = {0x003CA0, 19, 18},
571 [U_OTP_LockWord_CPU_bank_W] = {0x003CA0, 21, 20},
572 [U_OTP_LockWord_trimming_W] = {0x003CA0, 23, 22},
573 [U_OTP_LockWord_BOND0_W] = {0x003CA0, 25, 24},
574 [U_OTP_LockWord_BOND_Reserved_W] = {0x003CA0, 27, 26},
575 [U_OTP_LockWord_Reserved1] = {0x003CA0, 31, 28},
576 [U_OTP_LockWord_LOT_INFO_W] = {0x003CA4, 1, 0},
577 [U_OTP_LockWord_CA_Enable_W] = {0x003CA4, 3, 2},
578 [U_OTP_LockWord_KL_bank_W] = {0x003CA4, 5, 4},
579 [U_OTP_LockWord_KT_bank_W] = {0x003CA4, 7, 6},
580 [U_OTP_LockWord_DMA_bank_W] = {0x003CA4, 9, 8},
581 [U_OTP_LockWord_TSCE_W] = {0x003CA4, 11, 10},
582 [U_OTP_LockWord_HDCP_KEY_W] = {0x003CA4, 13, 12},
583 [U_OTP_LockWord_Multi2SysKey_W] = {0x003CA4, 15, 14},
584 [U_OTP_LockWord_CAV_Key1_W] = {0x003CA4, 17, 16},
585 [U_OTP_LockWord_CAV_Key2_W] = {0x003CA4, 19, 18},
586 [U_OTP_LockWord_CAV_Key3_W] = {0x003CA4, 21, 20},
587 [U_OTP_LockWord_CAV_Key4_W] = {0x003CA4, 23, 22},
588 [U_OTP_LockWord_CAV_Key5_W] = {0x003CA4, 25, 24},
589 [U_OTP_LockWord_CAV_Key6_W] = {0x003CA4, 27, 26},
590 [U_OTP_LockWord_CAV_Key7_W] = {0x003CA4, 29, 28},
591 [U_OTP_LockWord_CAV_Key8_W] = {0x003CA4, 31, 30},
592 [U_OTP_LockWord_CAVID_W] = {0x003CA8, 1, 0},
593 [U_OTP_LockWord_CAV_KP1_W] = {0x003CA8, 3, 2},
594 [U_OTP_LockWord_CAV_KP2_W] = {0x003CA8, 5, 4},
595 [U_OTP_LockWord_CAV_KP3_W] = {0x003CA8, 7, 6},
596 [U_OTP_LockWord_CAV_KP4_W] = {0x003CA8, 9, 8},
597 [U_OTP_LockWord_CAV_KP5_W] = {0x003CA8, 11, 10},
598 [U_OTP_LockWord_CAV_KP6_W] = {0x003CA8, 13, 12},
599 [U_OTP_LockWord_CAV_KP7_W] = {0x003CA8, 15, 14},
600 [U_OTP_LockWord_CAV_KP8_W] = {0x003CA8, 17, 16},
601 [U_OTP_LockWord_CAV_KP9_W] = {0x003CA8, 19, 18},
602 [U_OTP_LockWord_CAV_KP10_W] = {0x003CA8, 21, 20},
603 [U_OTP_LockWord_CAV_KP11_W] = {0x003CA8, 23, 22},
604 [U_OTP_LockWord_CAV_KP12_W] = {0x003CA8, 25, 24},
605 [U_OTP_LockWord_CAV_KP13_W] = {0x003CA8, 27, 26},
606 [U_OTP_LockWord_CAV_KP14_W] = {0x003CA8, 29, 28},
607 [U_OTP_LockWord_CAV_KP15_W] = {0x003CA8, 31, 30},
608 [U_OTP_LockWord_PubOTPUniqueID1_W] = {0x003CAC, 1, 0},
609 [U_OTP_LockWord_PubOTPUniqueID2_W] = {0x003CAC, 3, 2},
610 [U_OTP_LockWord_PubOTPUniqueID3_W] = {0x003CAC, 5, 4},
611 [U_OTP_LockWord_PubOTPUniqueID4_W] = {0x003CAC, 7, 6},
612 [U_OTP_LockWord_AES_MOD_MASK_W] = {0x003CAC, 9, 8},
613 [U_OTP_LockWord_ACPU_Property_W] = {0x003CAC, 11, 10},
614 [U_OTP_LockWord_SCPU_Property_W] = {0x003CAC, 13, 12},
615 [U_OTP_LockWord_CA_PWD_W] = {0x003CAC, 15, 14},
616 [U_OTP_LockWord_CA_PWD_CTRL_W] = {0x003CAC, 17, 16},
617 [U_OTP_LockWord_VtrackData_W] = {0x003CAC, 19, 18},
618 [U_OTP_LockWord_FAKE_W] = {0x003CAC, 21, 20},
619 [U_OTP_LockWord_SW0_W] = {0x003CAC, 23, 22},
620 [U_OTP_LockWord_Reserved2] = {0x003CAC, 31, 26},
621 [U_OTP_LockWord_0000_0511_W] = {0x003CB0, 1, 0},
622 [U_OTP_LockWord_0512_1023_W] = {0x003CB0, 3, 2},
623 [U_OTP_LockWord_1024_1535_W] = {0x003CB0, 5, 4},
624 [U_OTP_LockWord_1536_2047_W] = {0x003CB0, 7, 6},
625 [U_OTP_LockWord_2048_2559_W] = {0x003CB0, 9, 8},
626 [U_OTP_LockWord_2560_3071_W] = {0x003CB0, 11, 10},
627 [U_OTP_LockWord_3072_3391_W] = {0x003CB0, 13, 12},
628 [U_OTP_LockWord_Chip_Extension_ID] = {0x003CB0, 15, 14},
629 [U_OTP_LockWord_Reserved3] = {0x003CB0, 31, 16},
630 [U_OTP_LockWord_CAV_Key1_R] = {0x003CB4, 1, 0},
631 [U_OTP_LockWord_CAV_Key2_R] = {0x003CB4, 3, 2},
632 [U_OTP_LockWord_CAV_Key3_R] = {0x003CB4, 5, 4},
633 [U_OTP_LockWord_CAV_Key4_R] = {0x003CB4, 7, 6},
634 [U_OTP_LockWord_CAV_Key5_R] = {0x003CB4, 9, 8},
635 [U_OTP_LockWord_CAV_Key6_R] = {0x003CB4, 11, 10},
636 [U_OTP_LockWord_CAV_Key7_R] = {0x003CB4, 13, 12},
637 [U_OTP_LockWord_CAV_Key8_R] = {0x003CB4, 15, 14},
638 [U_OTP_LockWord_RSA_0_R] = {0x003CB4, 17, 16},
639 [U_OTP_LockWord_RSA_1_R] = {0x003CB4, 19, 18},
640 [U_OTP_LockWord_HDCP_KEY_R] = {0x003CB4, 21, 20},
641 [U_OTP_LockWord_Multi2SysKey_R] = {0x003CB4, 23, 22},
642 [U_OTP_LockWord_AES_MOD_MASK_R] = {0x003CB4, 25, 24},
643 [U_OTP_LockWord_VtrackData_R] = {0x003CB4, 27, 26},
644 [U_OTP_LockWord_CA_PWD_R] = {0x003CB4, 29, 28},
645 [U_OTP_LockWord_Reserved4] = {0x003CB4, 31, 30},
646 [U_OTP_ClkDet_Para] = {0x003CB8, 63, 0},
647 [U_OTP_forbid_ACPUWriteOTP] = {0x003CC0, 1, 0},
648 [U_OTP_forbid_ACPUReadOTP] = {0x003CC0, 3, 2},
649 [U_OTP_forbid_SCPUWriteOTP] = {0x003CC0, 5, 4},
650 [U_OTP_forbid_SCPUReadOTP] = {0x003CC0, 7, 6},
651 [U_OTP_forbid_DBBUSWriteOTP] = {0x003CC0, 9, 8},
652 [U_OTP_forbid_DBBUSReadOTP] = {0x003CC0, 11, 10},
653 [U_OTP_allow_RANDOM] = {0x003CC0, 13, 12},
654 [U_OTP_allow_NOISE_Rd] = {0x003CC0, 15, 14},
655 [U_OTP_allow_OTP_BgCRC] = {0x003CC0, 17, 16},
656 [U_OTP_allow_SKIP_0] = {0x003CC0, 19, 18},
657 [U_OTP_allow_SKIP_1] = {0x003CC0, 21, 20},
658 [U_OTP_allow_Mask_AES] = {0x003CC0, 23, 22},
659 [U_OTP_ena_Mstar_Wrapper] = {0x003CC0, 25, 24},
660 [U_OTP_CTRL_Reserved0] = {0x003CC0, 31, 26},
661 [U_OTP_allow_XOR_ROMCODE] = {0x003CC4, 6, 0},
662 [U_OTP_allow_XOR_FIX] = {0x003CC4, 7, 7},
663 [U_OTP_allow_PWD_OTP_prog] = {0x003CC4, 9, 8},
664 [U_OTP_CTRL_Reserved1] = {0x003CC4, 31, 10},
665 [U_OTP_SBoot] = {0x003CC8, 3, 0},
666 [U_OTP_SecretAreaEnable] = {0x003CC8, 7, 4},
667 [U_OTP_forbid_TestInOut] = {0x003CC8, 9, 8},
668 [U_OTP_allow_FlashProtect] = {0x003CC8, 11, 10},
669 [U_OTP_PERSO_done] = {0x003CC8, 13, 12},
670 [U_OTP_CERT_PERSO_done] = {0x003CC8, 15, 14},
671 [U_OTP_DBUG_Reserved0] = {0x003CC8, 31, 16},
672 [U_OTP_SCAN_MODE] = {0x003CCC, 8, 0},
673 [U_OTP_DBUG_Reserved1] = {0x003CCC, 9, 9},
674 [U_OTP_MBIST_MODE] = {0x003CCC, 15, 10},
675 [U_OTP_I2C_MODE] = {0x003CCC, 21, 16},
676 [U_OTP_DBUG_Reserved2] = {0x003CCC, 25, 22},
677 [U_OTP_EJTAG_MODE] = {0x003CCC, 31, 26},
678 [U_OTP_RMA_MODE] = {0x003CD0, 5, 0},
679 [U_OTP_LicRework] = {0x003CD0, 7, 6},
680 [U_OTP_forbid_USBSlaveMode] = {0x003CD0, 11, 8},
681 [U_OTP_allow_DRAM_MOBF] = {0x003CD0, 13, 12},
682 [U_OTP_allow_DRAMOBF_4ROUND] = {0x003CD0, 15, 14},
683 [U_OTP_ena_DRAMOBF_NS_MASK_ADDR] = {0x003CD0, 17, 16},
684 [U_OTP_forbid_clk_otp_sel] = {0x003CD0, 20, 18},
685 [U_OTP_forbid_acpu_access_sec_bridge] = {0x003CD0, 23, 21},
686 [U_OTP_forbid_dbbus_access_sec_bridge] = {0x003CD0, 26, 24},
687 [U_OTP_XPM_State] = {0x003CD0, 29, 27},
688 [U_OTP_DBUG_Reserved3] = {0x003CD0, 31, 30},
689 [U_OTP_DeactiveDRAMBoot] = {0x003CD4, 3, 0},
690 [U_OTP_ACPU_Reserved0] = {0x003CD4, 7, 4},
691 [U_OTP_BootMode] = {0x003CD4, 13, 8},
692 [U_OTP_forbid_BCKGND_CHK] = {0x003CD4, 15, 14},
693 [U_OTP_SCPUBootMode] = {0x003CD4, 21, 16},
694 [U_OTP_ACPU_Reserved1] = {0x003CD4, 23, 22},
695 [U_OTP_PM_MCU_RST_MOD] = {0x003CD4, 26, 24},
696 [U_OTP_boot_host_sel] = {0x003CD4, 29, 27},
697 [U_OTP_ACPU_Reserved2] = {0x003CD4, 31, 30},
698 [U_OTP_ACPU_Reserved3] = {0x003CD8, 11, 0},
699 [U_OTP_PostMskAreaRangeU] = {0x003CD8, 23, 12},
700 [U_OTP_ACPUasHost] = {0x003CD8, 26, 24},
701 [U_OTP_BONDING] = {0x003CD8, 28, 27},
702 [U_OTP_NON_BLANK] = {0x003CD8, 29, 29},
703 [U_OTP_ACPU_Reserved4] = {0x003CD8, 31, 30},
704 [U_OTP_PE_LOT_INFO] = {0x003CDC, 47, 0},
705 [U_OTP_BootDevice] = {0x003CDC, 55, 48},
706 [U_OTP_MAX_RDNTBLK] = {0x003CDC, 61, 56},
707 [U_OTP_forbid_STR] = {0x003CDC, 63, 62},
708 [U_OTP_Bootcode_project] = {0x003CE4, 7, 0},
709 [U_OTP_Bootcode_subversion] = {0x003CE4, 15, 8},
710 [U_OTP_Bootcode_version] = {0x003CE4, 31, 16},
711 [U_OTP_Analog_Usage] = {0x003CE8, 63, 0},
712 [U_OTP_Analog_Usage2] = {0x003CF0, 95, 0},
713 [U_OTP_trim_dac] = {0x003CFC, 125, 0},
714 [U_OTP_Trim_Reserved0] = {0x003CFC, 127, 126},
715 [U_OTP_BOND0] = {0x003D0C, 95, 0},
716 [U_OTP_BOND_Reserved] = {0x003D18, 95, 0},
717 [U_OTP_ena_KeyLadder_0] = {0x003D24, 3, 0},
718 [U_OTP_ena_KeyLadder_1] = {0x003D24, 7, 4},
719 [U_OTP_ena_NSK2] = {0x003D24, 11, 8},
720 [U_OTP_ena_CERT_IP] = {0x003D24, 13, 12},
721 [U_OTP_ena_DMA] = {0x003D24, 15, 14},
722 [U_OTP_ena_SCPU] = {0x003D24, 19, 16},
723 [U_OTP_CA_EN_Reserved0] = {0x003D24, 31, 20},
724 [U_OTP_allow_IXSC] = {0x003D28, 3, 0},
725 [U_OTP_forbid_IXSC] = {0x003D28, 7, 4},
726 [U_OTP_forbid_PAVOSC] = {0x003D28, 9, 8},
727 [U_OTP_cfDeactiveFuse] = {0x003D28, 10, 10},
728 [U_OTP_SOC_UID_SEL] = {0x003D28, 12, 11},
729 [U_OTP_CA_EN_Reserved2] = {0x003D28, 31, 13},
730 [U_OTP_dis_kl0_hostkey] = {0x003D2C, 1, 0},
731 [U_OTP_dis_kl1_hostkey] = {0x003D2C, 3, 2},
732 [U_OTP_dis_kl0_hostkey_property] = {0x003D2C, 5, 4},
733 [U_OTP_dis_kl1_hostkey_property] = {0x003D2C, 7, 6},
734 [U_OTP_kl_protect0_mode] = {0x003D2C, 9, 8},
735 [U_OTP_kl_protect1_mode] = {0x003D2C, 11, 10},
736 [U_OTP_kl_protect2_mode] = {0x003D2C, 13, 12},
737 [U_OTP_kl_protect3_mode] = {0x003D2C, 15, 14},
738 [U_OTP_dis_kl_protect0] = {0x003D2C, 17, 16},
739 [U_OTP_dis_kl_protect1] = {0x003D2C, 19, 18},
740 [U_OTP_dis_kl_protect2] = {0x003D2C, 21, 20},
741 [U_OTP_dis_kl_protect3] = {0x003D2C, 23, 22},
742 [U_OTP_dis_kl_protect4] = {0x003D2C, 25, 24},
743 [U_OTP_kl_TA_LUT0_mode] = {0x003D2C, 27, 26},
744 [U_OTP_kl_TA_LUT1_mode] = {0x003D2C, 29, 28},
745 [U_OTP_ena_kl_StopClkChk] = {0x003D2C, 31, 30},
746 [U_OTP_KDF_secret_mask] = {0x003D30, 127, 0},
747 [U_OTP_IMLB_ROTATION] = {0x003D40, 15, 0},
748 [U_OTP_IrdetoTweakedCSAv3] = {0x003D40, 17, 16},
749 [U_OTP_allow_SPSSPDKeyShuffle] = {0x003D40, 21, 18},
750 [U_OTP_kl_BISS_MODE] = {0x003D40, 23, 22},
751 [U_OTP_ena_kl_xor_func] = {0x003D40, 25, 24},
752 [U_OTP_KL_Reserved2] = {0x003D40, 31, 26},
753 [U_OTP_ena_ACPU2KT] = {0x003D44, 3, 0},
754 [U_OTP_ena_NSK2KT] = {0x003D44, 7, 4},
755 [U_OTP_ena_KL2KT] = {0x003D44, 11, 8},
756 [U_OTP_ena_SCPU2KT] = {0x003D44, 15, 12},
757 [U_OTP_ena_ACPUWrNSKKey2KT] = {0x003D44, 19, 16},
758 [U_OTP_ena_ACPUWrCFBKey2KT] = {0x003D44, 23, 20},
759 [U_OTP_ena_NSKCW2CryptoDMA] = {0x003D44, 27, 24},
760 [U_OTP_ena_ACPU2LSA] = {0x003D44, 31, 28},
761 [U_OTP_BISS_MODE] = {0x003D48, 3, 0},
762 [U_OTP_BISS_SUBMODE] = {0x003D48, 5, 4},
763 [U_OTP_KT_Reserved0] = {0x003D48, 31, 6},
764 [U_OTP_ena_ACPU2DMA] = {0x003D4C, 3, 0},
765 [U_OTP_ena_DMA_DESBasedCipher] = {0x003D4C, 7, 4},
766 [U_OTP_ena_AESMAC_MaxRate] = {0x003D4C, 9, 8},
767 [U_OTP_allow_DMAtDES2KeyEQChk] = {0x003D4C, 12, 10},
768 [U_OTP_DMA_Reserved0] = {0x003D4C, 13, 13},
769 [U_OTP_ena_DMA_ClearKeySlot ] = {0x003D4C, 15, 14},
770 [U_OTP_dis_DMA_mask_engine] = {0x003D4C, 17, 16},
771 [U_OTP_DMA_Reserved1] = {0x003D4C, 31, 18},
772 [U_OTP_ena_LSACPCM] = {0x003D50, 3, 0},
773 [U_OTP_ena_AESBasedCipher] = {0x003D50, 7, 4},
774 [U_OTP_ena_DESBasedCipher] = {0x003D50, 11, 8},
775 [U_OTP_ena_3DESBasedCipher] = {0x003D50, 15, 12},
776 [U_OTP_ena_Multi2BasedCipher] = {0x003D50, 19, 16},
777 [U_OTP_ena_DVBCSA2ConfCipher] = {0x003D50, 23, 20},
778 [U_OTP_ena_DVBCSA2Cipher] = {0x003D50, 27, 24},
779 [U_OTP_ena_DVBCSA3BasedCipher] = {0x003D50, 31, 28},
780 [U_OTP_Ch_SwitchComb] = {0x003D54, 63, 0},
781 [U_OTP_ena_LSAD_MDI] = {0x003D5C, 3, 0},
782 [U_OTP_ena_LSAD_MDD] = {0x003D5C, 7, 4},
783 [U_OTP_ena_LSAD_CIPLUS_AES] = {0x003D5C, 11, 8},
784 [U_OTP_ena_LSAD_AES_ECB_CLEAR] = {0x003D5C, 15, 12},
785 [U_OTP_ena_LSAD_SCTE41_SCTE52_DES] = {0x003D5C, 19, 16},
786 [U_OTP_TSCE_Reserved0] = {0x003D5C, 31, 20},
787 [U_OTP_ena_ESA_CIPLUS_AES] = {0x003D60, 3, 0},
788 [U_OTP_ena_ESA_CIPLUS_DES] = {0x003D60, 7, 4},
789 [U_OTP_ena_ESA_SCTE52_DES] = {0x003D60, 11, 8},
790 [U_OTP_ena_ESA_tDES_CBC_CLEAR] = {0x003D60, 15, 12},
791 [U_OTP_TSCE_Reserved1] = {0x003D60, 31, 16},
792 [U_OTP_ena_LSAS_MDI] = {0x003D64, 3, 0},
793 [U_OTP_ena_LSAS_MDD] = {0x003D64, 7, 4},
794 [U_OTP_ena_LSAS_CIPLUS_AES] = {0x003D64, 11, 8},
795 [U_OTP_ena_LSAS_AES_ECB_CLEAR] = {0x003D64, 15, 12},
796 [U_OTP_ena_LSAS_SCTE41_SCTE52_DES] = {0x003D64, 19, 16},
797 [U_OTP_TSCE_Reserved2] = {0x003D64, 31, 20},
798 [U_OTP_ena_DRMAreaEncrypt] = {0x003D68, 3, 0},
799 [U_OTP_ena_ReviewFailPkt] = {0x003D68, 7, 4},
800 [U_OTP_dis_NonSecRangeEncrypt] = {0x003D68, 11, 8},
801 [U_OTP_TSCE_Reserved3] = {0x003D68, 31, 12},
802 [U_OTP_ena_CA_PVR_secure_protect_0] = {0x003D6C, 3, 0},
803 [U_OTP_ena_CA_PVR_secure_protect_1] = {0x003D6C, 7, 4},
804 [U_OTP_ena_CA_PVR_secure_protect_2] = {0x003D6C, 11, 8},
805 [U_OTP_ena_CA_PVR_secure_protect_3] = {0x003D6C, 15, 12},
806 [U_OTP_ena_LowerPathRec] = {0x003D6C, 19, 16},
807 [U_OTP_ena_SWMulti2SysKey] = {0x003D6C, 23, 20},
808 [U_OTP_TSCE_Reserved4] = {0x003D6C, 31, 24},
809 [U_OTP_HDCP_KEY] = {0x003D70, 55, 0},
810 [U_OTP_HDCP_Reserved0] = {0x003D70, 7, 0},
811 [U_OTP_Multi2SysKey] = {0x003D78, 255, 0},
812 [U_OTP_AES_MOD_MASK] = {0x003D98, 127, 0},
813 [U_OTP_v_pubOtpUniqueID1] = {0x003DA8, 63, 0},
814 [U_OTP_v_pubOtpUniqueID2] = {0x003DB0, 63, 0},
815 [U_OTP_v_pubOtpUniqueID3] = {0x003DB8, 63, 0},
816 [U_OTP_v_pubOtpUniqueID4] = {0x003DC0, 63, 0},
817 [U_OTP_CAV_ESCK_KeyValid] = {0x003DC8, 7, 0},
818 [U_OTP_CAV_Reserved0] = {0x003DC8, 15, 8},
819 [U_OTP_CAV_SCK_KeyValid] = {0x003DC8, 31, 16},
820 [U_OTP_CAV_Reserved1] = {0x003DCC, 31, 0},
821 [U_OTP_CAV_Key1_SCK_mapping] = {0x003DD0, 15, 0},
822 [U_OTP_CAV_Key1_integrity_chk] = {0x003DD0, 17, 16},
823 [U_OTP_CAV_Key1_allow_ChkNum] = {0x003DD0, 19, 18},
824 [U_OTP_CAV_Key1_obfuscation] = {0x003DD0, 21, 20},
825 [U_OTP_CAV_Key1_IdSel] = {0x003DD0, 23, 22},
826 [U_OTP_CAV_Key1_KeySel] = {0x003DD0, 29, 24},
827 [U_OTP_CAV_Key1_reserved] = {0x003DD0, 31, 30},
828 [U_OTP_CAV_Key1_ChkNum_Gold] = {0x003DD4, 31, 0},
829 [U_OTP_CAV_Key2_SCK_mapping] = {0x003DD8, 15, 0},
830 [U_OTP_CAV_Key2_integrity_chk] = {0x003DD8, 17, 16},
831 [U_OTP_CAV_Key2_allow_ChkNum] = {0x003DD8, 19, 18},
832 [U_OTP_CAV_Key2_obfuscation] = {0x003DD8, 21, 20},
833 [U_OTP_CAV_Key2_IdSel] = {0x003DD8, 23, 22},
834 [U_OTP_CAV_Key2_KeySel] = {0x003DD8, 29, 24},
835 [U_OTP_CAV_Key2_reserved] = {0x003DD8, 31, 30},
836 [U_OTP_CAV_Key2_ChkNum_Gold] = {0x003DDC, 31, 0},
837 [U_OTP_CAV_Key3_SCK_mapping] = {0x003DE0, 15, 0},
838 [U_OTP_CAV_Key3_integrity_chk] = {0x003DE0, 17, 16},
839 [U_OTP_CAV_Key3_allow_ChkNum] = {0x003DE0, 19, 18},
840 [U_OTP_CAV_Key3_obfuscation] = {0x003DE0, 21, 20},
841 [U_OTP_CAV_Key3_IdSel] = {0x003DE0, 23, 22},
842 [U_OTP_CAV_Key3_KeySel] = {0x003DE0, 29, 24},
843 [U_OTP_CAV_Key3_reserved] = {0x003DE0, 31, 30},
844 [U_OTP_CAV_Key3_ChkNum_Gold] = {0x003DE4, 31, 0},
845 [U_OTP_CAV_Key4_SCK_mapping] = {0x003DE8, 15, 0},
846 [U_OTP_CAV_Key4_integrity_chk] = {0x003DE8, 17, 16},
847 [U_OTP_CAV_Key4_allow_ChkNum] = {0x003DE8, 19, 18},
848 [U_OTP_CAV_Key4_obfuscation] = {0x003DE8, 21, 20},
849 [U_OTP_CAV_Key4_IdSel] = {0x003DE8, 23, 22},
850 [U_OTP_CAV_Key4_KeySel] = {0x003DE8, 29, 24},
851 [U_OTP_CAV_Key4_reserved] = {0x003DE8, 31, 30},
852 [U_OTP_CAV_Key4_ChkNum_Gold] = {0x003DEC, 31, 0},
853 [U_OTP_CAV_Key5_SCK_mapping] = {0x003DF0, 15, 0},
854 [U_OTP_CAV_Key5_integrity_chk] = {0x003DF0, 17, 16},
855 [U_OTP_CAV_Key5_allow_ChkNum] = {0x003DF0, 19, 18},
856 [U_OTP_CAV_Key5_obfuscation] = {0x003DF0, 21, 20},
857 [U_OTP_CAV_Key5_IdSel] = {0x003DF0, 23, 22},
858 [U_OTP_CAV_Key5_KeySel] = {0x003DF0, 29, 24},
859 [U_OTP_CAV_Key5_reserved] = {0x003DF0, 31, 30},
860 [U_OTP_CAV_Key5_ChkNum_Gold] = {0x003DF4, 31, 0},
861 [U_OTP_CAV_Key6_SCK_mapping] = {0x003DF8, 15, 0},
862 [U_OTP_CAV_Key6_integrity_chk] = {0x003DF8, 17, 16},
863 [U_OTP_CAV_Key6_allow_ChkNum] = {0x003DF8, 19, 18},
864 [U_OTP_CAV_Key6_obfuscation] = {0x003DF8, 21, 20},
865 [U_OTP_CAV_Key6_IdSel] = {0x003DF8, 23, 22},
866 [U_OTP_CAV_Key6_KeySel] = {0x003DF8, 29, 24},
867 [U_OTP_CAV_Key6_reserved] = {0x003DF8, 31, 30},
868 [U_OTP_CAV_Key6_ChkNum_Gold] = {0x003DFC, 31, 0},
869 [U_OTP_CAV_Key7_SCK_mapping] = {0x003E00, 15, 0},
870 [U_OTP_CAV_Key7_integrity_chk] = {0x003E00, 17, 16},
871 [U_OTP_CAV_Key7_allow_ChkNum] = {0x003E00, 19, 18},
872 [U_OTP_CAV_Key7_obfuscation] = {0x003E00, 21, 20},
873 [U_OTP_CAV_Key7_IdSel] = {0x003E00, 23, 22},
874 [U_OTP_CAV_Key7_KeySel] = {0x003E00, 29, 24},
875 [U_OTP_CAV_Key7_reserved] = {0x003E00, 31, 30},
876 [U_OTP_CAV_Key7_ChkNum_Gold] = {0x003E04, 31, 0},
877 [U_OTP_CAV_Key8_SCK_mapping] = {0x003E08, 15, 0},
878 [U_OTP_CAV_Key8_integrity_chk] = {0x003E08, 17, 16},
879 [U_OTP_CAV_Key8_allow_ChkNum] = {0x003E08, 19, 18},
880 [U_OTP_CAV_Key8_obfuscation] = {0x003E08, 21, 20},
881 [U_OTP_CAV_Key8_IdSel] = {0x003E08, 23, 22},
882 [U_OTP_CAV_Key8_KeySel] = {0x003E08, 29, 24},
883 [U_OTP_CAV_Key8_reserved] = {0x003E08, 31, 30},
884 [U_OTP_CAV_Key8_ChkNum_Gold] = {0x003E0C, 31, 0},
885 [U_OTP_ACPU_Property] = {0x003E10, 127, 0},
886 [U_OTP_SCPU_Property] = {0x003E20, 127, 0},
887 [U_OTP_CAV_Key1_Property] = {0x003E30, 127, 0},
888 [U_OTP_CAV_Key2_Property] = {0x003E40, 127, 0},
889 [U_OTP_CAV_Key3_Property] = {0x003E50, 127, 0},
890 [U_OTP_CAV_Key4_Property] = {0x003E60, 127, 0},
891 [U_OTP_CAV_Key5_Property] = {0x003E70, 127, 0},
892 [U_OTP_CAV_Key6_Property] = {0x003E80, 127, 0},
893 [U_OTP_CAV_Key7_Property] = {0x003E90, 127, 0},
894 [U_OTP_CAV_Key8_Property] = {0x003EA0, 127, 0},
895 [U_OTP_CAV_Key9_Property] = {0x003EB0, 127, 0},
896 [U_OTP_CAV_Key10_Property] = {0x003EC0, 127, 0},
897 [U_OTP_CAV_Key11_Property] = {0x003ED0, 127, 0},
898 [U_OTP_CAV_Key12_Property] = {0x003EE0, 127, 0},
899 [U_OTP_CAV_Key13_Property] = {0x003EF0, 127, 0},
900 [U_OTP_CAV_Key14_Property] = {0x003F00, 127, 0},
901 [U_OTP_CAV_Key15_Property] = {0x003F10, 127, 0},
902 [U_OTP_CAV_SecretKey1] = {0x003F20, 127, 0},
903 [U_OTP_CAV_SecretKey2] = {0x003F30, 127, 0},
904 [U_OTP_CAV_SecretKey3] = {0x003F40, 127, 0},
905 [U_OTP_CAV_SecretKey4] = {0x003F50, 127, 0},
906 [U_OTP_CAV_SecretKey5] = {0x003F60, 127, 0},
907 [U_OTP_CAV_SecretKey6] = {0x003F70, 127, 0},
908 [U_OTP_CAV_SecretKey7] = {0x003F80, 127, 0},
909 [U_OTP_CAV_SecretKey8] = {0x003F90, 127, 0},
910 [U_OTP_CA_PWD_integrity_chk] = {0x003FA0, 1, 0},
911 [U_OTP_Multi2SysKey_integrity_chk] = {0x003FA0, 3, 2},
912 [U_OTP_CA_PWD_Reserved0] = {0x003FA0, 7, 4},
913 [U_OTP_I2C_PWD_obfuscation] = {0x003FA0, 9, 8},
914 [U_OTP_EJTAG_PWD_obfuscation] = {0x003FA0, 11, 10},
915 [U_OTP_SCAN_PWD_obfuscation] = {0x003FA0, 13, 12},
916 [U_OTP_MBIST_PWD_obfuscation] = {0x003FA0, 15, 14},
917 [U_OTP_Multi2SysKey_CRC] = {0x003FA0, 31, 16},
918 [U_OTP_I2C_PWD_CRC] = {0x003FA4, 15, 0},
919 [U_OTP_EJTAG_PWD_CRC] = {0x003FA4, 31, 16},
920 [U_OTP_SCAN_PWD_CRC] = {0x003FA8, 15, 0},
921 [U_OTP_MBIST_PWD_CRC] = {0x003FA8, 31, 16},
922 [U_OTP_CA_PWD_Keysel] = {0x003FAC, 5, 0},
923 [U_OTP_ena_TP_PWD] = {0x003FAC, 7, 6},
924 [U_OTP_ena_KDF_I2C_PWD] = {0x003FAC, 9, 8},
925 [U_OTP_ena_KDF_EJTAG_PWD] = {0x003FAC, 11, 10},
926 [U_OTP_ena_KDF_SCAN_PWD] = {0x003FAC, 13, 12},
927 [U_OTP_ena_KDF_MBIST_PWD] = {0x003FAC, 15, 14},
928 [U_OTP_I2C_TP_ID] = {0x003FAC, 19, 16},
929 [U_OTP_EJTAG_TP_ID] = {0x003FAC, 23, 20},
930 [U_OTP_SCAN_TP_ID] = {0x003FAC, 27, 24},
931 [U_OTP_MBIST_TP_ID] = {0x003FAC, 31, 28},
932 [U_OTP_I2C_PWD] = {0x003FB0, 127, 0},
933 [U_OTP_EJTAG_PWD] = {0x003FC0, 127, 0},
934 [U_OTP_SCAN_PWD] = {0x003FD0, 127, 0},
935 [U_OTP_MBIST_PWD] = {0x003FE0, 127, 0},
936 [U_OTP_VtrackID] = {0x003FF0, 31, 0},
937 [U_OTP_VtrackKey] = {0x003FF4, 31, 0},
938 [U_OTP_VtrackID_select] = {0x003FF8, 0, 0},
939 [U_OTP_VtrackKey_select] = {0x003FF8, 1, 1},
940 [U_OTP_Vtrack_Reserved0] = {0x003FF8, 31, 2},
941 [U_OTP_FAKE] = {0x003FFC, 23, 0},
942 [U_OTP_allow_CPU_rst_release] = {0x003FFC, 31, 24},
943
944 };
945
946
947 MS_BOOL _HAL_CA_OTP_GetConfig(MS_U32 u32Idx, MS_U32 *pu32Value);
948 MS_BOOL _HAL_CA_OTP_SetConfig(MS_U32 u32Idx, MS_U32 u32Value);
949
950 //--------------------------------------------------------------------------------------------------
951 // Macro of bit operations
952 //--------------------------------------------------------------------------------------------------
953
954 //--------------------------------------------------------------------------------------------------
955 // Inline Function
956 //--------------------------------------------------------------------------------------------------
HAL_CA_SetBank(MS_U32 u32RegAddr)957 void HAL_CA_SetBank(MS_U32 u32RegAddr)
958 {
959 _u32REGBase = u32RegAddr;
960 _u32REGPMBase = u32RegAddr - 0x200000UL;
961 _u32REG_OTP_Base = u32RegAddr + REG_OTP_BASE;
962 _u32REG_RSA_Base = u32RegAddr + REG_RSA_BASE;
963 }
964
HAL_CA_Init(void)965 MS_BOOL HAL_CA_Init(void)
966 {
967 return TRUE;
968 }
969
HAL_CA_BGC_ISR(void)970 void HAL_CA_BGC_ISR(void)
971 {
972 MS_U32 u32Excp = REG32(BGC_RESP_FAIL);
973 // MS_U32 u32SecID = u32Excp & BGC_RESP_SECID;
974
975 if((u32Excp & BGC_RESP_RESET_AV) == BGC_RESP_RESET_AV)
976 {
977 //AV reset
978 HAL_CA_DEBUG("BGC: unexpected modification of protected area detected. Reset AV.");
979 }
980
981 if((u32Excp & BGC_RESP_RESET_ACPU) == BGC_RESP_RESET_ACPU)
982 {
983 //ACPU reset
984 HAL_CA_DEBUG("BGC: unexpected modification of protected area detected. Reset ACPU.");
985 }
986
987 if((u32Excp & BGC_RESP_RESET_SCPU) == BGC_RESP_RESET_SCPU)
988 {
989 //SCPU reset
990 HAL_CA_DEBUG("BGC: unexpected modification of protected area detected. Reset SCPU.");
991 }
992
993 if((u32Excp & BGC_RESP_RESET_SYSTEM) == BGC_RESP_RESET_SYSTEM)
994 {
995 //If error is reset system, run reset system(only in keres)
996 //System reset
997 HAL_CA_DEBUG("BGC: unexpected modification of protected area detected. Reset system.");
998 // REG32_PM(REG_TOP_SW_RST) = ((REG32_PM(REG_TOP_SW_RST) & ~REG_TOP_SW_RST_MSK) | REG_TOP_SW_RST_PASSWD);
999 }
1000
1001
1002 }
1003
HAL_CA_BGC_DisableINT(void)1004 void HAL_CA_BGC_DisableINT(void)
1005 {
1006 REG32(REG_INTR_CPUINIT_HST3) = REG32(REG_INTR_CPUINIT_HST3) & (~REG_HST3TO2_INT);
1007 }
1008
HAL_CA_BGC_LoadFW(MS_U32 u32FwAddr,MS_U32 u32FwSize)1009 MS_BOOL HAL_CA_BGC_LoadFW(MS_U32 u32FwAddr, MS_U32 u32FwSize)
1010 {
1011 if(u32FwSize > 0x2000)
1012 { //max size is 8K
1013 return FALSE;
1014 }
1015
1016 if((REG32(REG_ONEWAY_42) & SEC51_SW_RST) == 0x0)//bit0, reset sec51
1017 {
1018 return TRUE;//already enable sec51
1019 }
1020
1021 REG32(REG_BDMA_STATUS) = REG32(REG_BDMA_STATUS) | 0x10; // triger bdma
1022 REG32(REG_BDMA_CTRL) = 0x0; //disable
1023 REG32(REG_BDMA_SRC_SEL) = 0x0940; //MIU0 to Sec_51
1024 REG32(REG_BDMA_SRC_ADDR_L) = u32FwAddr & 0xFFFF;
1025 REG32(REG_BDMA_SRC_ADDR_H) = (u32FwAddr >> 16) & 0xFFFF;
1026 REG32(REG_BDMA_DST_ADDR_L) = 0x0;
1027 REG32(REG_BDMA_DST_ADDR_H) = 0x0;
1028 REG32(REG_BDMA_SIZE_L) = u32FwSize & 0xFFFF; //size
1029 REG32(REG_BDMA_SIZE_H) = 0x0;
1030 REG32(REG_BDMA_CTRL) = 0x1; // triger bdma
1031 while((REG32(REG_BDMA_CTRL) & 0x1) != 0); //wait bdma done
1032
1033 REG32(REG_BDMA_STATUS) = REG32(REG_BDMA_STATUS) | 0x10; // triger bdma
1034
1035 REG32(REG_ONEWAY_42) = REG32(REG_ONEWAY_42) & (~SEC51_SW_RST);//bit 0, release sec51
1036
1037 REG32(REG_ONEWAY_52) = REG32(REG_ONEWAY_52) | SEC51_SW_LOCK;//bit 0, oneway lock sec51
1038
1039 //enable MIU cross bar
1040 REG32(REG_MIU_CROSSBAR_CTRL) = REG32(REG_MIU_CROSSBAR_CTRL) | REG_MIU_CROSSBAR_EN;
1041 return TRUE;
1042 }
1043
HAL_CA_BGC_Ctrl(MS_U32 u32Cmd,MS_U32 u32Data)1044 MS_BOOL HAL_CA_BGC_Ctrl(MS_U32 u32Cmd, MS_U32 u32Data)
1045 {
1046 MS_U16 u16Cmd = ((u32Data << BGC_CMD_SEC_DATA_SHT) & BGC_CMD_SEC_DATA) |
1047 ((u32Cmd << BGC_CMD_SEC_TYPE_SHT) & BGC_CMD_SEC_TYPE);
1048
1049 while((REG32(BGC_CMD_CTRL) & BGC_CMD_SEC_GO) == BGC_CMD_SEC_GO);
1050
1051 REG32(BGC_CMD_CTRL) = u16Cmd;
1052 REG32(BGC_CMD_CTRL) = u16Cmd | BGC_CMD_SEC_GO;
1053 // printf("[BGC Cmd]:%04X\n", u16Cmd);
1054
1055 while((REG32(BGC_CMD_CTRL) & BGC_CMD_SEC_GO) == BGC_CMD_SEC_GO);
1056 // printf("[BGC Cmd]:after write:%04X\n", REG32(BGC_CMD_CTRL));
1057
1058 if((REG32(BGC_CMD_CTRL) & BGC_CMD_SEC_STATUS) == BGC_CMD_SEC_STATUS)
1059 {
1060 return FALSE;
1061 }
1062 return TRUE;
1063 }
1064
HAL_CA_BGC_SetSec(MS_U32 u32SecId,const CA_BGC_SEC_CFG * pstSecCfg)1065 MS_BOOL HAL_CA_BGC_SetSec(MS_U32 u32SecId, const CA_BGC_SEC_CFG* pstSecCfg)
1066 {
1067 MS_U32 i = 0;
1068 MS_U32 u32Fail = 0;
1069
1070 if(u32SecId >= BGC_SEC_MAX )
1071 {
1072 return FALSE;
1073 }
1074
1075 //set section id
1076 if(HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_SECID, u32SecId) == FALSE)
1077 {
1078 u32Fail = 1;
1079 goto BGC_CONFIG_FAIL;
1080 }
1081
1082 //set BGC mode
1083 if(HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_MODE, pstSecCfg->u32BGCMode == 1 ? BGC_SEC_MODE_STATIC : BGC_SEC_MODE_DYNAMIC) == FALSE)
1084 {
1085 u32Fail = 2;
1086 goto BGC_CONFIG_FAIL;
1087 }
1088
1089 //set protect address and input cmd length
1090 if(HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_LENGTH, 0x4) == FALSE)
1091 {
1092 u32Fail = 3;
1093 goto BGC_CONFIG_FAIL;
1094 }
1095
1096 if((HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_ADDR, (pstSecCfg->u32ProtectAddr & 0x000000FF)>>0) == FALSE) |
1097 (HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_ADDR, (pstSecCfg->u32ProtectAddr & 0x0000FF00)>>8) == FALSE) |
1098 (HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_ADDR, (pstSecCfg->u32ProtectAddr & 0x00FF0000)>>16) == FALSE) |
1099 (HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_ADDR, (pstSecCfg->u32ProtectAddr & 0xFF000000)>>24) == FALSE))
1100 {
1101 u32Fail = 4;
1102 goto BGC_CONFIG_FAIL;
1103 }
1104
1105 //set protect size and input cmd length
1106 if(HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_LENGTH, 0x4) == FALSE)
1107 {
1108 u32Fail = 5;
1109 goto BGC_CONFIG_FAIL;
1110 }
1111 if((HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_SIZE, (pstSecCfg->u32ProtectSize & 0x000000FF)>>0) == FALSE) |
1112 (HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_SIZE, (pstSecCfg->u32ProtectSize & 0x0000FF00)>>8) == FALSE) |
1113 (HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_SIZE, (pstSecCfg->u32ProtectSize & 0x00FF0000)>>16) == FALSE) |
1114 (HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_SIZE, (pstSecCfg->u32ProtectSize & 0xFF000000)>>24) == FALSE))
1115 {
1116 u32Fail = 6;
1117 goto BGC_CONFIG_FAIL;
1118 }
1119
1120 //set interval bwteen two BGC check and input cmd length
1121 if(HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_LENGTH, 0x2) == FALSE)
1122 {
1123 u32Fail = 7;
1124 goto BGC_CONFIG_FAIL;
1125 }
1126 if((HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_INTERVAL, (pstSecCfg->u16Interval & 0x00FF)>>0) == FALSE) |
1127 (HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_INTERVAL, (pstSecCfg->u16Interval & 0xFF00)>>8) == FALSE))
1128 {
1129 u32Fail = 8;
1130 goto BGC_CONFIG_FAIL;
1131 }
1132
1133
1134 //set golden and incput golden length
1135 if(HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_LENGTH, 0x20) == FALSE)
1136 {
1137 u32Fail = 9;
1138 goto BGC_CONFIG_FAIL;
1139 }
1140
1141 for(i = 0 ; i < 0x20 ; i ++)
1142 {
1143 if(HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_GOLDEN, pstSecCfg->u8Golden[i]) == FALSE)
1144 {
1145 u32Fail = 10;
1146 goto BGC_CONFIG_FAIL;
1147 }
1148 }
1149
1150 //set password and incput length
1151 if(HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_LENGTH, 0x4) == FALSE)
1152 {
1153 u32Fail = 11;
1154 goto BGC_CONFIG_FAIL;
1155 }
1156
1157 for(i = 0 ; i < 0x4 ; i ++)
1158 {
1159 if(HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_SET_PASSWD, pstSecCfg->u8ResetPassword[i]) == FALSE)
1160 {
1161 u32Fail = 12;
1162 goto BGC_CONFIG_FAIL;
1163 }
1164 }
1165
1166 //set algorithm to sha256
1167 if(HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_ALGO, BGC_SEC_ALGO_SHA256) == FALSE)
1168 {
1169 u32Fail = 13;
1170 goto BGC_CONFIG_FAIL;
1171 }
1172
1173 //set the reset mode if BGC check fail
1174 if(HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_RESET_MODE, BGC_SEC_RESET_INTERRUPT | BGC_SEC_RESET_SYSTEM) == FALSE)
1175 {
1176 u32Fail = 14;
1177 goto BGC_CONFIG_FAIL;
1178 }
1179
1180 //enable section id
1181 if(HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_ENABLE, TRUE) == FALSE)
1182 {
1183 u32Fail = 15;
1184 goto BGC_CONFIG_FAIL;
1185 }
1186
1187 return TRUE;
1188
1189 BGC_CONFIG_FAIL:
1190 HAL_CA_DEBUG("BGC config fail:%08X\n", u32Fail);
1191 return FALSE;
1192 }
1193
HAL_CA_BGC_ResetSec(MS_U32 u32SecId,const MS_U8 * pu8RstPSWD)1194 MS_BOOL HAL_CA_BGC_ResetSec(MS_U32 u32SecId, const MS_U8* pu8RstPSWD)
1195 {
1196 MS_U32 i = 0;
1197 MS_U32 u32Fail = 0;
1198
1199 if((u32SecId >= BGC_SEC_MAX) || (pu8RstPSWD == NULL))
1200 {
1201 return FALSE;
1202 }
1203
1204 //check bgc mode, if mode = 1, return fail
1205 //set section id
1206 if(HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_SECID, u32SecId) == FALSE)
1207 {
1208 u32Fail = 1;
1209 goto BGC_RESET_FAIL;
1210 }
1211
1212 //set reset password and incput length
1213 if(HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_LENGTH, 0x4) == FALSE)
1214 {
1215 u32Fail = 2;
1216 goto BGC_RESET_FAIL;
1217 }
1218
1219 for(i = 0 ; i < 0x4 ; i ++)
1220 {
1221 if(HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_RESET_PASSWD, pu8RstPSWD[i]) == FALSE)
1222 {
1223 u32Fail = 3;
1224 goto BGC_RESET_FAIL;
1225 }
1226 }
1227 return TRUE;
1228
1229 BGC_RESET_FAIL:
1230 HAL_CA_DEBUG("BGC reset fail:%08X\n", u32Fail);
1231 return FALSE;
1232
1233 }
1234
HAL_CA_OTP_IsBlank(MS_U32 addr)1235 MS_BOOL HAL_CA_OTP_IsBlank(MS_U32 addr)
1236 {
1237 MS_U32 value;
1238
1239 if(addr >= CA_OTP_SIZE)
1240 return 0;
1241
1242 value = *(volatile MS_U32 *)(_u32REG_OTP_Base + addr);
1243
1244 return value == 0;
1245 }
1246
1247
_HAL_CA_OTP_Read_Real(MS_U32 addr,MS_BOOL bXor)1248 MS_U32 _HAL_CA_OTP_Read_Real(MS_U32 addr, MS_BOOL bXor)
1249 {
1250 MS_U32 value;
1251
1252 if(addr >= CA_OTP_SIZE)
1253 return 0;
1254
1255 value = *(volatile MS_U32 *)(_u32REG_OTP_Base + addr);
1256
1257 return value;
1258 }
1259
1260
HAL_CA_OTP_Read(MS_U32 addr)1261 MS_U32 HAL_CA_OTP_Read(MS_U32 addr)
1262 {
1263 return _HAL_CA_OTP_Read_Real(addr, FALSE);
1264 }
1265
1266
_HAL_CA_OTP_Write_Real(MS_U32 addr,MS_U8 value)1267 MS_BOOL _HAL_CA_OTP_Write_Real(MS_U32 addr, MS_U8 value)
1268 {
1269 MS_DEBUG_MSG(printf("[_HAL_CA_OTP_Write_Real] addr=0x%04lx value=0x%02lx\n", addr, (MS_U32)value);)
1270 #if 0
1271 printf("[_HAL_CA_OTP_Write_Real] NO REAL WRITE!!!\n");
1272 #else
1273 *(volatile MS_U8 *)(_u32REG_OTP_Base + addr) = value;
1274 #endif
1275
1276 MS_U32 v;
1277 v = REG32(REG_OTP_CTRL_PV) & REG_OTP_CTRL_PG_VERIFY_FAIL_FLAG;
1278 if(v == 0) {
1279 return TRUE;
1280 }
1281
1282 HAL_CA_DEBUG("[_HAL_CA_OTP_Write_Real] PV fail (0x%08x)\n", v);
1283 return FALSE;
1284 }
1285
HAL_CA_OTP_Write(MS_U32 addr,MS_U32 value)1286 MS_BOOL HAL_CA_OTP_Write(MS_U32 addr, MS_U32 value)
1287 {
1288 int i;
1289 if(addr >= CA_OTP_SIZE)
1290 return FALSE;
1291
1292 if(addr % 4 != 0)
1293 return FALSE;
1294
1295 REG32(REG_OTP_CTRL_0) = REG_OTP_CTRL_0_VALUE;
1296
1297 MS_U32 orig = _HAL_CA_OTP_Read_Real(addr, TRUE);
1298 MS_U32 write = value & (orig ^ value); // only write the bit from 0 to 1
1299
1300 if(write == 0)
1301 return TRUE;
1302
1303 for(i = 0; i < 4; i++) {
1304 if(_HAL_CA_OTP_Write_Real(addr + i, (value >> (i * 8)) & 0xff) == FALSE)
1305 return FALSE;
1306 }
1307
1308 MS_U32 result = _HAL_CA_OTP_Read_Real(addr, TRUE);
1309 if((result & value) == value) // only check the bit 1
1310 {
1311 return TRUE;
1312 }
1313
1314 return FALSE;
1315 }
1316
_HAL_CA_OTP_GetConfig(MS_U32 u32Idx,MS_U32 * pu32Value)1317 MS_BOOL _HAL_CA_OTP_GetConfig(MS_U32 u32Idx, MS_U32 *pu32Value)
1318 {
1319 MS_U32 u32Addr = _HAL_CA_OTP_Addr[u32Idx].u32Addr;
1320 MS_U32 u32Shift = _HAL_CA_OTP_Addr[u32Idx].u32Lo;
1321 MS_U32 u32Len = _HAL_CA_OTP_Addr[u32Idx].u32Hi - _HAL_CA_OTP_Addr[u32Idx].u32Lo + 1;
1322 MS_U32 u32Mask = bitmask(_HAL_CA_OTP_Addr[u32Idx].u32Hi, _HAL_CA_OTP_Addr[u32Idx].u32Lo);
1323
1324 if(pu32Value == NULL)
1325 return FALSE;
1326
1327 if(u32Len > 32)
1328 return FALSE;
1329
1330 *pu32Value = (HAL_CA_OTP_Read(u32Addr) & u32Mask) >> u32Shift;
1331
1332 return TRUE;
1333 }
1334
_HAL_CA_OTP_SetConfig(MS_U32 u32Idx,MS_U32 u32Value)1335 MS_BOOL _HAL_CA_OTP_SetConfig(MS_U32 u32Idx, MS_U32 u32Value)
1336 {
1337 //printf("[_HAL_CA_OTP_SetConfig] u32Idx=%ld u32Value=0x%08lx\n", u32Idx, u32Value);
1338
1339 MS_U32 u32Addr = _HAL_CA_OTP_Addr[u32Idx].u32Addr;
1340 MS_U32 u32Shift = _HAL_CA_OTP_Addr[u32Idx].u32Lo;
1341 MS_U32 u32Len = _HAL_CA_OTP_Addr[u32Idx].u32Hi - _HAL_CA_OTP_Addr[u32Idx].u32Lo + 1;
1342 MS_U32 u32Mask = bitmask(_HAL_CA_OTP_Addr[u32Idx].u32Hi, _HAL_CA_OTP_Addr[u32Idx].u32Lo);
1343
1344 if(u32Len > 32)
1345 return FALSE;
1346
1347 u32Value = (u32Value << u32Shift) & u32Mask;
1348
1349 return HAL_CA_OTP_Write(u32Addr, u32Value);
1350 }
1351
HAL_CA_OTP_EnableSecureBoot(void)1352 MS_BOOL HAL_CA_OTP_EnableSecureBoot(void)
1353 {
1354 return _HAL_CA_OTP_SetConfig(U_OTP_SBoot, 0xf);
1355 }
1356
HAL_CA_OTP_IsSecureBootEnabled(void)1357 MS_BOOL HAL_CA_OTP_IsSecureBootEnabled(void)
1358 {
1359 MS_U32 u32Value = 0;
1360 MS_BOOL ret = FALSE;
1361
1362 ret = _HAL_CA_OTP_GetConfig(U_OTP_SBoot, &u32Value);
1363
1364 if (ret == FALSE)
1365 {
1366 return FALSE;
1367 }
1368 return u32Value != 0;
1369 }
1370
1371
HAL_CA_OTP_SetBlockLock(MS_U32 u32Start,MS_U32 u32End,CA_LOCK_TYPE eLockType)1372 MS_BOOL HAL_CA_OTP_SetBlockLock(MS_U32 u32Start, MS_U32 u32End, CA_LOCK_TYPE eLockType)
1373 {
1374 //Not support
1375 MS_DEBUG_MSG(printf("[%s][%d] do not support\n", __FUNCTION__, __LINE__));
1376 return FALSE;
1377 }
1378
HAL_CA_OTP_GetBlockLock(MS_U32 * pu32Start,MS_U32 * pu32End,CA_LOCK_TYPE * peLockType)1379 MS_BOOL HAL_CA_OTP_GetBlockLock(MS_U32 *pu32Start, MS_U32 *pu32End, CA_LOCK_TYPE *peLockType)
1380 {
1381 //Not support
1382 MS_DEBUG_MSG(printf("[%s][%d] do not support\n", __FUNCTION__, __LINE__));
1383 return FALSE;
1384 }
1385
1386
1387 //=======================================================
1388 // RSA bank for Secure Range
1389 //=======================================================
1390
HAL_CA_RSA_SetSecureRange(MS_U32 u32SecSet,MS_U32 u32SecStart,MS_U32 u32SecEnd)1391 MS_BOOL HAL_CA_RSA_SetSecureRange(MS_U32 u32SecSet, MS_U32 u32SecStart, MS_U32 u32SecEnd)
1392 {
1393 if(u32SecSet > REG_RSA_SEC_RANGE_SET || u32SecEnd <= u32SecStart)
1394 return FALSE;
1395
1396 *(volatile MS_U32*) (_u32REGBase + REG_RSA_SEC_RANGE_START(u32SecSet)) = REG_RSA_SEC_RANGE_ENABLE | ( u32SecStart & REG_RSA_SEC_RANGE_MASK);
1397 *(volatile MS_U32*) (_u32REGBase + REG_RSA_SEC_RANGE_END(u32SecSet)) = REG_RSA_SEC_RANGE_ENABLE | ( u32SecEnd & REG_RSA_SEC_RANGE_MASK);
1398
1399 return TRUE;
1400 }
1401
HAL_CA_OTP_Lock(CA_OTP_LOCK eLock)1402 MS_BOOL HAL_CA_OTP_Lock(CA_OTP_LOCK eLock)
1403 {
1404 switch(eLock)
1405 {
1406 // Boot Area
1407 case E_BOOT_LockWord_W0000_0511_Addr:
1408 return _HAL_CA_OTP_SetConfig(U_OTP_LockWord_0000_0511_W, 0x3);
1409 case E_BOOT_LockWord_W0512_1023_Addr:
1410 return _HAL_CA_OTP_SetConfig(U_OTP_LockWord_0512_1023_W, 0x3);
1411 case E_BOOT_LockWord_W1024_1535_Addr:
1412 return _HAL_CA_OTP_SetConfig(U_OTP_LockWord_1024_1535_W, 0x3);
1413 case E_BOOT_LockWord_W1536_2047_Addr:
1414 return _HAL_CA_OTP_SetConfig(U_OTP_LockWord_1536_2047_W, 0x3);
1415 case E_BOOT_LockWord_W2048_2559_Addr:
1416 return _HAL_CA_OTP_SetConfig(U_OTP_LockWord_2048_2559_W, 0x3);
1417 case E_BOOT_LockWord_W2560_3071_Addr:
1418 return _HAL_CA_OTP_SetConfig(U_OTP_LockWord_2560_3071_W, 0x3);
1419 case E_BOOT_LockWord_W3072_3391_Addr:
1420 return _HAL_CA_OTP_SetConfig(U_OTP_LockWord_3072_3391_W, 0x3);
1421
1422 // IDs
1423 case E_LockWord_v_PubOtpOID:
1424 return _HAL_CA_OTP_SetConfig(U_OTP_LockWord_v_PubOtpOID_W, 0x3);
1425 case E_LockWord_v_PubOtpVID:
1426 return _HAL_CA_OTP_SetConfig(U_OTP_LockWord_v_PubOtpVID_W, 0x3);
1427 case E_LockWord_v_pubOtpUniqueID1:
1428 return _HAL_CA_OTP_SetConfig(U_OTP_LockWord_PubOTPUniqueID1_W, 0x3);
1429 case E_LockWord_v_pubOtpUniqueID2:
1430 return _HAL_CA_OTP_SetConfig(U_OTP_LockWord_PubOTPUniqueID2_W, 0x3);
1431 case E_LockWord_v_pubOtpUniqueID3:
1432 return _HAL_CA_OTP_SetConfig(U_OTP_LockWord_PubOTPUniqueID3_W, 0x3);
1433 case E_LockWord_v_pubOtpUniqueID4:
1434 return _HAL_CA_OTP_SetConfig(U_OTP_LockWord_PubOTPUniqueID4_W, 0x3);
1435 default:
1436 return FALSE;
1437 }
1438 }
1439
HAL_CA_Locked(CA_OTP_LOCK eLock)1440 MS_BOOL HAL_CA_Locked(CA_OTP_LOCK eLock)
1441 {
1442 MS_U32 u32Value = 0;
1443 MS_BOOL ret = FALSE;
1444 switch(eLock)
1445 {
1446 // Boot Area
1447 case E_BOOT_LockWord_W0000_0511_Addr:
1448 ret = _HAL_CA_OTP_GetConfig(U_OTP_LockWord_0000_0511_W, &u32Value);
1449 break;
1450 case E_BOOT_LockWord_W0512_1023_Addr:
1451 ret = _HAL_CA_OTP_GetConfig(U_OTP_LockWord_0512_1023_W, &u32Value);
1452 break;
1453 case E_BOOT_LockWord_W1024_1535_Addr:
1454 ret = _HAL_CA_OTP_GetConfig(U_OTP_LockWord_1024_1535_W, &u32Value);
1455 break;
1456 case E_BOOT_LockWord_W1536_2047_Addr:
1457 ret = _HAL_CA_OTP_GetConfig(U_OTP_LockWord_1536_2047_W, &u32Value);
1458 break;
1459 case E_BOOT_LockWord_W2048_2559_Addr:
1460 ret = _HAL_CA_OTP_GetConfig(U_OTP_LockWord_2048_2559_W, &u32Value);
1461 break;
1462 case E_BOOT_LockWord_W2560_3071_Addr:
1463 ret = _HAL_CA_OTP_GetConfig(U_OTP_LockWord_2560_3071_W, &u32Value);
1464 break;
1465 case E_BOOT_LockWord_W3072_3391_Addr:
1466 ret = _HAL_CA_OTP_GetConfig(U_OTP_LockWord_3072_3391_W, &u32Value);
1467 break;
1468
1469 // IDs
1470 case E_LockWord_v_PubOtpOID:
1471 ret = _HAL_CA_OTP_GetConfig(U_OTP_LockWord_v_PubOtpOID_W, &u32Value);
1472 break;
1473 case E_LockWord_v_PubOtpVID:
1474 ret = _HAL_CA_OTP_GetConfig(U_OTP_LockWord_v_PubOtpVID_W, &u32Value);
1475 break;
1476 case E_LockWord_v_pubOtpUniqueID1:
1477 ret = _HAL_CA_OTP_GetConfig(U_OTP_LockWord_PubOTPUniqueID1_W, &u32Value);
1478 break;
1479 case E_LockWord_v_pubOtpUniqueID2:
1480 ret = _HAL_CA_OTP_GetConfig(U_OTP_LockWord_PubOTPUniqueID2_W, &u32Value);
1481 break;
1482 case E_LockWord_v_pubOtpUniqueID3:
1483 ret = _HAL_CA_OTP_GetConfig(U_OTP_LockWord_PubOTPUniqueID3_W, &u32Value);
1484 break;
1485 case E_LockWord_v_pubOtpUniqueID4:
1486 ret = _HAL_CA_OTP_GetConfig(U_OTP_LockWord_PubOTPUniqueID4_W, &u32Value);
1487 break;
1488 default:
1489 ret = FALSE;
1490 }
1491
1492 if(ret == FALSE)
1493 return FALSE;
1494
1495 if(u32Value == 0x01) // 0x01 : unlock, xx : locked
1496 return FALSE;
1497
1498 return TRUE;
1499 }
1500
HAL_CA_OTP_SetRSAextID(MS_U32 u32Value)1501 MS_BOOL HAL_CA_OTP_SetRSAextID(MS_U32 u32Value)
1502 {
1503 return _HAL_CA_OTP_SetConfig(U_OTP_MSID, u32Value);
1504 }
1505
HAL_CA_OTP_GetRSAextID(void)1506 MS_U32 HAL_CA_OTP_GetRSAextID(void)
1507 {
1508
1509 MS_U32 u32Value = 0;
1510 MS_BOOL ret = FALSE;
1511
1512 ret = _HAL_CA_OTP_GetConfig(U_OTP_MSID, &u32Value);
1513
1514 if (ret == FALSE)
1515 {
1516 return FALSE;
1517 }
1518 return u32Value;
1519 }
1520
1521
HAL_CA_OTP_SetHASH_REF_VER_Ex(MS_U32 u32HASH0_REF_VER,MS_U32 u32HASH1_REF_VER,MS_U32 u32HASH2_REF_VER)1522 MS_BOOL HAL_CA_OTP_SetHASH_REF_VER_Ex(MS_U32 u32HASH0_REF_VER, MS_U32 u32HASH1_REF_VER, MS_U32 u32HASH2_REF_VER)
1523 {
1524 if(_HAL_CA_OTP_SetConfig(U_OTP_HASH0_VER_REF, u32HASH0_REF_VER) == FALSE)
1525 {
1526 return FALSE;
1527 }
1528
1529 if(_HAL_CA_OTP_SetConfig(U_OTP_HASH1_VER_REF, u32HASH1_REF_VER) == FALSE)
1530 {
1531 return FALSE;
1532 }
1533
1534 if(_HAL_CA_OTP_SetConfig(U_OTP_HASH2_VER_REF, u32HASH2_REF_VER) == FALSE)
1535 {
1536 return FALSE;
1537 }
1538
1539 return TRUE;
1540 }
1541
HAL_CA_OTP_GetHASH_REF_VER_Ex(MS_U32 * pu32HASH0_REF_VER,MS_U32 * pu32HASH1_REF_VER,MS_U32 * pu32HASH2_REF_VER)1542 MS_BOOL HAL_CA_OTP_GetHASH_REF_VER_Ex(MS_U32 *pu32HASH0_REF_VER, MS_U32 *pu32HASH1_REF_VER, MS_U32 *pu32HASH2_REF_VER)
1543 {
1544 MS_U32 u32Value = 0;
1545
1546 if(pu32HASH0_REF_VER != NULL)
1547 {
1548 if(_HAL_CA_OTP_GetConfig(U_OTP_HASH0_VER_REF, &u32Value) == FALSE)
1549 {
1550 return FALSE;
1551 }
1552
1553 *pu32HASH0_REF_VER = (u32Value);
1554 }
1555
1556 if(pu32HASH1_REF_VER != NULL)
1557 {
1558 if(_HAL_CA_OTP_GetConfig(U_OTP_HASH1_VER_REF, &u32Value) == FALSE)
1559 {
1560 return FALSE;
1561 }
1562 *pu32HASH1_REF_VER = (u32Value);
1563 }
1564
1565 if(pu32HASH2_REF_VER != NULL)
1566 {
1567 if(_HAL_CA_OTP_GetConfig(U_OTP_HASH2_VER_REF, &u32Value) == FALSE)
1568 {
1569 return FALSE;
1570 }
1571
1572 *pu32HASH2_REF_VER = (u32Value);
1573 }
1574
1575 return TRUE;
1576 }
1577
HAL_CA_OTP_SetHASH1_REF_VER(MS_U32 u32HASH1_REF_VER)1578 MS_BOOL HAL_CA_OTP_SetHASH1_REF_VER(MS_U32 u32HASH1_REF_VER)
1579 {
1580 if(HAL_CA_OTP_SetHASH_REF_VER_Ex(0, u32HASH1_REF_VER, 0) == FALSE)
1581 {
1582 return FALSE;
1583 }
1584
1585 return TRUE;
1586 }
1587
HAL_CA_OTP_GetHASH1_REF_VER(MS_U32 * pu32HASH1_REF_VER)1588 MS_BOOL HAL_CA_OTP_GetHASH1_REF_VER(MS_U32 *pu32HASH1_REF_VER)
1589 {
1590 if(HAL_CA_OTP_GetHASH_REF_VER_Ex(NULL, pu32HASH1_REF_VER, NULL) == FALSE)
1591 {
1592 return FALSE;
1593 }
1594
1595 return TRUE;
1596 }
1597
1598
HAL_CA_OTP_SetHASH_REF_VER(MS_U32 u32HASH0_REF_VER,MS_U32 u32HASH2_REF_VER)1599 MS_BOOL HAL_CA_OTP_SetHASH_REF_VER(MS_U32 u32HASH0_REF_VER, MS_U32 u32HASH2_REF_VER)
1600 {
1601 if(HAL_CA_OTP_SetHASH_REF_VER_Ex(u32HASH0_REF_VER, 0, u32HASH2_REF_VER) == FALSE)
1602 {
1603 return FALSE;
1604 }
1605
1606 return TRUE;
1607 }
1608
HAL_CA_OTP_GetHASH_REF_VER(MS_U32 * pu32HASH0_REF_VER,MS_U32 * pu32HASH2_REF_VER)1609 MS_BOOL HAL_CA_OTP_GetHASH_REF_VER(MS_U32 *pu32HASH0_REF_VER, MS_U32 *pu32HASH2_REF_VER)
1610 {
1611 if(HAL_CA_OTP_GetHASH_REF_VER_Ex(pu32HASH0_REF_VER, NULL, pu32HASH2_REF_VER) == FALSE)
1612 {
1613 return FALSE;
1614 }
1615
1616 return TRUE;
1617 }
1618
1619
HAL_CA_MaxDeviceIdSize(void)1620 MS_U32 HAL_CA_MaxDeviceIdSize(void)
1621 {
1622 return MAX_DEVICEID_SIZE;
1623 }
1624
HAL_CA_OTP_SetDeviceId(const MS_U8 * pu8Did,MS_U32 u32Size)1625 MS_BOOL HAL_CA_OTP_SetDeviceId(const MS_U8 *pu8Did, MS_U32 u32Size)
1626 {
1627 MS_U32 did[8] = {0};
1628 MS_U32 i, u32Addr;
1629 MS_U32 Did_Size = 2;
1630 MS_U8 *p = (MS_U8 *)did;
1631
1632 for(i = 0; i < sizeof(did) && i < u32Size; i++)
1633 {
1634 p[i] = pu8Did[i];
1635 }
1636
1637 u32Addr = _HAL_CA_OTP_Addr[U_OTP_v_pubOtpUniqueID1].u32Addr;
1638 for(i = 0; i < Did_Size; i++)
1639 {
1640 if(HAL_CA_OTP_Write(u32Addr,did[i]) == FALSE)
1641 {
1642 return FALSE;
1643 }
1644 u32Addr += 4;
1645 }
1646 u32Addr = _HAL_CA_OTP_Addr[U_OTP_v_pubOtpUniqueID2].u32Addr;
1647 for(i = Did_Size; i < (2*Did_Size); i++)
1648 {
1649 if(HAL_CA_OTP_Write(u32Addr,did[i]) == FALSE)
1650 {
1651 return FALSE;
1652 }
1653 u32Addr += 4;
1654 }
1655 u32Addr = _HAL_CA_OTP_Addr[U_OTP_v_pubOtpUniqueID3].u32Addr;
1656 for(i = (2*Did_Size); i < (3*Did_Size); i++)
1657 {
1658 if(HAL_CA_OTP_Write(u32Addr,did[i]) == FALSE)
1659 {
1660 return FALSE;
1661 }
1662 u32Addr += 4;
1663 }
1664 u32Addr = _HAL_CA_OTP_Addr[U_OTP_v_pubOtpUniqueID4].u32Addr;
1665 for(i = (3*Did_Size); i < (4*Did_Size); i++)
1666 {
1667 if(HAL_CA_OTP_Write(u32Addr,did[i]) == FALSE)
1668 {
1669 return FALSE;
1670 }
1671 u32Addr += 4;
1672 }
1673
1674 return TRUE;
1675 }
1676
HAL_CA_OTP_GetDeviceId(MS_U8 * pu8Did,MS_U32 u32Size)1677 MS_BOOL HAL_CA_OTP_GetDeviceId(MS_U8 *pu8Did, MS_U32 u32Size)
1678 {
1679 MS_U32 did[8] = {0};
1680 MS_U32 Did_Size = 2;
1681 MS_U32 i, u32Addr;
1682 MS_U8 *p = (MS_U8 *)did;
1683
1684 u32Addr = _HAL_CA_OTP_Addr[U_OTP_v_pubOtpUniqueID1].u32Addr;
1685 for(i = 0; i < Did_Size; i++)
1686 {
1687 did[i] = HAL_CA_OTP_Read(u32Addr);
1688 u32Addr += 4;
1689 }
1690 u32Addr = _HAL_CA_OTP_Addr[U_OTP_v_pubOtpUniqueID2].u32Addr;
1691 for(i = Did_Size; i < (2*Did_Size) ; i++)
1692 {
1693 did[i] = HAL_CA_OTP_Read(u32Addr);
1694 u32Addr += 4;
1695 }
1696 u32Addr = _HAL_CA_OTP_Addr[U_OTP_v_pubOtpUniqueID3].u32Addr;
1697 for(i = (2*Did_Size) ; i < (3*Did_Size) ; i++)
1698 {
1699 did[i] = HAL_CA_OTP_Read(u32Addr);
1700 u32Addr += 4;
1701 }
1702 u32Addr = _HAL_CA_OTP_Addr[U_OTP_v_pubOtpUniqueID4].u32Addr;
1703 for(i = (3*Did_Size); i < (4*Did_Size) ; i++)
1704 {
1705 did[i] = HAL_CA_OTP_Read(u32Addr);
1706 u32Addr += 4;
1707 }
1708
1709 for(i = 0; i < sizeof(did) && i < u32Size; i++)
1710 {
1711 pu8Did[i] = p[i];
1712 }
1713
1714 return TRUE;
1715 }
1716
HAL_CA_OTP_SetDebugPortMode(CA_DEBUG_PORT eDebugPort,CA_DEBUG_PORT_MODE eMode)1717 MS_BOOL HAL_CA_OTP_SetDebugPortMode(CA_DEBUG_PORT eDebugPort, CA_DEBUG_PORT_MODE eMode)
1718 {
1719 MS_U32 idx = 0;
1720 MS_U32 v = 0;
1721
1722 switch(eDebugPort)
1723 {
1724 case E_CA_DEBUG_PORT_I2C:
1725 idx = U_OTP_I2C_MODE;
1726 break;
1727 case E_CA_DEBUG_PORT_JTAG:
1728 idx = U_OTP_EJTAG_MODE;
1729 break;
1730 case E_CA_DEBUG_PORT_SCAN:
1731 idx = U_OTP_SCAN_MODE;
1732 break;
1733 default:
1734 return FALSE;
1735 }
1736
1737 switch(eMode)
1738 {
1739 case E_CA_DEBUG_PORT_OPEN:
1740 return TRUE;
1741 case E_CA_DEBUG_PORT_PASSWD:
1742 v = 0x7;
1743 break;
1744 case E_CA_DEBUG_PORT_CLOSE:
1745 v = 0x3f;
1746 break;
1747 default:
1748 return FALSE;
1749 }
1750
1751 return _HAL_CA_OTP_SetConfig(idx, v);
1752
1753 }
1754
1755
HAL_CA_OTP_GetDebugPortMode(CA_DEBUG_PORT eDebugPort,CA_DEBUG_PORT_MODE * eMode)1756 MS_BOOL HAL_CA_OTP_GetDebugPortMode(CA_DEBUG_PORT eDebugPort, CA_DEBUG_PORT_MODE *eMode)
1757 {
1758 MS_U32 v = 0;
1759 MS_BOOL ret = FALSE;
1760
1761 if(eMode == NULL)
1762 {
1763 return FALSE;
1764 }
1765
1766 switch(eDebugPort)
1767 {
1768 case E_CA_DEBUG_PORT_I2C:
1769 ret = _HAL_CA_OTP_GetConfig(U_OTP_I2C_MODE, &v);
1770 break;
1771 case E_CA_DEBUG_PORT_JTAG:
1772 ret = _HAL_CA_OTP_GetConfig(U_OTP_EJTAG_MODE, &v);
1773 break;
1774 case E_CA_DEBUG_PORT_SCAN:
1775 ret = _HAL_CA_OTP_GetConfig(U_OTP_SCAN_MODE, &v);
1776 break;
1777 default:
1778 return FALSE;
1779 }
1780
1781 if (ret == FALSE)
1782 {
1783 return FALSE;
1784 }
1785
1786 if(v & 0x38)
1787 {
1788 *eMode = E_CA_DEBUG_PORT_CLOSE;
1789 }
1790 else if(v)
1791 {
1792 *eMode = E_CA_DEBUG_PORT_PASSWD;
1793 }
1794 else
1795 {
1796 *eMode = E_CA_DEBUG_PORT_OPEN;
1797 }
1798
1799 return TRUE;
1800 }
1801
1802
1803 // This function is created to used for another hal driver: NSK2
HAL_CA_OTP_GetCfg(MS_U32 u32Idx,MS_U32 * pu32Value)1804 MS_BOOL HAL_CA_OTP_GetCfg(MS_U32 u32Idx,MS_U32 * pu32Value)
1805 {
1806 return _HAL_CA_OTP_GetConfig(u32Idx, pu32Value);
1807 }
1808
HAL_CA_OTP_EnableSecureCWMode(void)1809 MS_BOOL HAL_CA_OTP_EnableSecureCWMode(void)
1810 {
1811 return _HAL_CA_OTP_SetConfig(U_OTP_ena_ACPU2KT, 0xF);
1812 }
1813
HAL_CA_OTP_IsSecureCWMode(void)1814 MS_BOOL HAL_CA_OTP_IsSecureCWMode(void)
1815 {
1816 MS_U32 u32Value = 0;
1817 MS_BOOL ret = FALSE;
1818
1819 ret = _HAL_CA_OTP_GetConfig(U_OTP_ena_ACPU2KT, &u32Value);
1820
1821 if (ret == FALSE)
1822 {
1823 return FALSE;
1824 }
1825
1826 if(u32Value == 1)
1827 {
1828 return FALSE;
1829 }
1830 else
1831 {
1832 return TRUE;
1833 }
1834 }
1835
_HAL_CA_Random(void)1836 MS_U16 _HAL_CA_Random(void)
1837 {
1838 MS_U32 n;
1839
1840 do{
1841 n = REG32(REG_RNG_TRNG);
1842 if( n & REG_RNG_TRNG_VALID_MASK) //check valid
1843 {
1844 n &= REG_RNG_TRNG_OUT_MASK; // get random number
1845 REG32(REG_RNG_TRNG) = REG_RNG_TRNG_ACK; //ack
1846 break;
1847 }
1848 }while(1);
1849
1850 return n;
1851 }
1852
1853
HAL_CA_Random(void)1854 MS_U32 HAL_CA_Random(void)
1855 {
1856 MS_U32 u32Val = 0;
1857
1858 u32Val += _HAL_CA_Random()<<16;
1859 u32Val += _HAL_CA_Random();
1860
1861 return u32Val;
1862
1863 }
1864
HAL_CA_OTP_ReadCAVendor(void)1865 MS_U32 HAL_CA_OTP_ReadCAVendor(void)
1866 {
1867 MS_U32 u32CAV_Key_VendorID[CA_SCK_NUM] = {0}; // Store all VendorID
1868 MS_U32 u32CAV_Key_VendorID_Hi = 24; //High bit of VendorID in Key property
1869 MS_U32 u32CAV_Key_VendorID_Lo = 20; //Low bit of VendorID in Key property
1870
1871 MS_U32 u32CAV1_VendorID = 0;
1872 MS_U32 u32CAV2_VendorID = 0;
1873 MS_U32 u32CAV_Vendor = 0;
1874 MS_U32 u32CAV_Vendor_Shift = 16;
1875 MS_U32 u32CAV_Vendor_Num = 0; // Calculate how many different VendorID
1876
1877 MS_U32 u32Idx = 0;
1878 MS_U32 u32Addr = 0;
1879 MS_U32 u32Shift = 0;
1880 MS_U32 u32Len = 0;
1881 MS_U32 u32Mask = 0;
1882
1883 // Read VendorID of U_OTP_CAV_Keyn_Property
1884 for(u32Idx = 0; u32Idx < CA_SCK_NUM; u32Idx++)
1885 {
1886 u32Addr = _HAL_CA_OTP_Addr[u32Idx + U_OTP_CAV_Key1_Property].u32Addr;
1887 u32Shift = u32CAV_Key_VendorID_Lo;
1888 u32Len = u32CAV_Key_VendorID_Hi - u32CAV_Key_VendorID_Lo + 1;
1889 u32Mask = bitmask(u32CAV_Key_VendorID_Hi, u32CAV_Key_VendorID_Lo);
1890
1891 u32CAV_Key_VendorID[u32Idx] = (HAL_CA_OTP_Read(u32Addr) & u32Mask) >> u32Shift;
1892 }
1893
1894 // Assign VendorID
1895 for(u32Idx = 0; u32Idx < CA_SCK_NUM; u32Idx++)
1896 {
1897 // First non NULL VendorID assign to u32CAV1_VendorID
1898 if( (0 == u32CAV_Vendor_Num) && (CA_OTP_VENDOR_ID_NULL != u32CAV_Key_VendorID[u32Idx]) )
1899 {
1900 u32CAV1_VendorID = u32CAV_Key_VendorID[u32Idx];
1901 u32CAV_Vendor_Num++;
1902 }
1903 // Second non NULL and not u32CAV1_VendorID VendorID assign to u32CAV2_VendorID
1904 else if( (1 == u32CAV_Vendor_Num) && (CA_OTP_VENDOR_ID_NULL != u32CAV_Key_VendorID[u32Idx]) )
1905 {
1906 if(u32CAV1_VendorID != u32CAV_Key_VendorID[u32Idx])
1907 {
1908 u32CAV2_VendorID = u32CAV_Key_VendorID[u32Idx];
1909 u32CAV_Vendor_Num++;
1910 }
1911 }
1912 // If third non NULL, not u32CAV1_VendorID and not u32CAV2_VendorID VendorID
1913 else if( (2 <= u32CAV_Vendor_Num) && (CA_OTP_VENDOR_ID_NULL != u32CAV_Key_VendorID[u32Idx]) )
1914 {
1915 if( (u32CAV1_VendorID != u32CAV_Key_VendorID[u32Idx]) && (u32CAV2_VendorID != u32CAV_Key_VendorID[u32Idx]) )
1916 {
1917 u32CAV1_VendorID = CA_OTP_VENDOR_ID_UNKNOW;
1918 u32CAV2_VendorID = CA_OTP_VENDOR_ID_UNKNOW;
1919 u32CAV_Vendor_Num++;
1920 }
1921
1922 }
1923 }
1924
1925 // Transform VendorID to Vendor code
1926 switch(u32CAV1_VendorID)
1927 {
1928 case CA_OTP_VENDOR_ID_NULL:
1929 break;
1930 case CA_OTP_VENDOR_ID_NDS:
1931 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_NDS;
1932 break;
1933 case CA_OTP_VENDOR_ID_NAGRA:
1934 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_NAGRA;
1935 break;
1936 case CA_OTP_VENDOR_ID_VIACCESS:
1937 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_VIACCESS;
1938 break;
1939 case CA_OTP_VENDOR_ID_IRDETO:
1940 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_IRDETO;
1941 break;
1942 case CA_OTP_VENDOR_ID_VERIMATRIX:
1943 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_VERIMATRIX;
1944 break;
1945 case CA_OTP_VENDOR_ID_SMI:
1946 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_SMI;
1947 break;
1948 case CA_OTP_VENDOR_ID_CONAX:
1949 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_CONAX;
1950 break;
1951 case CA_OTP_VENDOR_ID_LATENS:
1952 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_LATENS;
1953 break;
1954 case CA_OTP_VENDOR_ID_ECHOSTAR:
1955 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_ECHOSTAR;
1956 break;
1957 default:
1958 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_UNKNOW;
1959 }
1960
1961 switch(u32CAV2_VendorID)
1962 {
1963 case CA_OTP_VENDOR_ID_NULL:
1964 break;
1965 case CA_OTP_VENDOR_ID_NDS:
1966 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_NDS << u32CAV_Vendor_Shift;
1967 break;
1968 case CA_OTP_VENDOR_ID_NAGRA:
1969 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_NAGRA << u32CAV_Vendor_Shift;
1970 break;
1971 case CA_OTP_VENDOR_ID_VIACCESS:
1972 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_VIACCESS << u32CAV_Vendor_Shift;
1973 break;
1974 case CA_OTP_VENDOR_ID_IRDETO:
1975 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_IRDETO << u32CAV_Vendor_Shift;
1976 break;
1977 case CA_OTP_VENDOR_ID_VERIMATRIX:
1978 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_VERIMATRIX << u32CAV_Vendor_Shift;
1979 break;
1980 case CA_OTP_VENDOR_ID_SMI:
1981 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_SMI << u32CAV_Vendor_Shift;
1982 break;
1983 case CA_OTP_VENDOR_ID_CONAX:
1984 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_CONAX << u32CAV_Vendor_Shift;
1985 break;
1986 case CA_OTP_VENDOR_ID_LATENS:
1987 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_LATENS << u32CAV_Vendor_Shift;
1988 break;
1989 case CA_OTP_VENDOR_ID_ECHOSTAR:
1990 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_ECHOSTAR << u32CAV_Vendor_Shift;
1991 break;
1992 default:
1993 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_UNKNOW << u32CAV_Vendor_Shift;
1994 }
1995
1996 return u32CAV_Vendor;
1997 }
1998
1999
HAL_CA_STR_SetBank(MS_U32 u32Bank)2000 void HAL_CA_STR_SetBank(MS_U32 u32Bank)
2001 {
2002 _u32REGPMBase = u32Bank;
2003
2004 return;
2005 }
2006
HAL_CA_STR_EnableKey(void)2007 void HAL_CA_STR_EnableKey(void)
2008 {
2009 MS_U16 u16Tmp = 0;
2010 u16Tmp = REG16_PM(REG_STR_KEY);
2011 u16Tmp |= REG_STR_DMA_KEY_VALID;
2012 REG16_PM(REG_STR_KEY) = u16Tmp;
2013
2014 return;
2015 }
2016
HAL_CA_STR_SetMAC(MS_U8 * pu8STRMAC,MS_U32 u32STRMACSize)2017 void HAL_CA_STR_SetMAC(MS_U8* pu8STRMAC, MS_U32 u32STRMACSize)
2018 {
2019 MS_U8 i = 0;
2020
2021 for(i = 0; i < (u32STRMACSize/2); i++) {
2022 REG16_PM(REG_STR_AUTH_RESULT + i*4) = (pu8STRMAC[i*2 + 1]<<8 |pu8STRMAC[i*2]);
2023 }
2024
2025 return;
2026 }
2027
HAL_CA_STR_SetParamAddr(MS_U8 * pu8BAddr)2028 void HAL_CA_STR_SetParamAddr(MS_U8 *pu8BAddr)
2029 {
2030 MS_U16 u16Tmp = 0;
2031
2032 u16Tmp = ((MS_VIRT)pu8BAddr & 0x0000FFFF);
2033 REG16_PM(REG_STR_PTR) = u16Tmp;
2034
2035 u16Tmp = ((MS_VIRT)pu8BAddr & 0xFFFF0000)>>16;
2036 REG16_PM(REG_STR_PTR + 4) = u16Tmp;
2037
2038 return;
2039 }
2040
HAL_CA_STR_EnableWarmBoot(void)2041 void HAL_CA_STR_EnableWarmBoot(void)
2042 {
2043 //Oneway
2044 REG16_PM(REG_WARM_BOOT_IND) = REG_WARM_BOOT_IND_MAGIC;
2045
2046 return;
2047 }
HAL_CA_OTP_SetSecretKey(CA_SECRET_KEY eKeySel,const MS_U8 * pu8SecretKey,MS_U32 u32Size)2048 MS_BOOL HAL_CA_OTP_SetSecretKey(CA_SECRET_KEY eKeySel, const MS_U8 *pu8SecretKey, MS_U32 u32Size)
2049 {
2050
2051 MS_U32 secret_key[4] = {0};
2052 MS_U32 i, j, u32Addr;
2053 MS_U8 *p = (MS_U8 *)secret_key;
2054 switch(eKeySel)
2055 {
2056 case E_CA_SECRET_KEY1:
2057 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CAV_SecretKey1].u32Addr;
2058 break;
2059 case E_CA_SECRET_KEY2:
2060 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CAV_SecretKey2].u32Addr;
2061 break;
2062 case E_CA_SECRET_KEY3:
2063 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CAV_SecretKey3].u32Addr;
2064 break;
2065 case E_CA_SECRET_KEY4:
2066 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CAV_SecretKey4].u32Addr;
2067 break;
2068 case E_CA_SECRET_KEY5:
2069 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CAV_SecretKey5].u32Addr;
2070 break;
2071 case E_CA_SECRET_KEY6:
2072 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CAV_SecretKey6].u32Addr;
2073 break;
2074 case E_CA_SECRET_KEY7:
2075 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CAV_SecretKey7].u32Addr;
2076 break;
2077 case E_CA_SECRET_KEY8:
2078 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CAV_SecretKey8].u32Addr;
2079 break;
2080 default:
2081 return FALSE;
2082 }
2083
2084 if(sizeof(secret_key)>u32Size)
2085 {
2086 j = u32Size;
2087 }
2088 else
2089 {
2090 j=sizeof(secret_key);
2091 }
2092 for(i = 0; i < sizeof(secret_key) && i < u32Size; i++)
2093 {
2094 p[i] = pu8SecretKey[(j-1)-i]; // Array reverse, for user easy viewing
2095 }
2096
2097 for(i = 0; i < 4; i++)
2098 {
2099 if(HAL_CA_OTP_Write(u32Addr,secret_key[i]) == FALSE)
2100 {
2101 return FALSE;
2102 }
2103 u32Addr += 4;
2104 }
2105 return TRUE;
2106 }
2107
HAL_CA_OTP_GetSecretKey(CA_SECRET_KEY eKeySel,MS_U8 * pu8SecretKey,MS_U32 u32Size)2108 MS_BOOL HAL_CA_OTP_GetSecretKey(CA_SECRET_KEY eKeySel, MS_U8 *pu8SecretKey, MS_U32 u32Size)
2109 {
2110 MS_U32 secret_key[4] = {0};
2111 MS_U32 i, j, u32Addr;
2112 MS_U8 *p = (MS_U8 *)secret_key;
2113
2114 switch(eKeySel)
2115 {
2116 case E_CA_SECRET_KEY1:
2117 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CAV_SecretKey1].u32Addr;
2118 break;
2119 case E_CA_SECRET_KEY2:
2120 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CAV_SecretKey2].u32Addr;
2121 break;
2122 case E_CA_SECRET_KEY3:
2123 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CAV_SecretKey3].u32Addr;
2124 break;
2125 case E_CA_SECRET_KEY4:
2126 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CAV_SecretKey4].u32Addr;
2127 break;
2128 case E_CA_SECRET_KEY5:
2129 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CAV_SecretKey5].u32Addr;
2130 break;
2131 case E_CA_SECRET_KEY6:
2132 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CAV_SecretKey6].u32Addr;
2133 break;
2134 case E_CA_SECRET_KEY7:
2135 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CAV_SecretKey7].u32Addr;
2136 break;
2137 case E_CA_SECRET_KEY8:
2138 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CAV_SecretKey8].u32Addr;
2139 break;
2140 default:
2141 return FALSE;
2142 }
2143 for(i = 0; i < 4; i++)
2144 {
2145 secret_key[i] = HAL_CA_OTP_Read(u32Addr);
2146 u32Addr += 4;
2147 }
2148
2149 if(sizeof(secret_key)>u32Size)
2150 {
2151 j = u32Size;
2152 }
2153 else
2154 {
2155 j=sizeof(secret_key);
2156 }
2157
2158 for(i = 0; i < sizeof(secret_key) && i < u32Size; i++)
2159 {
2160 pu8SecretKey[i] = p[(j-1)-i]; // Array reverse, for user easy viewing
2161 }
2162
2163 return TRUE;
2164 }
2165
HAL_CA_OTP_SetRSAKey(CA_RSA_KEY eKeySel,const MS_U8 * pu8RSAKey,MS_U32 u32Size)2166 MS_BOOL HAL_CA_OTP_SetRSAKey(CA_RSA_KEY eKeySel, const MS_U8 *pu8RSAKey, MS_U32 u32Size)
2167 {
2168 MS_U32 RSA_key[64] = {0};
2169 MS_U32 i, u32Addr;
2170 MS_U8 *p = (MS_U8 *)RSA_key;
2171
2172 switch(eKeySel)
2173 {
2174 case E_CA_RSA_KEY0:
2175 return FALSE;
2176 case E_CA_RSA_KEY1:
2177 u32Addr = _HAL_CA_OTP_Addr[U_OTP_RSA_1].u32Addr;
2178 break;
2179 default:
2180 return FALSE;
2181 }
2182
2183 for(i = 0; i < sizeof(RSA_key) && i < u32Size; i++)
2184 {
2185 p[i] = pu8RSAKey[i];
2186 }
2187 for(i = 0; i < 64; i++)
2188 {
2189 if(HAL_CA_OTP_Write(u32Addr,RSA_key[i]) == FALSE)
2190 {
2191 return FALSE;
2192 }
2193 u32Addr += 4;
2194 }
2195
2196 return TRUE;
2197 }
HAL_CA_OTP_GetRSAKey(CA_RSA_KEY eKeySel,MS_U8 * pu8RSAKey,MS_U32 u32Size)2198 MS_BOOL HAL_CA_OTP_GetRSAKey(CA_RSA_KEY eKeySel, MS_U8 *pu8RSAKey, MS_U32 u32Size)
2199 {
2200 MS_U32 RSA_key[64] = {0};
2201 MS_U32 i, u32Addr;
2202 MS_U8 *p = (MS_U8 *)RSA_key;
2203
2204 switch(eKeySel)
2205 {
2206 case E_CA_RSA_KEY0:
2207 return FALSE;
2208 break;
2209 case E_CA_RSA_KEY1:
2210 u32Addr = _HAL_CA_OTP_Addr[U_OTP_RSA_1].u32Addr;
2211 break;
2212 default:
2213 return FALSE;
2214 }
2215 for(i = 0; i < 64; i++)
2216 {
2217 RSA_key[i] = HAL_CA_OTP_Read(u32Addr);
2218 u32Addr += 4;
2219 }
2220 for(i = 0; i < sizeof(RSA_key) && i < u32Size; i++)
2221 {
2222 pu8RSAKey[i] = p[i];
2223 }
2224
2225 return TRUE;
2226 }
2227
2228
HAL_CA_OTP_SetDebugPortPassword(CA_DEBUG_PORT eDebugPort,const MS_U8 * pu8Password,MS_U32 u32Size)2229 MS_BOOL HAL_CA_OTP_SetDebugPortPassword(CA_DEBUG_PORT eDebugPort, const MS_U8 *pu8Password, MS_U32 u32Size)
2230 {
2231
2232 MS_U32 pwd[4] = {0};
2233 MS_U32 i, j, u32Addr;
2234 MS_U8 *p = (MS_U8 *)pwd;
2235
2236 switch(eDebugPort)
2237 {
2238 case E_CA_DEBUG_PORT_I2C:
2239 u32Addr = _HAL_CA_OTP_Addr[U_OTP_I2C_PWD].u32Addr;
2240 break;
2241 case E_CA_DEBUG_PORT_JTAG:
2242 u32Addr = _HAL_CA_OTP_Addr[U_OTP_EJTAG_PWD].u32Addr;
2243 break;
2244 case E_CA_DEBUG_PORT_SCAN:
2245 u32Addr = _HAL_CA_OTP_Addr[U_OTP_SCAN_PWD].u32Addr;
2246 break;
2247 default:
2248 return FALSE;
2249 }
2250 if(sizeof(pwd)>u32Size)
2251 {
2252 j = u32Size;
2253 }
2254 else
2255 {
2256 j=sizeof(pwd);
2257 }
2258
2259 for(i = 0; i < sizeof(pwd) && i < u32Size; i++)
2260 {
2261 p[i] = pu8Password[(j-1)-i]; // Array reverse, for user easy viewing
2262 }
2263
2264
2265 for(i = 0; i < 4; i++)
2266 {
2267 if(HAL_CA_OTP_Write(u32Addr,pwd[i]) == FALSE)
2268 {
2269 return FALSE;
2270 }
2271 u32Addr += 4;
2272 }
2273
2274 return TRUE;
2275 }
2276
HAL_CA_OTP_GetDebugPortPassword(CA_DEBUG_PORT eDebugPort,MS_U8 * pu8Password,MS_U32 u32Size)2277 MS_BOOL HAL_CA_OTP_GetDebugPortPassword(CA_DEBUG_PORT eDebugPort, MS_U8 *pu8Password, MS_U32 u32Size)
2278 {
2279 MS_U32 pwd[4] = {0};
2280 MS_U32 i, j, u32Addr;
2281 MS_U8 *p = (MS_U8 *)pwd;
2282
2283 switch(eDebugPort)
2284 {
2285 case E_CA_DEBUG_PORT_I2C:
2286 u32Addr = _HAL_CA_OTP_Addr[U_OTP_I2C_PWD].u32Addr;
2287 break;
2288 case E_CA_DEBUG_PORT_JTAG:
2289 u32Addr = _HAL_CA_OTP_Addr[U_OTP_EJTAG_PWD].u32Addr;
2290 break;
2291 case E_CA_DEBUG_PORT_SCAN:
2292 u32Addr = _HAL_CA_OTP_Addr[U_OTP_SCAN_PWD].u32Addr;
2293 break;
2294 default:
2295 return FALSE;
2296 }
2297 for(i = 0; i < 4; i++)
2298 {
2299 pwd[i] = HAL_CA_OTP_Read(u32Addr);
2300 u32Addr += 4;
2301 }
2302 if(sizeof(pwd)>u32Size)
2303 {
2304 j = u32Size;
2305 }
2306 else
2307 {
2308 j=sizeof(pwd);
2309 }
2310 for(i = 0; i < sizeof(pwd) &&i < u32Size; i++)
2311 {
2312 pu8Password[i] = p[(j-1)-i]; // Array reverse, for user easy viewing
2313 }
2314 return TRUE;
2315 }
2316
HAL_CA_MaxReservedSize(void)2317 MS_U32 HAL_CA_MaxReservedSize(void)
2318 {
2319 HAL_CA_DEBUG("Not Implement\n");
2320 return FALSE;
2321 }
2322
HAL_CA_OTP_WriteReserved(const MS_U8 * pu8RData,MS_U32 u32Size)2323 MS_BOOL HAL_CA_OTP_WriteReserved(const MS_U8 *pu8RData, MS_U32 u32Size)
2324 {
2325 MS_U32 u32rdata[32] = {0};
2326 MS_U32 i, u32Addr;
2327 MS_U32 u32ReservedSize = MAX_RESERVED_SIZE /16 ;
2328 MS_U8 *p = (MS_U8 *)u32rdata;
2329
2330 for(i = 0; i < sizeof(u32rdata) && i < u32Size; i++)
2331 {
2332 p[i] = pu8RData[i];
2333 }
2334
2335 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CA_reserved0].u32Addr;
2336 for(i = 0; i <u32ReservedSize; i++)
2337 {
2338 if(HAL_CA_OTP_Write(u32Addr,u32rdata[i]) == FALSE)
2339 {
2340 return FALSE;
2341 }
2342 u32Addr += 4;
2343 }
2344
2345 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CA_reserved1].u32Addr;
2346 for(i = u32ReservedSize; i < (2*u32ReservedSize); i++)
2347 {
2348 if(HAL_CA_OTP_Write(u32Addr,u32rdata[i]) == FALSE)
2349 {
2350 return FALSE;
2351 }
2352 u32Addr += 4;
2353 }
2354 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CA_reserved2].u32Addr;
2355 for(i = (2*u32ReservedSize); i < (3*u32ReservedSize); i++)
2356 {
2357 if(HAL_CA_OTP_Write(u32Addr,u32rdata[i]) == FALSE)
2358 {
2359 return FALSE;
2360 }
2361 u32Addr += 4;
2362 }
2363 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CA_reserved3].u32Addr;
2364 for(i = (3*u32ReservedSize); i < (4*u32ReservedSize); i++)
2365 {
2366 if(HAL_CA_OTP_Write(u32Addr,u32rdata[i]) == FALSE)
2367 {
2368 return FALSE;
2369 }
2370 u32Addr += 4;
2371 }
2372 return TRUE;
2373 }
2374
HAL_CA_OTP_ReadReserved(MS_U8 * pu8RData,MS_U32 u32Size)2375 MS_BOOL HAL_CA_OTP_ReadReserved(MS_U8 *pu8RData, MS_U32 u32Size)
2376 {
2377 MS_U32 u32rdata[32] = {0};
2378 MS_U32 i, u32Addr;
2379 MS_U32 u32ReservedSize = MAX_RESERVED_SIZE /16 ;
2380 MS_U8 *p = (MS_U8 *)u32rdata;
2381
2382 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CA_reserved0].u32Addr;
2383 for(i = 0; i < u32ReservedSize; i++)
2384 {
2385 u32rdata[i] = HAL_CA_OTP_Read(u32Addr);
2386 u32Addr += 4;
2387 }
2388 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CA_reserved1].u32Addr;
2389 for(i = u32ReservedSize; i < (2*u32ReservedSize); i++)
2390 {
2391 u32rdata[i] = HAL_CA_OTP_Read(u32Addr);
2392 u32Addr += 4;
2393 }
2394 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CA_reserved2].u32Addr;
2395 for(i = (2*u32ReservedSize); i < (3*u32ReservedSize); i++)
2396 {
2397 u32rdata[i] = HAL_CA_OTP_Read(u32Addr);
2398 u32Addr += 4;
2399 }
2400 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CA_reserved3].u32Addr;
2401 for(i = (3*u32ReservedSize); i < (4*u32ReservedSize); i++)
2402 {
2403 u32rdata[i] = HAL_CA_OTP_Read(u32Addr);
2404 u32Addr += 4;
2405 }
2406
2407 for(i = 0; i < sizeof(u32rdata) && i < u32Size; i++)
2408 {
2409 pu8RData[i] = p[i];
2410 }
2411
2412 return TRUE;
2413 }
2414