1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
5 // All software, firmware and related documentation herein ("MStar Software") are
6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by
7 // law, including, but not limited to, copyright law and international treaties.
8 // Any use, modification, reproduction, retransmission, or republication of all
9 // or part of MStar Software is expressly prohibited, unless prior written
10 // permission has been granted by MStar.
11 //
12 // By accessing, browsing and/or using MStar Software, you acknowledge that you
13 // have read, understood, and agree, to be bound by below terms ("Terms") and to
14 // comply with all applicable laws and regulations:
15 //
16 // 1. MStar shall retain any and all right, ownership and interest to MStar
17 // Software and any modification/derivatives thereof.
18 // No right, ownership, or interest to MStar Software and any
19 // modification/derivatives thereof is transferred to you under Terms.
20 //
21 // 2. You understand that MStar Software might include, incorporate or be
22 // supplied together with third party`s software and the use of MStar
23 // Software may require additional licenses from third parties.
24 // Therefore, you hereby agree it is your sole responsibility to separately
25 // obtain any and all third party right and license necessary for your use of
26 // such third party`s software.
27 //
28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as
29 // MStar`s confidential information and you agree to keep MStar`s
30 // confidential information in strictest confidence and not disclose to any
31 // third party.
32 //
33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any
34 // kind. Any warranties are hereby expressly disclaimed by MStar, including
35 // without limitation, any warranties of merchantability, non-infringement of
36 // intellectual property rights, fitness for a particular purpose, error free
37 // and in conformity with any international standard. You agree to waive any
38 // claim against MStar for any loss, damage, cost or expense that you may
39 // incur related to your use of MStar Software.
40 // In no event shall MStar be liable for any direct, indirect, incidental or
41 // consequential damages, including without limitation, lost of profit or
42 // revenues, lost or damage of data, and unauthorized system use.
43 // You agree that this Section 4 shall still apply without being affected
44 // even if MStar Software has been modified by MStar in accordance with your
45 // request or instruction for your use, except otherwise agreed by both
46 // parties in writing.
47 //
48 // 5. If requested, MStar may from time to time provide technical supports or
49 // services in relation with MStar Software to you for your use of
50 // MStar Software in conjunction with your or your customer`s product
51 // ("Services").
52 // You understand and agree that, except otherwise agreed by both parties in
53 // writing, Services are provided on an "AS IS" basis and the warranty
54 // disclaimer set forth in Section 4 above shall apply.
55 //
56 // 6. Nothing contained herein shall be construed as by implication, estoppels
57 // or otherwise:
58 // (a) conferring any license or right to use MStar name, trademark, service
59 // mark, symbol or any other identification;
60 // (b) obligating MStar or any of its affiliates to furnish any person,
61 // including without limitation, you and your customers, any assistance
62 // of any kind whatsoever, or any information; or
63 // (c) conferring any license or right under any intellectual property right.
64 //
65 // 7. These terms shall be governed by and construed in accordance with the laws
66 // of Taiwan, R.O.C., excluding its conflict of law rules.
67 // Any and all dispute arising out hereof or related hereto shall be finally
68 // settled by arbitration referred to the Chinese Arbitration Association,
69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration
70 // Rules of the Association by three (3) arbitrators appointed in accordance
71 // with the said Rules.
72 // The place of arbitration shall be in Taipei, Taiwan and the language shall
73 // be English.
74 // The arbitration award shall be final and binding to both parties.
75 //
76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2006-2009 MStar Semiconductor, Inc.
81 // All rights reserved.
82 //
83 // Unless otherwise stipulated in writing, any and all information contained
84 // herein regardless in any format shall remain the sole proprietary of
85 // MStar Semiconductor Inc. and be kept in strict confidence
86 // ("MStar Confidential Information") by the recipient.
87 // Any unauthorized act including without limitation unauthorized disclosure,
88 // copying, use, reproduction, sale, distribution, modification, disassembling,
89 // reverse engineering and compiling of the contents of MStar Confidential
90 // Information is unlawful and strictly prohibited. MStar hereby reserves the
91 // rights to any and all damages, losses, costs and expenses resulting therefrom.
92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95 ////////////////////////////////////////////////////////////////////////////////////////////////////
96 // file halCA.c
97 // @brief CA HAL
98 // @author MStar Semiconductor,Inc.
99 ////////////////////////////////////////////////////////////////////////////////////////////////////
100
101 #include "MsCommon.h"
102 #include "regCA.h"
103 #include "drvCA.h"
104 #include "halCA.h"
105
106 #include <drvSYS.h>
107 #include <string.h>
108
109 // #undef MS_DEBUG_MSG
110 // #define MS_DEBUG_MSG(x) x
111
112 //--------------------------------------------------------------------------------------------------
113 // Driver Compiler Option
114 //--------------------------------------------------------------------------------------------------
115
116 //--------------------------------------------------------------------------------------------------
117 // Global Definition
118 //--------------------------------------------------------------------------------------------------
119 #define MAX_RESERVED_SIZE 128
120
121 //--------------------------------------------------------------------------------------------------
122 // CA Hardware Abstraction Layer
123 //--------------------------------------------------------------------------------------------------
124 static MS_VIRT _u32REGBase = 0;
125 static MS_VIRT _u32REGPMBase = 0;
126 static MS_VIRT _u32REG_OTP_Base = 0;
127 static MS_VIRT _u32REG_RSA_Base = 0;
128
129 #define REG16(addr) (*(volatile unsigned short *)(_u32REGBase + (addr)))
130 #define REG16_WRITE(addr, value, mask) do { REG16(addr) = (REG16(addr) & ~(mask)) | ((value) & (mask)); } while(0)
131
132 #define REG32(addr) (*(volatile unsigned *)(_u32REGBase + (addr)))
133 #define REG32_WRITE(addr, value, mask) do { REG32(addr) = (REG32(addr) & ~(mask)) | ((value) & (mask)); } while(0)
134
135 #define REG32_PM(addr) (*(volatile unsigned *)(_u32REGPMBase + (addr)))
136
137 #define REG16_PM(addr) (*(volatile unsigned short *)(_u32REGPMBase + (addr)))
138
139 #ifdef CA_NO_PRINTF
140 #define HAL_CA_DEBUG(fmt, args...)
141 #else
142 #define HAL_CA_DEBUG(fmt, args...) do{ \
143 printf("[%s][%d]"fmt"\n", __FUNCTION__, __LINE__, ## args);}\
144 while(0)
145 #endif
bitmask(unsigned hi,unsigned lo)146 static unsigned bitmask(unsigned hi, unsigned lo)
147 {
148 unsigned x, s = hi - lo + 1;
149 // printf("hi=%d lo=%d size=%d\n", hi, lo, s);
150
151 if(s >= sizeof(unsigned) * 8)
152 x = (unsigned)-1;
153 else
154 x = (1U << s) - 1;
155 return x << lo;
156 }
157
158 struct {
159 MS_U32 u32Addr;
160 MS_U32 u32Hi;
161 MS_U32 u32Lo;
162 } _HAL_CA_OTP_Addr[] = {
163 //Parse from Kano_otp_mapping_v0.93(20151127).xlsx
164 [U_OTP_CA_reserved0] = {0x003500, 255, 0},
165 [U_OTP_CA_reserved1] = {0x003520, 255, 0},
166 [U_OTP_CA_reserved2] = {0x003540, 255, 0},
167 [U_OTP_CA_reserved3] = {0x003560, 255, 0},
168 [U_OTP_CA_reserved4] = {0x003580, 255, 0},
169 [U_OTP_CA_reserved5] = {0x0035A0, 255, 0},
170 [U_OTP_CA_reserved6] = {0x0035C0, 255, 0},
171 [U_OTP_CA_reserved7] = {0x0035E0, 255, 0},
172 [U_OTP_CA_reserved8] = {0x003600, 255, 0},
173 [U_OTP_CA_reserved9] = {0x003620, 255, 0},
174 [U_OTP_CA_reserved10] = {0x003640, 255, 0},
175 [U_OTP_CA_reserved11] = {0x003660, 255, 0},
176 [U_OTP_CA_reserved12] = {0x003680, 255, 0},
177 [U_OTP_CA_reserved13] = {0x0036A0, 255, 0},
178 [U_OTP_CA_reserved14] = {0x0036C0, 255, 0},
179 [U_OTP_CA_reserved15] = {0x0036E0, 255, 0},
180 [U_OTP_Chip_Extension_ID] = {0x003700, 127, 0},
181 [U_OTP_PVConfiguration] = {0x003710, 23, 0},
182 [U_OTP_EncryptLoader_Key_sel] = {0x003710, 27, 24},
183 [U_OTP_EncryptLoader_KL_level] = {0x003710, 29, 28},
184 [U_OTP_SW_Reserved0] = {0x003710, 31, 30},
185 [U_OTP_EncryptLoader_ForceEnc] = {0x003714, 1, 0},
186 [U_OTP_SW_Reserved1] = {0x003714, 31, 2},
187 [U_OTP_HASH0_VER_REF] = {0x003718, 31, 0},
188 [U_OTP_HASH1_VER_REF] = {0x00371C, 31, 0},
189 [U_OTP_HASH2_VER_REF] = {0x003720, 31, 0},
190 [U_OTP_SW_Reserved2] = {0x003724, 31, 0},
191 [U_OTP_Versioning] = {0x003728, 511, 0},
192 [U_OTP_Preenablement_0] = {0x003768, 31, 0},
193 [U_OTP_Preenablement_1] = {0x00376C, 31, 0},
194 [U_OTP_Preenablement_2] = {0x003770, 31, 0},
195 [U_OTP_Preenablement_3] = {0x003774, 31, 0},
196 [U_OTP_Preenablement_4] = {0x003778, 31, 0},
197 [U_OTP_Preenablement_5] = {0x00377C, 31, 0},
198 [U_OTP_Preenablement_6] = {0x003780, 31, 0},
199 [U_OTP_Preenablement_7] = {0x003784, 31, 0},
200 [U_OTP_CAdata_0] = {0x003788, 31, 0},
201 [U_OTP_CAdata_1] = {0x00378C, 31, 0},
202 [U_OTP_CAdata_2] = {0x003790, 31, 0},
203 [U_OTP_CAdata_3] = {0x003794, 31, 0},
204 [U_OTP_CAdata_4] = {0x003798, 31, 0},
205 [U_OTP_CAdata_5] = {0x00379C, 31, 0},
206 [U_OTP_CAdata_6] = {0x0037A0, 31, 0},
207 [U_OTP_CAdata_7] = {0x0037A4, 31, 0},
208 [U_OTP_CAdata_8] = {0x0037A8, 31, 0},
209 [U_OTP_CAdata_9] = {0x0037AC, 31, 0},
210 [U_OTP_CAdata_10] = {0x0037B0, 31, 0},
211 [U_OTP_CAdata_11] = {0x0037B4, 31, 0},
212 [U_OTP_CAdata_12] = {0x0037B8, 31, 0},
213 [U_OTP_CAdata_13] = {0x0037BC, 31, 0},
214 [U_OTP_CAdata_14] = {0x0037C0, 31, 0},
215 [U_OTP_CAdata_15] = {0x0037C4, 31, 0},
216 [U_OTP_CAdata_16] = {0x0037C8, 31, 0},
217 [U_OTP_CAdata_17] = {0x0037CC, 31, 0},
218 [U_OTP_CAdata_18] = {0x0037D0, 31, 0},
219 [U_OTP_CAdata_19] = {0x0037D4, 31, 0},
220 [U_OTP_CAdata_20] = {0x0037D8, 31, 0},
221 [U_OTP_CAdata_21] = {0x0037DC, 31, 0},
222 [U_OTP_CAdata_22] = {0x0037E0, 31, 0},
223 [U_OTP_CAdata_23] = {0x0037E4, 31, 0},
224 [U_OTP_CAdata_24] = {0x0037E8, 31, 0},
225 [U_OTP_CAdata_25] = {0x0037EC, 31, 0},
226 [U_OTP_CAdata_26] = {0x0037F0, 31, 0},
227 [U_OTP_CAdata_27] = {0x0037F4, 31, 0},
228 [U_OTP_CAdata_28] = {0x0037F8, 31, 0},
229 [U_OTP_CAdata_29] = {0x0037FC, 31, 0},
230 [U_OTP_CAdata_30] = {0x003800, 31, 0},
231 [U_OTP_CAdata_31] = {0x003804, 31, 0},
232 [U_OTP_CAdata_32] = {0x003808, 31, 0},
233 [U_OTP_CAdata_33] = {0x00380C, 31, 0},
234 [U_OTP_CAdata_34] = {0x003810, 31, 0},
235 [U_OTP_CAdata_35] = {0x003814, 31, 0},
236 [U_OTP_CAdata_36] = {0x003818, 31, 0},
237 [U_OTP_CAdata_37] = {0x00381C, 31, 0},
238 [U_OTP_forbid_SCPU2DRAM] = {0x003820, 3, 0},
239 [U_OTP_forbid_SCPUQMEM_to_DRAM] = {0x003820, 7, 4},
240 [U_OTP_forbid_CryptoDMA_keyslot_QMEM] = {0x003820, 11, 8},
241 [U_OTP_forbid_SCPU2UART] = {0x003820, 15, 12},
242 [U_OTP_IXSC_config1] = {0x003820, 19, 16},
243 [U_OTP_IXSC_config2] = {0x003820, 23, 20},
244 [U_OTP_IXSC_config3] = {0x003820, 27, 24},
245 [U_OTP_IXSC_config4] = {0x003820, 31, 28},
246 [U_OTP_LockWord_Preenablement_0_W] = {0x003824, 1, 0},
247 [U_OTP_LockWord_Preenablement_1_W] = {0x003824, 3, 2},
248 [U_OTP_LockWord_Preenablement_2_W] = {0x003824, 5, 4},
249 [U_OTP_LockWord_Preenablement_3_W] = {0x003824, 7, 6},
250 [U_OTP_LockWord_Preenablement_4_W] = {0x003824, 9, 8},
251 [U_OTP_LockWord_Preenablement_5_W] = {0x003824, 11, 10},
252 [U_OTP_LockWord_Preenablement_6_W] = {0x003824, 13, 12},
253 [U_OTP_LockWord_Preenablement_7_W] = {0x003824, 15, 14},
254 [U_OTP_Test_Switch] = {0x003824, 23, 16},
255 [U_OTP_IXSC_Reserved0] = {0x003824, 31, 24},
256 [U_OTP_NOCS3_00] = {0x003828, 383, 0},
257 [U_OTP_NOCS3_01] = {0x003858, 383, 0},
258 [U_OTP_NOCS3_02] = {0x003888, 127, 0},
259 [U_OTP_NOCS3_03] = {0x003898, 127, 0},
260 [U_OTP_MSID] = {0x0038A8, 31, 0},
261 [U_OTP_CFG_STB_CA_SN] = {0x0038AC, 31, 0},
262 [U_OTP_RSA_0] = {0x0038B0, 2047, 0},
263 [U_OTP_RSA_1] = {0x0039B0, 2047, 0},
264 [U_OTP_RSA_0_integrity_chk] = {0x003AB0, 1, 0},
265 [U_OTP_RSA_1_integrity_chk] = {0x003AB0, 3, 2},
266 [U_OTP_ena_ACPUUseHWRSAKey] = {0x003AB0, 7, 4},
267 [U_OTP_forbid_ACPUReadRSAKey0] = {0x003AB0, 10, 8},
268 [U_OTP_forbid_ACPUReadRSAKey1] = {0x003AB0, 13, 11},
269 [U_OTP_forbid_ACPUWrite_Versioning] = {0x003AB0, 15, 14},
270 [U_OTP_forbid_ACPURead_Versioning] = {0x003AB0, 17, 16},
271 [U_OTP_RSA_Reserved0] = {0x003AB0, 31, 18},
272 [U_OTP_RSA_0_CRC] = {0x003AB4, 15, 0},
273 [U_OTP_RSA_1_CRC] = {0x003AB4, 31, 16},
274 [U_OTP_PGMask0] = {0x003AB8, 31, 0},
275 [U_OTP_PGMask1] = {0x003ABC, 31, 0},
276 [U_OTP_PGMask2] = {0x003AC0, 31, 0},
277 [U_OTP_PGMask3] = {0x003AC4, 31, 0},
278 [U_OTP_PGMask4] = {0x003AC8, 31, 0},
279 [U_OTP_PGMask5] = {0x003ACC, 31, 0},
280 [U_OTP_PGMask6] = {0x003AD0, 31, 0},
281 [U_OTP_PGMask7] = {0x003AD4, 31, 0},
282 [U_OTP_PGMask8] = {0x003AD8, 31, 0},
283 [U_OTP_PGMask9] = {0x003ADC, 31, 0},
284 [U_OTP_PGMask10] = {0x003AE0, 31, 0},
285 [U_OTP_PGMask11] = {0x003AE4, 31, 0},
286 [U_OTP_PGMask12] = {0x003AE8, 31, 0},
287 [U_OTP_PGMask13] = {0x003AEC, 31, 0},
288 [U_OTP_PGMask14] = {0x003AF0, 31, 0},
289 [U_OTP_PGMask15] = {0x003AF4, 31, 0},
290 [U_OTP_PGMask16] = {0x003AF8, 31, 0},
291 [U_OTP_PGMask17] = {0x003AFC, 31, 0},
292 [U_OTP_v_PubOtpOID] = {0x003B00, 15, 0},
293 [U_OTP_NDS_Reserved0] = {0x003B00, 31, 16},
294 [U_OTP_v_PubOtpVID] = {0x003B04, 15, 0},
295 [U_OTP_NDS_Reserved1] = {0x003B04, 31, 16},
296 [U_OTP_v_PubOtpGP] = {0x003B08, 15, 0},
297 [U_OTP_LockWord_GP_group_W] = {0x003B08, 31, 16},
298 [U_OTP_v_PubOtpBID] = {0x003B0C, 3, 0},
299 [U_OTP_NDS_Reserved2] = {0x003B0C, 31, 4},
300 [U_OTP_v_PubOtpRsaIndex] = {0x003B10, 3, 0},
301 [U_OTP_NDS_Reserved3] = {0x003B10, 31, 4},
302 [U_OTP_v_PubOtpMinConfVer] = {0x003B14, 7, 0},
303 [U_OTP_NDS_Reserved4] = {0x003B14, 31, 8},
304 [U_OTP_VenderConstSel] = {0x003B18, 2, 0},
305 [U_OTP_NDS_Reserved5] = {0x003B18, 31, 3},
306 [U_OTP_LockWord_NDS_Key1] = {0x003B1C, 2, 0},
307 [U_OTP_LockWord_NDS_Key2] = {0x003B1C, 5, 3},
308 [U_OTP_LockWord_NDS_Key3] = {0x003B1C, 8, 6},
309 [U_OTP_LockWord_NDS_Key4] = {0x003B1C, 11, 9},
310 [U_OTP_LockWord_NDS_Key5] = {0x003B1C, 14, 12},
311 [U_OTP_LockWord_NDS_Key6] = {0x003B1C, 17, 15},
312 [U_OTP_LockWord_NDS_Key7] = {0x003B1C, 20, 18},
313 [U_OTP_LockWord_NDS_Key8] = {0x003B1C, 23, 21},
314 [U_OTP_NDSKeyValid] = {0x003B1C, 31, 24},
315 [U_OTP_forbid_NSK_wr_sck] = {0x003B20, 7, 0},
316 [U_OTP_UseCheckSum] = {0x003B20, 15, 8},
317 [U_OTP_allow_NDSKey_BlankChk] = {0x003B20, 17, 16},
318 [U_OTP_allow_ProgFail_RuinNDSKey] = {0x003B20, 19, 18},
319 [U_OTP_allow_NDSReadKeyWait200ms] = {0x003B20, 21, 20},
320 [U_OTP_allow_ReadErrorRstOtp] = {0x003B20, 23, 22},
321 [U_OTP_allow_illegalNDSFlagChk] = {0x003B20, 27, 24},
322 [U_OTP_allow_Rst_NDS_SCFlag_ParityFail] = {0x003B20, 31, 28},
323 [U_OTP_ena_ACPUUseNSK2] = {0x003B24, 3, 0},
324 [U_OTP_ena_DBUSUseNSK2] = {0x003B24, 7, 4},
325 [U_OTP_ena_ForceOneMilSec] = {0x003B24, 11, 8},
326 [U_OTP_allow_SCCheck] = {0x003B24, 15, 12},
327 [U_OTP_ena_TestRCFreq] = {0x003B24, 19, 16},
328 [U_OTP_ena_SWRN] = {0x003B24, 23, 20},
329 [U_OTP_ena_NSKSeedPRNG] = {0x003B24, 27, 24},
330 [U_OTP_OTPWritePWDProtect] = {0x003B24, 31, 28},
331 [U_OTP_NDS_keysel] = {0x003B28, 5, 0},
332 [U_OTP_allow_NSK2_PWD_Mode] = {0x003B28, 7, 6},
333 [U_OTP_ena_EMMFilter] = {0x003B28, 11, 8},
334 [U_OTP_ena_TestGenIN] = {0x003B28, 15, 12},
335 [U_OTP_RCFreq_map] = {0x003B28, 20, 16},
336 [U_OTP_NDS_Reserved6] = {0x003B28, 31, 21},
337 [U_OTP_allow_SkipBadNVBit] = {0x003B2C, 1, 0},
338 [U_OTP_allow_NDSSC_ReadFail_BadPkt] = {0x003B2C, 3, 2},
339 [U_OTP_allow_RANDOM_keybus] = {0x003B2C, 5, 4},
340 [U_OTP_allow_RANDOM_byteacc] = {0x003B2C, 7, 6},
341 [U_OTP_allow_NDS_Rd55AA] = {0x003B2C, 9, 8},
342 [U_OTP_allow_NDS_Parity_chk] = {0x003B2C, 11, 10},
343 [U_OTP_allow_NDS_KeyRd55AA] = {0x003B2C, 13, 12},
344 [U_OTP_forbid_OTPBuiltInTest] = {0x003B2C, 15, 14},
345 [U_OTP_forbid_Kilo_ProgRepair] = {0x003B2C, 17, 16},
346 [U_OTP_NDS_Reserved7] = {0x003B2C, 31, 18},
347 [U_OTP_NVCOUNT] = {0x003B30, 1023, 0},
348 [U_OTP_NDS_SecretKey1] = {0x003BB0, 127, 0},
349 [U_OTP_NDS_SecretKey2] = {0x003BC0, 127, 0},
350 [U_OTP_NDS_SecretKey3] = {0x003BD0, 127, 0},
351 [U_OTP_NDS_SecretKey4] = {0x003BE0, 127, 0},
352 [U_OTP_NDS_SecretKey5] = {0x003BF0, 127, 0},
353 [U_OTP_NDS_SecretKey6] = {0x003C00, 127, 0},
354 [U_OTP_NDS_SecretKey7] = {0x003C10, 127, 0},
355 [U_OTP_NDS_SecretKey8] = {0x003C20, 127, 0},
356 [U_OTP_NDSKey1Chksum] = {0x003C30, 7, 0},
357 [U_OTP_NDSKey1Tag] = {0x003C30, 15, 8},
358 [U_OTP_NDSKey2Chksum] = {0x003C30, 23, 16},
359 [U_OTP_NDSKey2Tag] = {0x003C30, 31, 24},
360 [U_OTP_NDSKey3Chksum] = {0x003C34, 7, 0},
361 [U_OTP_NDSKey3Tag] = {0x003C34, 15, 8},
362 [U_OTP_NDSKey4Chksum] = {0x003C34, 23, 16},
363 [U_OTP_NDSKey4Tag] = {0x003C34, 31, 24},
364 [U_OTP_NDSKey5Chksum] = {0x003C38, 7, 0},
365 [U_OTP_NDSKey5Tag] = {0x003C38, 15, 8},
366 [U_OTP_NDSKey6Chksum] = {0x003C38, 23, 16},
367 [U_OTP_NDSKey6Tag] = {0x003C38, 31, 24},
368 [U_OTP_NDSKey7Chksum] = {0x003C3C, 7, 0},
369 [U_OTP_NDSKey7Tag] = {0x003C3C, 15, 8},
370 [U_OTP_NDSKey8Chksum] = {0x003C3C, 23, 16},
371 [U_OTP_NDSKey8Tag] = {0x003C3C, 31, 24},
372 [U_OTP_NDS_Key1_CRC] = {0x003C40, 15, 0},
373 [U_OTP_NDS_Key2_CRC] = {0x003C40, 31, 16},
374 [U_OTP_NDS_Key3_CRC] = {0x003C44, 15, 0},
375 [U_OTP_NDS_Key4_CRC] = {0x003C44, 31, 16},
376 [U_OTP_NDS_Key5_CRC] = {0x003C48, 15, 0},
377 [U_OTP_NDS_Key6_CRC] = {0x003C48, 31, 16},
378 [U_OTP_NDS_Key7_CRC] = {0x003C4C, 15, 0},
379 [U_OTP_NDS_Key8_CRC] = {0x003C4C, 31, 16},
380 [U_OTP_NDS_ESCK_Key1_obfuscation] = {0x003C50, 1, 0},
381 [U_OTP_NDS_Key1_integrity_chk] = {0x003C50, 3, 2},
382 [U_OTP_NDS_ESCK_Key2_obfuscation] = {0x003C50, 5, 4},
383 [U_OTP_NDS_Key2_integrity_chk] = {0x003C50, 7, 6},
384 [U_OTP_NDS_ESCK_Key3_obfuscation] = {0x003C50, 9, 8},
385 [U_OTP_NDS_Key3_integrity_chk] = {0x003C50, 11, 10},
386 [U_OTP_NDS_ESCK_Key4_obfuscation] = {0x003C50, 13, 12},
387 [U_OTP_NDS_Key4_integrity_chk] = {0x003C50, 15, 14},
388 [U_OTP_NDS_ESCK_Key5_obfuscation] = {0x003C50, 17, 16},
389 [U_OTP_NDS_Key5_integrity_chk] = {0x003C50, 19, 18},
390 [U_OTP_NDS_ESCK_Key6_obfuscation] = {0x003C50, 21, 20},
391 [U_OTP_NDS_Key6_integrity_chk] = {0x003C50, 23, 22},
392 [U_OTP_NDS_ESCK_Key7_obfuscation] = {0x003C50, 25, 24},
393 [U_OTP_NDS_Key7_integrity_chk] = {0x003C50, 27, 26},
394 [U_OTP_NDS_ESCK_Key8_obfuscation] = {0x003C50, 29, 28},
395 [U_OTP_NDS_Key8_integrity_chk] = {0x003C50, 31, 30},
396 [U_OTP_EJTAG_MODE_Parity_bit] = {0x003C54, 0, 0},
397 [U_OTP_I2C_MODE_Parity_bit] = {0x003C54, 1, 1},
398 [U_OTP_SCAN_MODE_Parity_bit] = {0x003C54, 2, 2},
399 [U_OTP_VenderConstSel_Parity_bit] = {0x003C54, 3, 3},
400 [U_OTP_v_PubOtpRsaIndex_Parity_bit] = {0x003C54, 4, 4},
401 [U_OTP_NDS_ESCK_Key1_obfuscation_Parity_bit] = {0x003C54, 5, 5},
402 [U_OTP_NDS_ESCK_Key2_obfuscation_Parity_bit] = {0x003C54, 6, 6},
403 [U_OTP_NDS_ESCK_Key3_obfuscation_Parity_bit] = {0x003C54, 7, 7},
404 [U_OTP_NDS_ESCK_Key4_obfuscation_Parity_bit] = {0x003C54, 8, 8},
405 [U_OTP_NDS_ESCK_Key5_obfuscation_Parity_bit] = {0x003C54, 9, 9},
406 [U_OTP_NDS_ESCK_Key6_obfuscation_Parity_bit] = {0x003C54, 10, 10},
407 [U_OTP_NDS_ESCK_Key7_obfuscation_Parity_bit] = {0x003C54, 11, 11},
408 [U_OTP_NDS_ESCK_Key8_obfuscation_Parity_bit] = {0x003C54, 12, 12},
409 [U_OTP_allow_ReadErrorRstOtp_Parity_bit] = {0x003C54, 13, 13},
410 [U_OTP_ena_ACPUUseNSK2_Parity_bit] = {0x003C54, 14, 14},
411 [U_OTP_BootMode_Parity_bit] = {0x003C54, 15, 15},
412 [U_OTP_ena_ACPU2KT_Parity_bit] = {0x003C54, 16, 16},
413 [U_OTP_ena_EMMFilter_Parity_bit] = {0x003C54, 17, 17},
414 [U_OTP_allow_NDS_Rd55AA_Parity_bit] = {0x003C54, 18, 18},
415 [U_OTP_forbid_OTPBuiltInTest_Parity_bit] = {0x003C54, 19, 19},
416 [U_OTP_allow_NSK_RNG_ROSC_Parity_bit] = {0x003C54, 20, 20},
417 [U_OTP_SecretAreaEnable_Parity_bit] = {0x003C54, 21, 21},
418 [U_OTP_forbid_SW_SPSD_Key_Parity_bit] = {0x003C54, 22, 22},
419 [U_OTP_allow_OTP_BgCRC_Parity_bit] = {0x003C54, 23, 23},
420 [U_OTP_forbid_USBSlaveMode_Parity_bit] = {0x003C54, 24, 24},
421 [U_OTP_OTPWritePWDProtect_Parity_bit] = {0x003C54, 25, 25},
422 [U_OTP_ena_NSK2_Parity_bit] = {0x003C54, 26, 26},
423 [U_OTP_NDS_Reserved8] = {0x003C54, 31, 27},
424 [U_OTP_ena_ESAAlgo_invalidate] = {0x003C58, 3, 0},
425 [U_OTP_ena_LocalAlgo_Invalidate] = {0x003C58, 7, 4},
426 [U_OTP_ContentProtEn] = {0x003C58, 11, 8},
427 [U_OTP_concurrency_configuration] = {0x003C58, 13, 12},
428 [U_OTP_allow_NSK_RNG_ROSC] = {0x003C58, 15, 14},
429 [U_OTP_nds_fc_disable] = {0x003C58, 16, 16},
430 [U_OTP_NDS_CPNR0_sel] = {0x003C58, 17, 17},
431 [U_OTP_NDS_CPNR_off] = {0x003C58, 18, 18},
432 [U_OTP_NDS_Reserved9] = {0x003C58, 31, 19},
433 [U_OTP_PM51_ST_ADDR] = {0x003C5C, 11, 0},
434 [U_OTP_PM51_ED_ADDR] = {0x003C5C, 23, 12},
435 [U_OTP_forbid_PM51ReadOTP] = {0x003C5C, 25, 24},
436 [U_OTP_forbid_PM51WriteOTP] = {0x003C5C, 27, 26},
437 [U_OTP_allow_PM51] = {0x003C5C, 29, 28},
438 [U_OTP_PM51_SW_R2] = {0x003C5C, 31, 30},
439 [U_OTP_forbid_CLK_SEED_TEST] = {0x003C60, 0, 0},
440 [U_OTP_MOBF_TOP_use_DES] = {0x003C60, 1, 1},
441 [U_OTP_OBFUSCATEVideoStream] = {0x003C60, 3, 2},
442 [U_OTP_forbid_EJTAG_Pinshare] = {0x003C60, 5, 4},
443 [U_OTP_allow_clear_sram] = {0x003C60, 6, 6},
444 [U_OTP_forbid_dft_md_sram] = {0x003C60, 7, 7},
445 [U_OTP_LINK_ISOEN2GPIO4] = {0x003C60, 8, 8},
446 [U_OTP_PM_SLEEP_WR_PROT_EN] = {0x003C60, 9, 9},
447 [U_OTP_PWR_HW_RST_MODE_EN] = {0x003C60, 10, 10},
448 [U_OTP_ISOC_TST_DIG_EN_GATE] = {0x003C60, 11, 11},
449 [U_OTP_OTHERS_Reserved0] = {0x003C60, 15, 12},
450 [U_OTP_Rsv_Feature] = {0x003C60, 31, 16},
451 [U_OTP_forbid_CA_MCM] = {0x003C64, 2, 0},
452 [U_OTP_forbid_DIAMOND_PMU] = {0x003C64, 5, 3},
453 [U_OTP_allow_force_dual_core] = {0x003C64, 6, 6},
454 [U_OTP_disable_jpi] = {0x003C64, 7, 7},
455 [U_OTP_forbid_DIG_PMU] = {0x003C64, 10, 8},
456 [U_OTP_forbid_WHOLECHIP_alive_when_NOCORE_alive] = {0x003C64, 13, 11},
457 [U_OTP_OTHERS_Reserved2] = {0x003C64, 15, 14},
458 [U_OTP_allow_CORE0_always_alive] = {0x003C64, 18, 16},
459 [U_OTP_allow_NONCORE0_default_reset] = {0x003C64, 21, 19},
460 [U_OTP_pwrgd_int_en] = {0x003C64, 22, 22},
461 [U_OTP_OTHERS_Reserved3] = {0x003C64, 31, 23},
462 [U_OTP_LOGICBIST_SCAN_OUT_CRC32] = {0x003C68, 31, 0},
463 [U_OTP_OTHERS_Reserved4] = {0x003C6C, 31, 0},
464 [U_OTP_RC_OPTION] = {0x003C70, 7, 0},
465 [U_OTP_RC_OPTION_EN] = {0x003C70, 8, 8},
466 [U_OTP_GCR_TRVBG] = {0x003C70, 14, 9},
467 [U_OTP_OTHERS_Reserved5] = {0x003C70, 15, 15},
468 [U_OTP_TEST_Status_TE] = {0x003C70, 23, 16},
469 [U_OTP_TEST_Status] = {0x003C70, 31, 24},
470 [U_OTP_ena_PVRNS2S] = {0x003C74, 3, 0},
471 [U_OTP_ena_PVRS2NS] = {0x003C74, 7, 4},
472 [U_OTP_ena_PlayBackRec0] = {0x003C74, 11, 8},
473 [U_OTP_ena_PlayBackRec1] = {0x003C74, 15, 12},
474 [U_OTP_ena_PlayBackRec2] = {0x003C74, 19, 16},
475 [U_OTP_ena_PlayBackRec3] = {0x003C74, 23, 20},
476 [U_OTP_ena_PlayBackRec4] = {0x003C74, 27, 24},
477 [U_OTP_ena_PlayBackRec5] = {0x003C74, 31, 28},
478 [U_OTP_ena_PVR_secure_protect_0] = {0x003C78, 3, 0},
479 [U_OTP_ena_PVR_secure_protect_1] = {0x003C78, 7, 4},
480 [U_OTP_ena_VQ_secure_protect_0] = {0x003C78, 11, 8},
481 [U_OTP_TSP_Reserved0] = {0x003C78, 15, 12},
482 [U_OTP_dis_TSO] = {0x003C78, 19, 16},
483 [U_OTP_ena_TS2TSO_0] = {0x003C78, 23, 20},
484 [U_OTP_ena_TS2TSO_1] = {0x003C78, 27, 24},
485 [U_OTP_ena_TSO_SecRange] = {0x003C78, 31, 28},
486 [U_OTP_CAVIDEnforcedTS0] = {0x003C7C, 5, 0},
487 [U_OTP_CAVIDEnforcedTS1] = {0x003C7C, 11, 6},
488 [U_OTP_CAVIDEnforcedTS2] = {0x003C7C, 17, 12},
489 [U_OTP_CAVIDEnforcedTS3] = {0x003C7C, 23, 18},
490 [U_OTP_CAVIDEnforcedTS4] = {0x003C7C, 29, 24},
491 [U_OTP_TSP_Reserved1] = {0x003C7C, 31, 30},
492 [U_OTP_CAVIDEnforcedTS5] = {0x003C80, 5, 0},
493 [U_OTP_ForbidAVtoSec] = {0x003C80, 6, 6},
494 [U_OTP_TSP_Reserved2] = {0x003C80, 7, 7},
495 [U_OTP_dis_clear_stream_to_PVR] = {0x003C80, 11, 8},
496 [U_OTP_forbid_SW_SPSD_Key] = {0x003C80, 13, 12},
497 [U_OTP_forbid_KL_SPSD_Key] = {0x003C80, 15, 14},
498 [U_OTP_allow_TSPCPUCodeProt] = {0x003C80, 17, 16},
499 [U_OTP_TSP_Reserved3] = {0x003C80, 31, 18},
500 [U_OTP_ena_KeyLadder_0_lock] = {0x003C84, 3, 0},
501 [U_OTP_ena_KeyLadder_1_lock] = {0x003C84, 7, 4},
502 [U_OTP_ena_NSK2_lock] = {0x003C84, 11, 8},
503 [U_OTP_ena_CERT_IP_lock] = {0x003C84, 15, 12},
504 [U_OTP_ena_DMA_lock] = {0x003C84, 19, 16},
505 [U_OTP_ena_SCPU_lock] = {0x003C84, 23, 20},
506 [U_OTP_Dlock_Reserved0] = {0x003C84, 31, 24},
507 [U_OTP_ena_ACPU2KT_lock] = {0x003C88, 3, 0},
508 [U_OTP_ena_NSK2KT_lock] = {0x003C88, 7, 4},
509 [U_OTP_ena_KL2KT_lock] = {0x003C88, 11, 8},
510 [U_OTP_ena_SCPU2KT_lock] = {0x003C88, 15, 12},
511 [U_OTP_ena_ACPU2DMA_lock] = {0x003C88, 19, 16},
512 [U_OTP_ena_DMA_DESBasedCipher_lock] = {0x003C88, 23, 20},
513 [U_OTP_Dlock_Reserved1] = {0x003C88, 31, 24},
514 [U_OTP_ena_LSACPCM_lock] = {0x003C8C, 3, 0},
515 [U_OTP_ena_AESBasedCipher_lock] = {0x003C8C, 7, 4},
516 [U_OTP_ena_DESBasedCipher_lock] = {0x003C8C, 11, 8},
517 [U_OTP_ena_3DESBasedCipher_lock] = {0x003C8C, 15, 12},
518 [U_OTP_ena_Multi2BasedCipher_lock] = {0x003C8C, 19, 16},
519 [U_OTP_ena_DVBCSA2ConfCipher_lock] = {0x003C8C, 23, 20},
520 [U_OTP_ena_DVBCSA2Cipher_lock] = {0x003C8C, 27, 24},
521 [U_OTP_ena_DVBCSA3BasedCipher_lock] = {0x003C8C, 31, 28},
522 [U_OTP_dis_kl0_hostkey_lock] = {0x003C90, 3, 0},
523 [U_OTP_dis_kl1_hostkey_lock] = {0x003C90, 7, 4},
524 [U_OTP_NDSKeyValid_lock] = {0x003C90, 11, 8},
525 [U_OTP_RC_OPTION_lock] = {0x003C90, 15, 12},
526 [U_OTP_Dlock_Reserved2] = {0x003C90, 31, 16},
527 [U_OTP_Dlock_Reserved3] = {0x003C94, 31, 0},
528 [U_OTP_LockWord_CA_reserved0_W] = {0x003C98, 1, 0},
529 [U_OTP_LockWord_CA_reserved1_W] = {0x003C98, 3, 2},
530 [U_OTP_LockWord_CA_reserved2_W] = {0x003C98, 5, 4},
531 [U_OTP_LockWord_CA_reserved3_W] = {0x003C98, 7, 6},
532 [U_OTP_LockWord_CA_reserved4_W] = {0x003C98, 9, 8},
533 [U_OTP_LockWord_CA_reserved5_W] = {0x003C98, 11, 10},
534 [U_OTP_LockWord_CA_reserved6_W] = {0x003C98, 13, 12},
535 [U_OTP_LockWord_CA_reserved7_W] = {0x003C98, 15, 14},
536 [U_OTP_LockWord_CA_reserved8_W] = {0x003C98, 17, 16},
537 [U_OTP_LockWord_CA_reserved9_W] = {0x003C98, 19, 18},
538 [U_OTP_LockWord_CA_reserved10_W] = {0x003C98, 21, 20},
539 [U_OTP_LockWord_CA_reserved11_W] = {0x003C98, 23, 22},
540 [U_OTP_LockWord_CA_reserved12_W] = {0x003C98, 25, 24},
541 [U_OTP_LockWord_CA_reserved13_W] = {0x003C98, 27, 26},
542 [U_OTP_LockWord_CA_reserved14_W] = {0x003C98, 29, 28},
543 [U_OTP_LockWord_CA_reserved15_W] = {0x003C98, 31, 30},
544 [U_OTP_LockWord_RSA_0_W] = {0x003C9C, 1, 0},
545 [U_OTP_LockWord_RSA_1_W] = {0x003C9C, 3, 2},
546 [U_OTP_LockWord_RSA_CTRL_W] = {0x003C9C, 5, 4},
547 [U_OTP_LockWord_IXSC_Config_W] = {0x003C9C, 7, 6},
548 [U_OTP_LockWord_v_PubOtpOID_W] = {0x003C9C, 9, 8},
549 [U_OTP_LockWord_v_PubOtpVID_W] = {0x003C9C, 11, 10},
550 [U_OTP_LockWord_v_PubOtpBID_W] = {0x003C9C, 13, 12},
551 [U_OTP_LockWord_v_PubOtpRsaIndex_W] = {0x003C9C, 15, 14},
552 [U_OTP_LockWord_v_PubOtpMinConfVer_W] = {0x003C9C, 17, 16},
553 [U_OTP_LockWord_VenderConstSel_W] = {0x003C9C, 19, 18},
554 [U_OTP_LockWord_NDS_info_W] = {0x003C9C, 21, 20},
555 [U_OTP_LockWord_PM51_W] = {0x003C9C, 23, 22},
556 [U_OTP_LockWord_OTHERS_W] = {0x003C9C, 25, 24},
557 [U_OTP_LockWord_Reserved0] = {0x003C9C, 31, 26},
558 [U_OTP_LockWord_NOCS3_MEM0_W] = {0x003CA0, 1, 0},
559 [U_OTP_LockWord_NOCS3_MEM1_W] = {0x003CA0, 3, 2},
560 [U_OTP_LockWord_NOCS3_MEM2_W] = {0x003CA0, 5, 4},
561 [U_OTP_LockWord_NOCS3_MEM3_W] = {0x003CA0, 7, 6},
562 [U_OTP_LockWord_MSID_W] = {0x003CA0, 9, 8},
563 [U_OTP_LockWord_CFG_STB_CA_SN_W] = {0x003CA0, 11, 10},
564 [U_OTP_LockWord_TSP_W] = {0x003CA0, 13, 12},
565 [U_OTP_LockWord_PGMask_W] = {0x003CA0, 15, 14},
566 [U_OTP_LockWord_ClkDet_Para_W] = {0x003CA0, 17, 16},
567 [U_OTP_LockWord_OTP_CTRL_W] = {0x003CA0, 19, 18},
568 [U_OTP_LockWord_CPU_bank_W] = {0x003CA0, 21, 20},
569 [U_OTP_LockWord_trimming_W] = {0x003CA0, 23, 22},
570 [U_OTP_LockWord_BOND0_W] = {0x003CA0, 25, 24},
571 [U_OTP_LockWord_BOND_Reserved_W] = {0x003CA0, 27, 26},
572 [U_OTP_LockWord_Reserved1] = {0x003CA0, 31, 28},
573 [U_OTP_LockWord_LOT_INFO_W] = {0x003CA4, 1, 0},
574 [U_OTP_LockWord_CA_Enable_W] = {0x003CA4, 3, 2},
575 [U_OTP_LockWord_KL_bank_W] = {0x003CA4, 5, 4},
576 [U_OTP_LockWord_KT_bank_W] = {0x003CA4, 7, 6},
577 [U_OTP_LockWord_DMA_bank_W] = {0x003CA4, 9, 8},
578 [U_OTP_LockWord_TSCE_W] = {0x003CA4, 11, 10},
579 [U_OTP_LockWord_HDCP_KEY_W] = {0x003CA4, 13, 12},
580 [U_OTP_LockWord_Multi2SysKey_W] = {0x003CA4, 15, 14},
581 [U_OTP_LockWord_CAV_Key1_W] = {0x003CA4, 17, 16},
582 [U_OTP_LockWord_CAV_Key2_W] = {0x003CA4, 19, 18},
583 [U_OTP_LockWord_CAV_Key3_W] = {0x003CA4, 21, 20},
584 [U_OTP_LockWord_CAV_Key4_W] = {0x003CA4, 23, 22},
585 [U_OTP_LockWord_CAV_Key5_W] = {0x003CA4, 25, 24},
586 [U_OTP_LockWord_CAV_Key6_W] = {0x003CA4, 27, 26},
587 [U_OTP_LockWord_CAV_Key7_W] = {0x003CA4, 29, 28},
588 [U_OTP_LockWord_CAV_Key8_W] = {0x003CA4, 31, 30},
589 [U_OTP_LockWord_CAVID_W] = {0x003CA8, 1, 0},
590 [U_OTP_LockWord_CAV_KP1_W] = {0x003CA8, 3, 2},
591 [U_OTP_LockWord_CAV_KP2_W] = {0x003CA8, 5, 4},
592 [U_OTP_LockWord_CAV_KP3_W] = {0x003CA8, 7, 6},
593 [U_OTP_LockWord_CAV_KP4_W] = {0x003CA8, 9, 8},
594 [U_OTP_LockWord_CAV_KP5_W] = {0x003CA8, 11, 10},
595 [U_OTP_LockWord_CAV_KP6_W] = {0x003CA8, 13, 12},
596 [U_OTP_LockWord_CAV_KP7_W] = {0x003CA8, 15, 14},
597 [U_OTP_LockWord_CAV_KP8_W] = {0x003CA8, 17, 16},
598 [U_OTP_LockWord_CAV_KP9_W] = {0x003CA8, 19, 18},
599 [U_OTP_LockWord_CAV_KP10_W] = {0x003CA8, 21, 20},
600 [U_OTP_LockWord_CAV_KP11_W] = {0x003CA8, 23, 22},
601 [U_OTP_LockWord_CAV_KP12_W] = {0x003CA8, 25, 24},
602 [U_OTP_LockWord_CAV_KP13_W] = {0x003CA8, 27, 26},
603 [U_OTP_LockWord_CAV_KP14_W] = {0x003CA8, 29, 28},
604 [U_OTP_LockWord_CAV_KP15_W] = {0x003CA8, 31, 30},
605 [U_OTP_LockWord_PubOTPUniqueID1_W] = {0x003CAC, 1, 0},
606 [U_OTP_LockWord_PubOTPUniqueID2_W] = {0x003CAC, 3, 2},
607 [U_OTP_LockWord_PubOTPUniqueID3_W] = {0x003CAC, 5, 4},
608 [U_OTP_LockWord_PubOTPUniqueID4_W] = {0x003CAC, 7, 6},
609 [U_OTP_LockWord_AES_MOD_MASK_W] = {0x003CAC, 9, 8},
610 [U_OTP_LockWord_ACPU_Property_W] = {0x003CAC, 11, 10},
611 [U_OTP_LockWord_SCPU_Property_W] = {0x003CAC, 13, 12},
612 [U_OTP_LockWord_CA_PWD_W] = {0x003CAC, 15, 14},
613 [U_OTP_LockWord_CA_PWD_CTRL_W] = {0x003CAC, 17, 16},
614 [U_OTP_LockWord_VtrackData_W] = {0x003CAC, 19, 18},
615 [U_OTP_LockWord_FAKE_W] = {0x003CAC, 21, 20},
616 [U_OTP_LockWord_SW0_W] = {0x003CAC, 23, 22},
617 [U_OTP_LockWord_Reserved2] = {0x003CAC, 31, 26},
618 [U_OTP_LockWord_0000_0511_W] = {0x003CB0, 1, 0},
619 [U_OTP_LockWord_0512_1023_W] = {0x003CB0, 3, 2},
620 [U_OTP_LockWord_1024_1535_W] = {0x003CB0, 5, 4},
621 [U_OTP_LockWord_1536_2047_W] = {0x003CB0, 7, 6},
622 [U_OTP_LockWord_2048_2559_W] = {0x003CB0, 9, 8},
623 [U_OTP_LockWord_2560_3071_W] = {0x003CB0, 11, 10},
624 [U_OTP_LockWord_3072_3391_W] = {0x003CB0, 13, 12},
625 [U_OTP_LockWord_Chip_Extension_ID] = {0x003CB0, 15, 14},
626 [U_OTP_LockWord_Reserved3] = {0x003CB0, 31, 16},
627 [U_OTP_LockWord_CAV_Key1_R] = {0x003CB4, 1, 0},
628 [U_OTP_LockWord_CAV_Key2_R] = {0x003CB4, 3, 2},
629 [U_OTP_LockWord_CAV_Key3_R] = {0x003CB4, 5, 4},
630 [U_OTP_LockWord_CAV_Key4_R] = {0x003CB4, 7, 6},
631 [U_OTP_LockWord_CAV_Key5_R] = {0x003CB4, 9, 8},
632 [U_OTP_LockWord_CAV_Key6_R] = {0x003CB4, 11, 10},
633 [U_OTP_LockWord_CAV_Key7_R] = {0x003CB4, 13, 12},
634 [U_OTP_LockWord_CAV_Key8_R] = {0x003CB4, 15, 14},
635 [U_OTP_LockWord_RSA_0_R] = {0x003CB4, 17, 16},
636 [U_OTP_LockWord_RSA_1_R] = {0x003CB4, 19, 18},
637 [U_OTP_LockWord_HDCP_KEY_R] = {0x003CB4, 21, 20},
638 [U_OTP_LockWord_Multi2SysKey_R] = {0x003CB4, 23, 22},
639 [U_OTP_LockWord_AES_MOD_MASK_R] = {0x003CB4, 25, 24},
640 [U_OTP_LockWord_VtrackData_R] = {0x003CB4, 27, 26},
641 [U_OTP_LockWord_CA_PWD_R] = {0x003CB4, 29, 28},
642 [U_OTP_LockWord_Reserved4] = {0x003CB4, 31, 30},
643 [U_OTP_ClkDet_Para] = {0x003CB8, 63, 0},
644 [U_OTP_forbid_ACPUWriteOTP] = {0x003CC0, 1, 0},
645 [U_OTP_forbid_ACPUReadOTP] = {0x003CC0, 3, 2},
646 [U_OTP_forbid_SCPUWriteOTP] = {0x003CC0, 5, 4},
647 [U_OTP_forbid_SCPUReadOTP] = {0x003CC0, 7, 6},
648 [U_OTP_forbid_DBBUSWriteOTP] = {0x003CC0, 9, 8},
649 [U_OTP_forbid_DBBUSReadOTP] = {0x003CC0, 11, 10},
650 [U_OTP_allow_RANDOM] = {0x003CC0, 13, 12},
651 [U_OTP_allow_NOISE_Rd] = {0x003CC0, 15, 14},
652 [U_OTP_allow_OTP_BgCRC] = {0x003CC0, 17, 16},
653 [U_OTP_allow_SKIP_0] = {0x003CC0, 19, 18},
654 [U_OTP_allow_SKIP_1] = {0x003CC0, 21, 20},
655 [U_OTP_allow_Mask_AES] = {0x003CC0, 23, 22},
656 [U_OTP_ena_Mstar_Wrapper] = {0x003CC0, 25, 24},
657 [U_OTP_CTRL_Reserved0] = {0x003CC0, 31, 26},
658 [U_OTP_allow_XOR_ROMCODE] = {0x003CC4, 6, 0},
659 [U_OTP_allow_XOR_FIX] = {0x003CC4, 7, 7},
660 [U_OTP_allow_PWD_OTP_prog] = {0x003CC4, 9, 8},
661 [U_OTP_CTRL_Reserved1] = {0x003CC4, 31, 10},
662 [U_OTP_SBoot] = {0x003CC8, 3, 0},
663 [U_OTP_SecretAreaEnable] = {0x003CC8, 7, 4},
664 [U_OTP_forbid_TestInOut] = {0x003CC8, 9, 8},
665 [U_OTP_allow_FlashProtect] = {0x003CC8, 11, 10},
666 [U_OTP_PERSO_done] = {0x003CC8, 13, 12},
667 [U_OTP_CERT_PERSO_done] = {0x003CC8, 15, 14},
668 [U_OTP_DBUG_Reserved0] = {0x003CC8, 31, 16},
669 [U_OTP_SCAN_MODE] = {0x003CCC, 8, 0},
670 [U_OTP_DBUG_Reserved1] = {0x003CCC, 9, 9},
671 [U_OTP_MBIST_MODE] = {0x003CCC, 15, 10},
672 [U_OTP_I2C_MODE] = {0x003CCC, 21, 16},
673 [U_OTP_DBUG_Reserved2] = {0x003CCC, 25, 22},
674 [U_OTP_EJTAG_MODE] = {0x003CCC, 31, 26},
675 [U_OTP_RMA_MODE] = {0x003CD0, 5, 0},
676 [U_OTP_LicRework] = {0x003CD0, 7, 6},
677 [U_OTP_forbid_USBSlaveMode] = {0x003CD0, 11, 8},
678 [U_OTP_allow_DRAM_MOBF] = {0x003CD0, 13, 12},
679 [U_OTP_allow_DRAMOBF_4ROUND] = {0x003CD0, 15, 14},
680 [U_OTP_ena_DRAMOBF_NS_MASK_ADDR] = {0x003CD0, 17, 16},
681 [U_OTP_forbid_clk_otp_sel] = {0x003CD0, 20, 18},
682 [U_OTP_forbid_acpu_access_sec_bridge] = {0x003CD0, 23, 21},
683 [U_OTP_forbid_dbbus_access_sec_bridge] = {0x003CD0, 26, 24},
684 [U_OTP_XPM_State] = {0x003CD0, 29, 27},
685 [U_OTP_DBUG_Reserved3] = {0x003CD0, 31, 30},
686 [U_OTP_DeactiveDRAMBoot] = {0x003CD4, 3, 0},
687 [U_OTP_ACPU_Reserved0] = {0x003CD4, 7, 4},
688 [U_OTP_BootMode] = {0x003CD4, 13, 8},
689 [U_OTP_forbid_BCKGND_CHK] = {0x003CD4, 15, 14},
690 [U_OTP_SCPUBootMode] = {0x003CD4, 21, 16},
691 [U_OTP_ACPU_Reserved1] = {0x003CD4, 23, 22},
692 [U_OTP_PM_MCU_RST_MOD] = {0x003CD4, 26, 24},
693 [U_OTP_boot_host_sel] = {0x003CD4, 29, 27},
694 [U_OTP_ACPU_Reserved2] = {0x003CD4, 31, 30},
695 [U_OTP_ACPU_Reserved3] = {0x003CD8, 11, 0},
696 [U_OTP_PostMskAreaRangeU] = {0x003CD8, 23, 12},
697 [U_OTP_ACPUasHost] = {0x003CD8, 26, 24},
698 [U_OTP_BONDING] = {0x003CD8, 28, 27},
699 [U_OTP_NON_BLANK] = {0x003CD8, 29, 29},
700 [U_OTP_ACPU_Reserved4] = {0x003CD8, 31, 30},
701 [U_OTP_PE_LOT_INFO] = {0x003CDC, 47, 0},
702 [U_OTP_BootDevice] = {0x003CDC, 55, 48},
703 [U_OTP_MAX_RDNTBLK] = {0x003CDC, 61, 56},
704 [U_OTP_forbid_STR] = {0x003CDC, 63, 62},
705 [U_OTP_Bootcode_project] = {0x003CE4, 7, 0},
706 [U_OTP_Bootcode_subversion] = {0x003CE4, 15, 8},
707 [U_OTP_Bootcode_version] = {0x003CE4, 31, 16},
708 [U_OTP_Analog_Usage] = {0x003CE8, 63, 0},
709 [U_OTP_Analog_Usage2] = {0x003CF0, 95, 0},
710 [U_OTP_trim_dac] = {0x003CFC, 125, 0},
711 [U_OTP_Trim_Reserved0] = {0x003CFC, 127, 126},
712 [U_OTP_BOND0] = {0x003D0C, 95, 0},
713 [U_OTP_BOND_Reserved] = {0x003D18, 95, 0},
714 [U_OTP_ena_KeyLadder_0] = {0x003D24, 3, 0},
715 [U_OTP_ena_KeyLadder_1] = {0x003D24, 7, 4},
716 [U_OTP_ena_NSK2] = {0x003D24, 11, 8},
717 [U_OTP_ena_CERT_IP] = {0x003D24, 13, 12},
718 [U_OTP_ena_DMA] = {0x003D24, 15, 14},
719 [U_OTP_ena_SCPU] = {0x003D24, 19, 16},
720 [U_OTP_CA_EN_Reserved0] = {0x003D24, 31, 20},
721 [U_OTP_allow_IXSC] = {0x003D28, 3, 0},
722 [U_OTP_forbid_IXSC] = {0x003D28, 7, 4},
723 [U_OTP_forbid_PAVOSC] = {0x003D28, 9, 8},
724 [U_OTP_cfDeactiveFuse] = {0x003D28, 10, 10},
725 [U_OTP_SOC_UID_SEL] = {0x003D28, 12, 11},
726 [U_OTP_CA_EN_Reserved2] = {0x003D28, 31, 13},
727 [U_OTP_dis_kl0_hostkey] = {0x003D2C, 1, 0},
728 [U_OTP_dis_kl1_hostkey] = {0x003D2C, 3, 2},
729 [U_OTP_dis_kl0_hostkey_property] = {0x003D2C, 5, 4},
730 [U_OTP_dis_kl1_hostkey_property] = {0x003D2C, 7, 6},
731 [U_OTP_kl_protect0_mode] = {0x003D2C, 9, 8},
732 [U_OTP_kl_protect1_mode] = {0x003D2C, 11, 10},
733 [U_OTP_kl_protect2_mode] = {0x003D2C, 13, 12},
734 [U_OTP_kl_protect3_mode] = {0x003D2C, 15, 14},
735 [U_OTP_dis_kl_protect0] = {0x003D2C, 17, 16},
736 [U_OTP_dis_kl_protect1] = {0x003D2C, 19, 18},
737 [U_OTP_dis_kl_protect2] = {0x003D2C, 21, 20},
738 [U_OTP_dis_kl_protect3] = {0x003D2C, 23, 22},
739 [U_OTP_dis_kl_protect4] = {0x003D2C, 25, 24},
740 [U_OTP_kl_TA_LUT0_mode] = {0x003D2C, 27, 26},
741 [U_OTP_kl_TA_LUT1_mode] = {0x003D2C, 29, 28},
742 [U_OTP_ena_kl_StopClkChk] = {0x003D2C, 31, 30},
743 [U_OTP_KDF_secret_mask] = {0x003D30, 127, 0},
744 [U_OTP_IMLB_ROTATION] = {0x003D40, 15, 0},
745 [U_OTP_IrdetoTweakedCSAv3] = {0x003D40, 17, 16},
746 [U_OTP_allow_SPSSPDKeyShuffle] = {0x003D40, 21, 18},
747 [U_OTP_kl_BISS_MODE] = {0x003D40, 23, 22},
748 [U_OTP_ena_kl_xor_func] = {0x003D40, 25, 24},
749 [U_OTP_KL_Reserved2] = {0x003D40, 31, 26},
750 [U_OTP_ena_ACPU2KT] = {0x003D44, 3, 0},
751 [U_OTP_ena_NSK2KT] = {0x003D44, 7, 4},
752 [U_OTP_ena_KL2KT] = {0x003D44, 11, 8},
753 [U_OTP_ena_SCPU2KT] = {0x003D44, 15, 12},
754 [U_OTP_ena_ACPUWrNSKKey2KT] = {0x003D44, 19, 16},
755 [U_OTP_ena_ACPUWrCFBKey2KT] = {0x003D44, 23, 20},
756 [U_OTP_ena_NSKCW2CryptoDMA] = {0x003D44, 27, 24},
757 [U_OTP_ena_ACPU2LSA] = {0x003D44, 31, 28},
758 [U_OTP_BISS_MODE] = {0x003D48, 3, 0},
759 [U_OTP_BISS_SUBMODE] = {0x003D48, 5, 4},
760 [U_OTP_KT_Reserved0] = {0x003D48, 31, 6},
761 [U_OTP_ena_ACPU2DMA] = {0x003D4C, 3, 0},
762 [U_OTP_ena_DMA_DESBasedCipher] = {0x003D4C, 7, 4},
763 [U_OTP_ena_AESMAC_MaxRate] = {0x003D4C, 9, 8},
764 [U_OTP_allow_DMAtDES2KeyEQChk] = {0x003D4C, 12, 10},
765 [U_OTP_DMA_Reserved0] = {0x003D4C, 13, 13},
766 [U_OTP_ena_DMA_ClearKeySlot ] = {0x003D4C, 15, 14},
767 [U_OTP_dis_DMA_mask_engine] = {0x003D4C, 17, 16},
768 [U_OTP_DMA_Reserved1] = {0x003D4C, 31, 18},
769 [U_OTP_ena_LSACPCM] = {0x003D50, 3, 0},
770 [U_OTP_ena_AESBasedCipher] = {0x003D50, 7, 4},
771 [U_OTP_ena_DESBasedCipher] = {0x003D50, 11, 8},
772 [U_OTP_ena_3DESBasedCipher] = {0x003D50, 15, 12},
773 [U_OTP_ena_Multi2BasedCipher] = {0x003D50, 19, 16},
774 [U_OTP_ena_DVBCSA2ConfCipher] = {0x003D50, 23, 20},
775 [U_OTP_ena_DVBCSA2Cipher] = {0x003D50, 27, 24},
776 [U_OTP_ena_DVBCSA3BasedCipher] = {0x003D50, 31, 28},
777 [U_OTP_Ch_SwitchComb] = {0x003D54, 63, 0},
778 [U_OTP_ena_LSAD_MDI] = {0x003D5C, 3, 0},
779 [U_OTP_ena_LSAD_MDD] = {0x003D5C, 7, 4},
780 [U_OTP_ena_LSAD_CIPLUS_AES] = {0x003D5C, 11, 8},
781 [U_OTP_ena_LSAD_AES_ECB_CLEAR] = {0x003D5C, 15, 12},
782 [U_OTP_ena_LSAD_SCTE41_SCTE52_DES] = {0x003D5C, 19, 16},
783 [U_OTP_TSCE_Reserved0] = {0x003D5C, 31, 20},
784 [U_OTP_ena_ESA_CIPLUS_AES] = {0x003D60, 3, 0},
785 [U_OTP_ena_ESA_CIPLUS_DES] = {0x003D60, 7, 4},
786 [U_OTP_ena_ESA_SCTE52_DES] = {0x003D60, 11, 8},
787 [U_OTP_ena_ESA_tDES_CBC_CLEAR] = {0x003D60, 15, 12},
788 [U_OTP_TSCE_Reserved1] = {0x003D60, 31, 16},
789 [U_OTP_ena_LSAS_MDI] = {0x003D64, 3, 0},
790 [U_OTP_ena_LSAS_MDD] = {0x003D64, 7, 4},
791 [U_OTP_ena_LSAS_CIPLUS_AES] = {0x003D64, 11, 8},
792 [U_OTP_ena_LSAS_AES_ECB_CLEAR] = {0x003D64, 15, 12},
793 [U_OTP_ena_LSAS_SCTE41_SCTE52_DES] = {0x003D64, 19, 16},
794 [U_OTP_TSCE_Reserved2] = {0x003D64, 31, 20},
795 [U_OTP_ena_DRMAreaEncrypt] = {0x003D68, 3, 0},
796 [U_OTP_ena_ReviewFailPkt] = {0x003D68, 7, 4},
797 [U_OTP_dis_NonSecRangeEncrypt] = {0x003D68, 11, 8},
798 [U_OTP_TSCE_Reserved3] = {0x003D68, 31, 12},
799 [U_OTP_ena_CA_PVR_secure_protect_0] = {0x003D6C, 3, 0},
800 [U_OTP_ena_CA_PVR_secure_protect_1] = {0x003D6C, 7, 4},
801 [U_OTP_ena_CA_PVR_secure_protect_2] = {0x003D6C, 11, 8},
802 [U_OTP_ena_CA_PVR_secure_protect_3] = {0x003D6C, 15, 12},
803 [U_OTP_ena_LowerPathRec] = {0x003D6C, 19, 16},
804 [U_OTP_ena_SWMulti2SysKey] = {0x003D6C, 23, 20},
805 [U_OTP_TSCE_Reserved4] = {0x003D6C, 31, 24},
806 [U_OTP_HDCP_KEY] = {0x003D70, 55, 0},
807 [U_OTP_HDCP_Reserved0] = {0x003D70, 7, 0},
808 [U_OTP_Multi2SysKey] = {0x003D78, 255, 0},
809 [U_OTP_AES_MOD_MASK] = {0x003D98, 127, 0},
810 [U_OTP_v_pubOtpUniqueID1] = {0x003DA8, 63, 0},
811 [U_OTP_v_pubOtpUniqueID2] = {0x003DB0, 63, 0},
812 [U_OTP_v_pubOtpUniqueID3] = {0x003DB8, 63, 0},
813 [U_OTP_v_pubOtpUniqueID4] = {0x003DC0, 63, 0},
814 [U_OTP_CAV_ESCK_KeyValid] = {0x003DC8, 7, 0},
815 [U_OTP_CAV_Reserved0] = {0x003DC8, 15, 8},
816 [U_OTP_CAV_SCK_KeyValid] = {0x003DC8, 31, 16},
817 [U_OTP_CAV_Reserved1] = {0x003DCC, 31, 0},
818 [U_OTP_CAV_Key1_SCK_mapping] = {0x003DD0, 15, 0},
819 [U_OTP_CAV_Key1_integrity_chk] = {0x003DD0, 17, 16},
820 [U_OTP_CAV_Key1_allow_ChkNum] = {0x003DD0, 19, 18},
821 [U_OTP_CAV_Key1_obfuscation] = {0x003DD0, 21, 20},
822 [U_OTP_CAV_Key1_IdSel] = {0x003DD0, 23, 22},
823 [U_OTP_CAV_Key1_KeySel] = {0x003DD0, 29, 24},
824 [U_OTP_CAV_Key1_reserved] = {0x003DD0, 31, 30},
825 [U_OTP_CAV_Key1_ChkNum_Gold] = {0x003DD4, 31, 0},
826 [U_OTP_CAV_Key2_SCK_mapping] = {0x003DD8, 15, 0},
827 [U_OTP_CAV_Key2_integrity_chk] = {0x003DD8, 17, 16},
828 [U_OTP_CAV_Key2_allow_ChkNum] = {0x003DD8, 19, 18},
829 [U_OTP_CAV_Key2_obfuscation] = {0x003DD8, 21, 20},
830 [U_OTP_CAV_Key2_IdSel] = {0x003DD8, 23, 22},
831 [U_OTP_CAV_Key2_KeySel] = {0x003DD8, 29, 24},
832 [U_OTP_CAV_Key2_reserved] = {0x003DD8, 31, 30},
833 [U_OTP_CAV_Key2_ChkNum_Gold] = {0x003DDC, 31, 0},
834 [U_OTP_CAV_Key3_SCK_mapping] = {0x003DE0, 15, 0},
835 [U_OTP_CAV_Key3_integrity_chk] = {0x003DE0, 17, 16},
836 [U_OTP_CAV_Key3_allow_ChkNum] = {0x003DE0, 19, 18},
837 [U_OTP_CAV_Key3_obfuscation] = {0x003DE0, 21, 20},
838 [U_OTP_CAV_Key3_IdSel] = {0x003DE0, 23, 22},
839 [U_OTP_CAV_Key3_KeySel] = {0x003DE0, 29, 24},
840 [U_OTP_CAV_Key3_reserved] = {0x003DE0, 31, 30},
841 [U_OTP_CAV_Key3_ChkNum_Gold] = {0x003DE4, 31, 0},
842 [U_OTP_CAV_Key4_SCK_mapping] = {0x003DE8, 15, 0},
843 [U_OTP_CAV_Key4_integrity_chk] = {0x003DE8, 17, 16},
844 [U_OTP_CAV_Key4_allow_ChkNum] = {0x003DE8, 19, 18},
845 [U_OTP_CAV_Key4_obfuscation] = {0x003DE8, 21, 20},
846 [U_OTP_CAV_Key4_IdSel] = {0x003DE8, 23, 22},
847 [U_OTP_CAV_Key4_KeySel] = {0x003DE8, 29, 24},
848 [U_OTP_CAV_Key4_reserved] = {0x003DE8, 31, 30},
849 [U_OTP_CAV_Key4_ChkNum_Gold] = {0x003DEC, 31, 0},
850 [U_OTP_CAV_Key5_SCK_mapping] = {0x003DF0, 15, 0},
851 [U_OTP_CAV_Key5_integrity_chk] = {0x003DF0, 17, 16},
852 [U_OTP_CAV_Key5_allow_ChkNum] = {0x003DF0, 19, 18},
853 [U_OTP_CAV_Key5_obfuscation] = {0x003DF0, 21, 20},
854 [U_OTP_CAV_Key5_IdSel] = {0x003DF0, 23, 22},
855 [U_OTP_CAV_Key5_KeySel] = {0x003DF0, 29, 24},
856 [U_OTP_CAV_Key5_reserved] = {0x003DF0, 31, 30},
857 [U_OTP_CAV_Key5_ChkNum_Gold] = {0x003DF4, 31, 0},
858 [U_OTP_CAV_Key6_SCK_mapping] = {0x003DF8, 15, 0},
859 [U_OTP_CAV_Key6_integrity_chk] = {0x003DF8, 17, 16},
860 [U_OTP_CAV_Key6_allow_ChkNum] = {0x003DF8, 19, 18},
861 [U_OTP_CAV_Key6_obfuscation] = {0x003DF8, 21, 20},
862 [U_OTP_CAV_Key6_IdSel] = {0x003DF8, 23, 22},
863 [U_OTP_CAV_Key6_KeySel] = {0x003DF8, 29, 24},
864 [U_OTP_CAV_Key6_reserved] = {0x003DF8, 31, 30},
865 [U_OTP_CAV_Key6_ChkNum_Gold] = {0x003DFC, 31, 0},
866 [U_OTP_CAV_Key7_SCK_mapping] = {0x003E00, 15, 0},
867 [U_OTP_CAV_Key7_integrity_chk] = {0x003E00, 17, 16},
868 [U_OTP_CAV_Key7_allow_ChkNum] = {0x003E00, 19, 18},
869 [U_OTP_CAV_Key7_obfuscation] = {0x003E00, 21, 20},
870 [U_OTP_CAV_Key7_IdSel] = {0x003E00, 23, 22},
871 [U_OTP_CAV_Key7_KeySel] = {0x003E00, 29, 24},
872 [U_OTP_CAV_Key7_reserved] = {0x003E00, 31, 30},
873 [U_OTP_CAV_Key7_ChkNum_Gold] = {0x003E04, 31, 0},
874 [U_OTP_CAV_Key8_SCK_mapping] = {0x003E08, 15, 0},
875 [U_OTP_CAV_Key8_integrity_chk] = {0x003E08, 17, 16},
876 [U_OTP_CAV_Key8_allow_ChkNum] = {0x003E08, 19, 18},
877 [U_OTP_CAV_Key8_obfuscation] = {0x003E08, 21, 20},
878 [U_OTP_CAV_Key8_IdSel] = {0x003E08, 23, 22},
879 [U_OTP_CAV_Key8_KeySel] = {0x003E08, 29, 24},
880 [U_OTP_CAV_Key8_reserved] = {0x003E08, 31, 30},
881 [U_OTP_CAV_Key8_ChkNum_Gold] = {0x003E0C, 31, 0},
882 [U_OTP_ACPU_Property] = {0x003E10, 127, 0},
883 [U_OTP_SCPU_Property] = {0x003E20, 127, 0},
884 [U_OTP_CAV_Key1_Property] = {0x003E30, 127, 0},
885 [U_OTP_CAV_Key2_Property] = {0x003E40, 127, 0},
886 [U_OTP_CAV_Key3_Property] = {0x003E50, 127, 0},
887 [U_OTP_CAV_Key4_Property] = {0x003E60, 127, 0},
888 [U_OTP_CAV_Key5_Property] = {0x003E70, 127, 0},
889 [U_OTP_CAV_Key6_Property] = {0x003E80, 127, 0},
890 [U_OTP_CAV_Key7_Property] = {0x003E90, 127, 0},
891 [U_OTP_CAV_Key8_Property] = {0x003EA0, 127, 0},
892 [U_OTP_CAV_Key9_Property] = {0x003EB0, 127, 0},
893 [U_OTP_CAV_Key10_Property] = {0x003EC0, 127, 0},
894 [U_OTP_CAV_Key11_Property] = {0x003ED0, 127, 0},
895 [U_OTP_CAV_Key12_Property] = {0x003EE0, 127, 0},
896 [U_OTP_CAV_Key13_Property] = {0x003EF0, 127, 0},
897 [U_OTP_CAV_Key14_Property] = {0x003F00, 127, 0},
898 [U_OTP_CAV_Key15_Property] = {0x003F10, 127, 0},
899 [U_OTP_CAV_SecretKey1] = {0x003F20, 127, 0},
900 [U_OTP_CAV_SecretKey2] = {0x003F30, 127, 0},
901 [U_OTP_CAV_SecretKey3] = {0x003F40, 127, 0},
902 [U_OTP_CAV_SecretKey4] = {0x003F50, 127, 0},
903 [U_OTP_CAV_SecretKey5] = {0x003F60, 127, 0},
904 [U_OTP_CAV_SecretKey6] = {0x003F70, 127, 0},
905 [U_OTP_CAV_SecretKey7] = {0x003F80, 127, 0},
906 [U_OTP_CAV_SecretKey8] = {0x003F90, 127, 0},
907 [U_OTP_CA_PWD_integrity_chk] = {0x003FA0, 1, 0},
908 [U_OTP_Multi2SysKey_integrity_chk] = {0x003FA0, 3, 2},
909 [U_OTP_CA_PWD_Reserved0] = {0x003FA0, 7, 4},
910 [U_OTP_I2C_PWD_obfuscation] = {0x003FA0, 9, 8},
911 [U_OTP_EJTAG_PWD_obfuscation] = {0x003FA0, 11, 10},
912 [U_OTP_SCAN_PWD_obfuscation] = {0x003FA0, 13, 12},
913 [U_OTP_MBIST_PWD_obfuscation] = {0x003FA0, 15, 14},
914 [U_OTP_Multi2SysKey_CRC] = {0x003FA0, 31, 16},
915 [U_OTP_I2C_PWD_CRC] = {0x003FA4, 15, 0},
916 [U_OTP_EJTAG_PWD_CRC] = {0x003FA4, 31, 16},
917 [U_OTP_SCAN_PWD_CRC] = {0x003FA8, 15, 0},
918 [U_OTP_MBIST_PWD_CRC] = {0x003FA8, 31, 16},
919 [U_OTP_CA_PWD_Keysel] = {0x003FAC, 5, 0},
920 [U_OTP_ena_TP_PWD] = {0x003FAC, 7, 6},
921 [U_OTP_ena_KDF_I2C_PWD] = {0x003FAC, 9, 8},
922 [U_OTP_ena_KDF_EJTAG_PWD] = {0x003FAC, 11, 10},
923 [U_OTP_ena_KDF_SCAN_PWD] = {0x003FAC, 13, 12},
924 [U_OTP_ena_KDF_MBIST_PWD] = {0x003FAC, 15, 14},
925 [U_OTP_I2C_TP_ID] = {0x003FAC, 19, 16},
926 [U_OTP_EJTAG_TP_ID] = {0x003FAC, 23, 20},
927 [U_OTP_SCAN_TP_ID] = {0x003FAC, 27, 24},
928 [U_OTP_MBIST_TP_ID] = {0x003FAC, 31, 28},
929 [U_OTP_I2C_PWD] = {0x003FB0, 127, 0},
930 [U_OTP_EJTAG_PWD] = {0x003FC0, 127, 0},
931 [U_OTP_SCAN_PWD] = {0x003FD0, 127, 0},
932 [U_OTP_MBIST_PWD] = {0x003FE0, 127, 0},
933 [U_OTP_VtrackID] = {0x003FF0, 31, 0},
934 [U_OTP_VtrackKey] = {0x003FF4, 31, 0},
935 [U_OTP_VtrackID_select] = {0x003FF8, 0, 0},
936 [U_OTP_VtrackKey_select] = {0x003FF8, 1, 1},
937 [U_OTP_Vtrack_Reserved0] = {0x003FF8, 31, 2},
938 [U_OTP_FAKE] = {0x003FFC, 23, 0},
939 [U_OTP_allow_CPU_rst_release] = {0x003FFC, 31, 24},
940
941 };
942
943
944 MS_BOOL _HAL_CA_OTP_GetConfig(MS_U32 u32Idx, MS_U32 *pu32Value);
945 MS_BOOL _HAL_CA_OTP_SetConfig(MS_U32 u32Idx, MS_U32 u32Value);
946
947 //--------------------------------------------------------------------------------------------------
948 // Macro of bit operations
949 //--------------------------------------------------------------------------------------------------
950
951 //--------------------------------------------------------------------------------------------------
952 // Inline Function
953 //--------------------------------------------------------------------------------------------------
HAL_CA_SetBank(MS_U32 u32RegAddr)954 void HAL_CA_SetBank(MS_U32 u32RegAddr)
955 {
956 _u32REGBase = u32RegAddr;
957 _u32REGPMBase = u32RegAddr - 0x200000UL;
958 _u32REG_OTP_Base = u32RegAddr + REG_OTP_BASE;
959 _u32REG_RSA_Base = u32RegAddr + REG_RSA_BASE;
960 }
961
HAL_CA_Init(void)962 MS_BOOL HAL_CA_Init(void)
963 {
964 return TRUE;
965 }
966
HAL_CA_BGC_ISR(void)967 void HAL_CA_BGC_ISR(void)
968 {
969 MS_U32 u32Excp = REG32(BGC_RESP_FAIL);
970 // MS_U32 u32SecID = u32Excp & BGC_RESP_SECID;
971
972 if((u32Excp & BGC_RESP_RESET_AV) == BGC_RESP_RESET_AV)
973 {
974 //AV reset
975 HAL_CA_DEBUG("BGC: unexpected modification of protected area detected. Reset AV.");
976 }
977
978 if((u32Excp & BGC_RESP_RESET_ACPU) == BGC_RESP_RESET_ACPU)
979 {
980 //ACPU reset
981 HAL_CA_DEBUG("BGC: unexpected modification of protected area detected. Reset ACPU.");
982 }
983
984 if((u32Excp & BGC_RESP_RESET_SCPU) == BGC_RESP_RESET_SCPU)
985 {
986 //SCPU reset
987 HAL_CA_DEBUG("BGC: unexpected modification of protected area detected. Reset SCPU.");
988 }
989
990 if((u32Excp & BGC_RESP_RESET_SYSTEM) == BGC_RESP_RESET_SYSTEM)
991 {
992 //If error is reset system, run reset system(only in keres)
993 //System reset
994 HAL_CA_DEBUG("BGC: unexpected modification of protected area detected. Reset system.");
995 // REG32_PM(REG_TOP_SW_RST) = ((REG32_PM(REG_TOP_SW_RST) & ~REG_TOP_SW_RST_MSK) | REG_TOP_SW_RST_PASSWD);
996 }
997
998
999 }
1000
HAL_CA_BGC_DisableINT(void)1001 void HAL_CA_BGC_DisableINT(void)
1002 {
1003 REG32(REG_INTR_CPUINIT_HST3) = REG32(REG_INTR_CPUINIT_HST3) & (~REG_HST3TO2_INT);
1004 }
1005
HAL_CA_BGC_LoadFW(MS_U32 u32FwAddr,MS_U32 u32FwSize)1006 MS_BOOL HAL_CA_BGC_LoadFW(MS_U32 u32FwAddr, MS_U32 u32FwSize)
1007 {
1008 if(u32FwSize > 0x2000)
1009 { //max size is 8K
1010 return FALSE;
1011 }
1012
1013 if((REG32(REG_ONEWAY_42) & SEC51_SW_RST) == 0x0)//bit0, reset sec51
1014 {
1015 return TRUE;//already enable sec51
1016 }
1017
1018 REG32(REG_BDMA_STATUS) = REG32(REG_BDMA_STATUS) | 0x10; // triger bdma
1019 REG32(REG_BDMA_CTRL) = 0x0; //disable
1020 REG32(REG_BDMA_SRC_SEL) = 0x0940; //MIU0 to Sec_51
1021 REG32(REG_BDMA_SRC_ADDR_L) = u32FwAddr & 0xFFFF;
1022 REG32(REG_BDMA_SRC_ADDR_H) = (u32FwAddr >> 16) & 0xFFFF;
1023 REG32(REG_BDMA_DST_ADDR_L) = 0x0;
1024 REG32(REG_BDMA_DST_ADDR_H) = 0x0;
1025 REG32(REG_BDMA_SIZE_L) = u32FwSize & 0xFFFF; //size
1026 REG32(REG_BDMA_SIZE_H) = 0x0;
1027 REG32(REG_BDMA_CTRL) = 0x1; // triger bdma
1028 while((REG32(REG_BDMA_CTRL) & 0x1) != 0); //wait bdma done
1029
1030 REG32(REG_BDMA_STATUS) = REG32(REG_BDMA_STATUS) | 0x10; // triger bdma
1031
1032 REG32(REG_ONEWAY_42) = REG32(REG_ONEWAY_42) & (~SEC51_SW_RST);//bit 0, release sec51
1033
1034 REG32(REG_ONEWAY_52) = REG32(REG_ONEWAY_52) | SEC51_SW_LOCK;//bit 0, oneway lock sec51
1035
1036 //enable MIU cross bar
1037 REG32(REG_MIU_CROSSBAR_CTRL) = REG32(REG_MIU_CROSSBAR_CTRL) | REG_MIU_CROSSBAR_EN;
1038 return TRUE;
1039 }
1040
HAL_CA_BGC_Ctrl(MS_U32 u32Cmd,MS_U32 u32Data)1041 MS_BOOL HAL_CA_BGC_Ctrl(MS_U32 u32Cmd, MS_U32 u32Data)
1042 {
1043 MS_U16 u16Cmd = ((u32Data << BGC_CMD_SEC_DATA_SHT) & BGC_CMD_SEC_DATA) |
1044 ((u32Cmd << BGC_CMD_SEC_TYPE_SHT) & BGC_CMD_SEC_TYPE);
1045
1046 while((REG32(BGC_CMD_CTRL) & BGC_CMD_SEC_GO) == BGC_CMD_SEC_GO);
1047
1048 REG32(BGC_CMD_CTRL) = u16Cmd;
1049 REG32(BGC_CMD_CTRL) = u16Cmd | BGC_CMD_SEC_GO;
1050 // printf("[BGC Cmd]:%04X\n", u16Cmd);
1051
1052 while((REG32(BGC_CMD_CTRL) & BGC_CMD_SEC_GO) == BGC_CMD_SEC_GO);
1053 // printf("[BGC Cmd]:after write:%04X\n", REG32(BGC_CMD_CTRL));
1054
1055 if((REG32(BGC_CMD_CTRL) & BGC_CMD_SEC_STATUS) == BGC_CMD_SEC_STATUS)
1056 {
1057 return FALSE;
1058 }
1059 return TRUE;
1060 }
1061
HAL_CA_BGC_SetSec(MS_U32 u32SecId,const CA_BGC_SEC_CFG * pstSecCfg)1062 MS_BOOL HAL_CA_BGC_SetSec(MS_U32 u32SecId, const CA_BGC_SEC_CFG* pstSecCfg)
1063 {
1064 MS_U32 i = 0;
1065 MS_U32 u32Fail = 0;
1066
1067 if(u32SecId >= BGC_SEC_MAX )
1068 {
1069 return FALSE;
1070 }
1071
1072 //set section id
1073 if(HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_SECID, u32SecId) == FALSE)
1074 {
1075 u32Fail = 1;
1076 goto BGC_CONFIG_FAIL;
1077 }
1078
1079 //set BGC mode
1080 if(HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_MODE, pstSecCfg->u32BGCMode == 1 ? BGC_SEC_MODE_STATIC : BGC_SEC_MODE_DYNAMIC) == FALSE)
1081 {
1082 u32Fail = 2;
1083 goto BGC_CONFIG_FAIL;
1084 }
1085
1086 //set protect address and input cmd length
1087 if(HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_LENGTH, 0x4) == FALSE)
1088 {
1089 u32Fail = 3;
1090 goto BGC_CONFIG_FAIL;
1091 }
1092
1093 if((HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_ADDR, (pstSecCfg->u32ProtectAddr & 0x000000FF)>>0) == FALSE) |
1094 (HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_ADDR, (pstSecCfg->u32ProtectAddr & 0x0000FF00)>>8) == FALSE) |
1095 (HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_ADDR, (pstSecCfg->u32ProtectAddr & 0x00FF0000)>>16) == FALSE) |
1096 (HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_ADDR, (pstSecCfg->u32ProtectAddr & 0xFF000000)>>24) == FALSE))
1097 {
1098 u32Fail = 4;
1099 goto BGC_CONFIG_FAIL;
1100 }
1101
1102 //set protect size and input cmd length
1103 if(HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_LENGTH, 0x4) == FALSE)
1104 {
1105 u32Fail = 5;
1106 goto BGC_CONFIG_FAIL;
1107 }
1108 if((HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_SIZE, (pstSecCfg->u32ProtectSize & 0x000000FF)>>0) == FALSE) |
1109 (HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_SIZE, (pstSecCfg->u32ProtectSize & 0x0000FF00)>>8) == FALSE) |
1110 (HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_SIZE, (pstSecCfg->u32ProtectSize & 0x00FF0000)>>16) == FALSE) |
1111 (HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_SIZE, (pstSecCfg->u32ProtectSize & 0xFF000000)>>24) == FALSE))
1112 {
1113 u32Fail = 6;
1114 goto BGC_CONFIG_FAIL;
1115 }
1116
1117 //set interval bwteen two BGC check and input cmd length
1118 if(HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_LENGTH, 0x2) == FALSE)
1119 {
1120 u32Fail = 7;
1121 goto BGC_CONFIG_FAIL;
1122 }
1123 if((HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_INTERVAL, (pstSecCfg->u16Interval & 0x00FF)>>0) == FALSE) |
1124 (HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_INTERVAL, (pstSecCfg->u16Interval & 0xFF00)>>8) == FALSE))
1125 {
1126 u32Fail = 8;
1127 goto BGC_CONFIG_FAIL;
1128 }
1129
1130
1131 //set golden and incput golden length
1132 if(HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_LENGTH, 0x20) == FALSE)
1133 {
1134 u32Fail = 9;
1135 goto BGC_CONFIG_FAIL;
1136 }
1137
1138 for(i = 0 ; i < 0x20 ; i ++)
1139 {
1140 if(HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_GOLDEN, pstSecCfg->u8Golden[i]) == FALSE)
1141 {
1142 u32Fail = 10;
1143 goto BGC_CONFIG_FAIL;
1144 }
1145 }
1146
1147 //set password and incput length
1148 if(HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_LENGTH, 0x4) == FALSE)
1149 {
1150 u32Fail = 11;
1151 goto BGC_CONFIG_FAIL;
1152 }
1153
1154 for(i = 0 ; i < 0x4 ; i ++)
1155 {
1156 if(HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_SET_PASSWD, pstSecCfg->u8ResetPassword[i]) == FALSE)
1157 {
1158 u32Fail = 12;
1159 goto BGC_CONFIG_FAIL;
1160 }
1161 }
1162
1163 //set algorithm to sha256
1164 if(HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_ALGO, BGC_SEC_ALGO_SHA256) == FALSE)
1165 {
1166 u32Fail = 13;
1167 goto BGC_CONFIG_FAIL;
1168 }
1169
1170 //set the reset mode if BGC check fail
1171 if(HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_RESET_MODE, BGC_SEC_RESET_INTERRUPT | BGC_SEC_RESET_SYSTEM) == FALSE)
1172 {
1173 u32Fail = 14;
1174 goto BGC_CONFIG_FAIL;
1175 }
1176
1177 //enable section id
1178 if(HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_ENABLE, TRUE) == FALSE)
1179 {
1180 u32Fail = 15;
1181 goto BGC_CONFIG_FAIL;
1182 }
1183
1184 return TRUE;
1185
1186 BGC_CONFIG_FAIL:
1187 HAL_CA_DEBUG("BGC config fail:%08X\n", u32Fail);
1188 return FALSE;
1189 }
1190
HAL_CA_BGC_ResetSec(MS_U32 u32SecId,const MS_U8 * pu8RstPSWD)1191 MS_BOOL HAL_CA_BGC_ResetSec(MS_U32 u32SecId, const MS_U8* pu8RstPSWD)
1192 {
1193 MS_U32 i = 0;
1194 MS_U32 u32Fail = 0;
1195
1196 if((u32SecId >= BGC_SEC_MAX) || (pu8RstPSWD == NULL))
1197 {
1198 return FALSE;
1199 }
1200
1201 //check bgc mode, if mode = 1, return fail
1202 //set section id
1203 if(HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_SECID, u32SecId) == FALSE)
1204 {
1205 u32Fail = 1;
1206 goto BGC_RESET_FAIL;
1207 }
1208
1209 //set reset password and incput length
1210 if(HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_LENGTH, 0x4) == FALSE)
1211 {
1212 u32Fail = 2;
1213 goto BGC_RESET_FAIL;
1214 }
1215
1216 for(i = 0 ; i < 0x4 ; i ++)
1217 {
1218 if(HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_RESET_PASSWD, pu8RstPSWD[i]) == FALSE)
1219 {
1220 u32Fail = 3;
1221 goto BGC_RESET_FAIL;
1222 }
1223 }
1224 return TRUE;
1225
1226 BGC_RESET_FAIL:
1227 HAL_CA_DEBUG("BGC reset fail:%08X\n", u32Fail);
1228 return FALSE;
1229
1230 }
1231
HAL_CA_OTP_IsBlank(MS_U32 addr)1232 MS_BOOL HAL_CA_OTP_IsBlank(MS_U32 addr)
1233 {
1234 MS_U32 value;
1235
1236 if(addr >= CA_OTP_SIZE)
1237 return 0;
1238
1239 value = *(volatile MS_U32 *)(_u32REG_OTP_Base + addr);
1240
1241 return value == 0;
1242 }
1243
1244
_HAL_CA_OTP_Read_Real(MS_U32 addr,MS_BOOL bXor)1245 MS_U32 _HAL_CA_OTP_Read_Real(MS_U32 addr, MS_BOOL bXor)
1246 {
1247 MS_U32 value;
1248
1249 if(addr >= CA_OTP_SIZE)
1250 return 0;
1251
1252 value = *(volatile MS_U32 *)(_u32REG_OTP_Base + addr);
1253
1254 return value;
1255 }
1256
1257
HAL_CA_OTP_Read(MS_U32 addr)1258 MS_U32 HAL_CA_OTP_Read(MS_U32 addr)
1259 {
1260 return _HAL_CA_OTP_Read_Real(addr, FALSE);
1261 }
1262
1263
_HAL_CA_OTP_Write_Real(MS_U32 addr,MS_U8 value)1264 MS_BOOL _HAL_CA_OTP_Write_Real(MS_U32 addr, MS_U8 value)
1265 {
1266 MS_DEBUG_MSG(printf("[_HAL_CA_OTP_Write_Real] addr=0x%04lx value=0x%02lx\n", addr, (MS_U32)value);)
1267 #if 0
1268 printf("[_HAL_CA_OTP_Write_Real] NO REAL WRITE!!!\n");
1269 #else
1270 *(volatile MS_U8 *)(_u32REG_OTP_Base + addr) = value;
1271 #endif
1272
1273 MS_U32 v;
1274 v = REG32(REG_OTP_CTRL_PV) & REG_OTP_CTRL_PG_VERIFY_FAIL_FLAG;
1275 if(v == 0) {
1276 return TRUE;
1277 }
1278
1279 HAL_CA_DEBUG("[_HAL_CA_OTP_Write_Real] PV fail (0x%08x)\n", v);
1280 return FALSE;
1281 }
1282
HAL_CA_OTP_Write(MS_U32 addr,MS_U32 value)1283 MS_BOOL HAL_CA_OTP_Write(MS_U32 addr, MS_U32 value)
1284 {
1285 int i;
1286 if(addr >= CA_OTP_SIZE)
1287 return FALSE;
1288
1289 if(addr % 4 != 0)
1290 return FALSE;
1291
1292 REG32(REG_OTP_CTRL_0) = REG_OTP_CTRL_0_VALUE;
1293
1294 MS_U32 orig = _HAL_CA_OTP_Read_Real(addr, TRUE);
1295 MS_U32 write = value & (orig ^ value); // only write the bit from 0 to 1
1296
1297 if(write == 0)
1298 return TRUE;
1299
1300 for(i = 0; i < 4; i++) {
1301 if(_HAL_CA_OTP_Write_Real(addr + i, (value >> (i * 8)) & 0xff) == FALSE)
1302 return FALSE;
1303 }
1304
1305 MS_U32 result = _HAL_CA_OTP_Read_Real(addr, TRUE);
1306 if((result & value) == value) // only check the bit 1
1307 {
1308 return TRUE;
1309 }
1310
1311 return FALSE;
1312 }
1313
_HAL_CA_OTP_GetConfig(MS_U32 u32Idx,MS_U32 * pu32Value)1314 MS_BOOL _HAL_CA_OTP_GetConfig(MS_U32 u32Idx, MS_U32 *pu32Value)
1315 {
1316 MS_U32 u32Addr = _HAL_CA_OTP_Addr[u32Idx].u32Addr;
1317 MS_U32 u32Shift = _HAL_CA_OTP_Addr[u32Idx].u32Lo;
1318 MS_U32 u32Len = _HAL_CA_OTP_Addr[u32Idx].u32Hi - _HAL_CA_OTP_Addr[u32Idx].u32Lo + 1;
1319 MS_U32 u32Mask = bitmask(_HAL_CA_OTP_Addr[u32Idx].u32Hi, _HAL_CA_OTP_Addr[u32Idx].u32Lo);
1320
1321 if(pu32Value == NULL)
1322 return FALSE;
1323
1324 if(u32Len > 32)
1325 return FALSE;
1326
1327 *pu32Value = (HAL_CA_OTP_Read(u32Addr) & u32Mask) >> u32Shift;
1328
1329 return TRUE;
1330 }
1331
_HAL_CA_OTP_SetConfig(MS_U32 u32Idx,MS_U32 u32Value)1332 MS_BOOL _HAL_CA_OTP_SetConfig(MS_U32 u32Idx, MS_U32 u32Value)
1333 {
1334 //printf("[_HAL_CA_OTP_SetConfig] u32Idx=%ld u32Value=0x%08lx\n", u32Idx, u32Value);
1335
1336 MS_U32 u32Addr = _HAL_CA_OTP_Addr[u32Idx].u32Addr;
1337 MS_U32 u32Shift = _HAL_CA_OTP_Addr[u32Idx].u32Lo;
1338 MS_U32 u32Len = _HAL_CA_OTP_Addr[u32Idx].u32Hi - _HAL_CA_OTP_Addr[u32Idx].u32Lo + 1;
1339 MS_U32 u32Mask = bitmask(_HAL_CA_OTP_Addr[u32Idx].u32Hi, _HAL_CA_OTP_Addr[u32Idx].u32Lo);
1340
1341 if(u32Len > 32)
1342 return FALSE;
1343
1344 u32Value = (u32Value << u32Shift) & u32Mask;
1345
1346 return HAL_CA_OTP_Write(u32Addr, u32Value);
1347 }
1348
HAL_CA_OTP_EnableSecureBoot(void)1349 MS_BOOL HAL_CA_OTP_EnableSecureBoot(void)
1350 {
1351 return _HAL_CA_OTP_SetConfig(U_OTP_SBoot, 0xf);
1352 }
1353
HAL_CA_OTP_IsSecureBootEnabled(void)1354 MS_BOOL HAL_CA_OTP_IsSecureBootEnabled(void)
1355 {
1356 MS_U32 u32Value = 0;
1357 MS_BOOL ret = FALSE;
1358
1359 ret = _HAL_CA_OTP_GetConfig(U_OTP_SBoot, &u32Value);
1360
1361 if (ret == FALSE)
1362 {
1363 return FALSE;
1364 }
1365 return u32Value != 0;
1366 }
1367
1368
HAL_CA_OTP_SetBlockLock(MS_U32 u32Start,MS_U32 u32End,CA_LOCK_TYPE eLockType)1369 MS_BOOL HAL_CA_OTP_SetBlockLock(MS_U32 u32Start, MS_U32 u32End, CA_LOCK_TYPE eLockType)
1370 {
1371 //Kano not support
1372 MS_DEBUG_MSG(printf("[%s][%d] do not support Kano\n", __FUNCTION__, __LINE__));
1373 return FALSE;
1374 }
1375
HAL_CA_OTP_GetBlockLock(MS_U32 * pu32Start,MS_U32 * pu32End,CA_LOCK_TYPE * peLockType)1376 MS_BOOL HAL_CA_OTP_GetBlockLock(MS_U32 *pu32Start, MS_U32 *pu32End, CA_LOCK_TYPE *peLockType)
1377 {
1378 //Kano not support
1379 MS_DEBUG_MSG(printf("[%s][%d] do not support Kano\n", __FUNCTION__, __LINE__));
1380 return FALSE;
1381 }
1382
1383
1384 //=======================================================
1385 // RSA bank for Secure Range
1386 //=======================================================
1387
HAL_CA_RSA_SetSecureRange(MS_U32 u32SecSet,MS_U32 u32SecStart,MS_U32 u32SecEnd)1388 MS_BOOL HAL_CA_RSA_SetSecureRange(MS_U32 u32SecSet, MS_U32 u32SecStart, MS_U32 u32SecEnd)
1389 {
1390 if(u32SecSet > REG_RSA_SEC_RANGE_SET || u32SecEnd <= u32SecStart)
1391 return FALSE;
1392
1393 *(volatile MS_U32*) (_u32REGBase + REG_RSA_SEC_RANGE_START(u32SecSet)) = REG_RSA_SEC_RANGE_ENABLE | ( u32SecStart & REG_RSA_SEC_RANGE_MASK);
1394 *(volatile MS_U32*) (_u32REGBase + REG_RSA_SEC_RANGE_END(u32SecSet)) = REG_RSA_SEC_RANGE_ENABLE | ( u32SecEnd & REG_RSA_SEC_RANGE_MASK);
1395
1396 return TRUE;
1397 }
1398
HAL_CA_OTP_Lock(CA_OTP_LOCK eLock)1399 MS_BOOL HAL_CA_OTP_Lock(CA_OTP_LOCK eLock)
1400 {
1401 switch(eLock)
1402 {
1403 // Boot Area
1404 case E_BOOT_LockWord_W0000_0511_Addr:
1405 return _HAL_CA_OTP_SetConfig(U_OTP_LockWord_0000_0511_W, 0x3);
1406 case E_BOOT_LockWord_W0512_1023_Addr:
1407 return _HAL_CA_OTP_SetConfig(U_OTP_LockWord_0512_1023_W, 0x3);
1408 case E_BOOT_LockWord_W1024_1535_Addr:
1409 return _HAL_CA_OTP_SetConfig(U_OTP_LockWord_1024_1535_W, 0x3);
1410 case E_BOOT_LockWord_W1536_2047_Addr:
1411 return _HAL_CA_OTP_SetConfig(U_OTP_LockWord_1536_2047_W, 0x3);
1412 case E_BOOT_LockWord_W2048_2559_Addr:
1413 return _HAL_CA_OTP_SetConfig(U_OTP_LockWord_2048_2559_W, 0x3);
1414 case E_BOOT_LockWord_W2560_3071_Addr:
1415 return _HAL_CA_OTP_SetConfig(U_OTP_LockWord_2560_3071_W, 0x3);
1416 case E_BOOT_LockWord_W3072_3391_Addr:
1417 return _HAL_CA_OTP_SetConfig(U_OTP_LockWord_3072_3391_W, 0x3);
1418
1419 // IDs
1420 case E_LockWord_v_PubOtpOID:
1421 return _HAL_CA_OTP_SetConfig(U_OTP_LockWord_v_PubOtpOID_W, 0x3);
1422 case E_LockWord_v_PubOtpVID:
1423 return _HAL_CA_OTP_SetConfig(U_OTP_LockWord_v_PubOtpVID_W, 0x3);
1424 case E_LockWord_v_pubOtpUniqueID1:
1425 return _HAL_CA_OTP_SetConfig(U_OTP_LockWord_PubOTPUniqueID1_W, 0x3);
1426 case E_LockWord_v_pubOtpUniqueID2:
1427 return _HAL_CA_OTP_SetConfig(U_OTP_LockWord_PubOTPUniqueID2_W, 0x3);
1428 case E_LockWord_v_pubOtpUniqueID3:
1429 return _HAL_CA_OTP_SetConfig(U_OTP_LockWord_PubOTPUniqueID3_W, 0x3);
1430 case E_LockWord_v_pubOtpUniqueID4:
1431 return _HAL_CA_OTP_SetConfig(U_OTP_LockWord_PubOTPUniqueID4_W, 0x3);
1432 case E_LockWord_CA_MSID:
1433 return _HAL_CA_OTP_SetConfig(U_OTP_LockWord_MSID_W, 0x3);
1434
1435 //CA_SecretKey
1436 case E_LockWord_CAV_SecretKey6_W:
1437 return _HAL_CA_OTP_SetConfig(U_OTP_LockWord_CAV_Key6_W, 0x3);
1438 case E_LockWord_CAV_SecretKey6_R:
1439 return _HAL_CA_OTP_SetConfig(U_OTP_LockWord_CAV_Key6_R, 0x3);
1440
1441 //RSA_Key
1442 case E_LockWord_RSA_1_W:
1443 return _HAL_CA_OTP_SetConfig(U_OTP_LockWord_RSA_1_W, 0x3);
1444
1445 //Debug ports
1446 case E_LockWord_Debugport_PWD_W:
1447 return _HAL_CA_OTP_SetConfig(U_OTP_LockWord_CA_PWD_W, 0x3);
1448 case E_LockWord_Debugport_PWD_R:
1449 return _HAL_CA_OTP_SetConfig(U_OTP_LockWord_CA_PWD_R, 0x3);
1450
1451 // Reserved
1452 case E_LockWord_CA_reserved0:
1453 return _HAL_CA_OTP_SetConfig(U_OTP_LockWord_CA_reserved0_W, 0x3);
1454 case E_LockWord_CA_reserved1:
1455 return _HAL_CA_OTP_SetConfig(U_OTP_LockWord_CA_reserved1_W, 0x3);
1456 case E_LockWord_CA_reserved2:
1457 return _HAL_CA_OTP_SetConfig(U_OTP_LockWord_CA_reserved2_W, 0x3);
1458 case E_LockWord_CA_reserved3:
1459 return _HAL_CA_OTP_SetConfig(U_OTP_LockWord_CA_reserved3_W, 0x3);
1460
1461 default:
1462 return FALSE;
1463 }
1464 }
1465
HAL_CA_Locked(CA_OTP_LOCK eLock)1466 MS_BOOL HAL_CA_Locked(CA_OTP_LOCK eLock)
1467 {
1468 MS_U32 u32Value = 0;
1469 MS_BOOL ret = FALSE;
1470 switch(eLock)
1471 {
1472 // Boot Area
1473 case E_BOOT_LockWord_W0000_0511_Addr:
1474 ret = _HAL_CA_OTP_GetConfig(U_OTP_LockWord_0000_0511_W, &u32Value);
1475 break;
1476 case E_BOOT_LockWord_W0512_1023_Addr:
1477 ret = _HAL_CA_OTP_GetConfig(U_OTP_LockWord_0512_1023_W, &u32Value);
1478 break;
1479 case E_BOOT_LockWord_W1024_1535_Addr:
1480 ret = _HAL_CA_OTP_GetConfig(U_OTP_LockWord_1024_1535_W, &u32Value);
1481 break;
1482 case E_BOOT_LockWord_W1536_2047_Addr:
1483 ret = _HAL_CA_OTP_GetConfig(U_OTP_LockWord_1536_2047_W, &u32Value);
1484 break;
1485 case E_BOOT_LockWord_W2048_2559_Addr:
1486 ret = _HAL_CA_OTP_GetConfig(U_OTP_LockWord_2048_2559_W, &u32Value);
1487 break;
1488 case E_BOOT_LockWord_W2560_3071_Addr:
1489 ret = _HAL_CA_OTP_GetConfig(U_OTP_LockWord_2560_3071_W, &u32Value);
1490 break;
1491 case E_BOOT_LockWord_W3072_3391_Addr:
1492 ret = _HAL_CA_OTP_GetConfig(U_OTP_LockWord_3072_3391_W, &u32Value);
1493 break;
1494
1495 // IDs
1496 case E_LockWord_v_PubOtpOID:
1497 ret = _HAL_CA_OTP_GetConfig(U_OTP_LockWord_v_PubOtpOID_W, &u32Value);
1498 break;
1499 case E_LockWord_v_PubOtpVID:
1500 ret = _HAL_CA_OTP_GetConfig(U_OTP_LockWord_v_PubOtpVID_W, &u32Value);
1501 break;
1502 case E_LockWord_v_pubOtpUniqueID1:
1503 ret = _HAL_CA_OTP_GetConfig(U_OTP_LockWord_PubOTPUniqueID1_W, &u32Value);
1504 break;
1505 case E_LockWord_v_pubOtpUniqueID2:
1506 ret = _HAL_CA_OTP_GetConfig(U_OTP_LockWord_PubOTPUniqueID2_W, &u32Value);
1507 break;
1508 case E_LockWord_v_pubOtpUniqueID3:
1509 ret = _HAL_CA_OTP_GetConfig(U_OTP_LockWord_PubOTPUniqueID3_W, &u32Value);
1510 break;
1511 case E_LockWord_v_pubOtpUniqueID4:
1512 ret = _HAL_CA_OTP_GetConfig(U_OTP_LockWord_PubOTPUniqueID4_W, &u32Value);
1513 break;
1514 case E_LockWord_CA_MSID:
1515 ret = _HAL_CA_OTP_GetConfig(U_OTP_LockWord_MSID_W, &u32Value);
1516 break;
1517
1518 //CA_SecretKey
1519 case E_LockWord_CAV_SecretKey6_W:
1520 ret = _HAL_CA_OTP_GetConfig(U_OTP_LockWord_CAV_Key6_W, &u32Value);
1521 break;
1522 case E_LockWord_CAV_SecretKey6_R:
1523 ret = _HAL_CA_OTP_GetConfig(U_OTP_LockWord_CAV_Key6_R, &u32Value);
1524 break;
1525
1526 //RSA_Key
1527 case E_LockWord_RSA_1_W:
1528 ret = _HAL_CA_OTP_GetConfig(U_OTP_LockWord_RSA_1_W, &u32Value);
1529 break;
1530
1531 //Debug ports
1532 case E_LockWord_Debugport_PWD_W:
1533 ret = _HAL_CA_OTP_GetConfig(U_OTP_LockWord_CA_PWD_W, &u32Value);
1534 break;
1535 case E_LockWord_Debugport_PWD_R:
1536 ret = _HAL_CA_OTP_GetConfig(U_OTP_LockWord_CA_PWD_R, &u32Value);
1537 break;
1538
1539 // Reserved
1540 case E_LockWord_CA_reserved0:
1541 ret = _HAL_CA_OTP_GetConfig(U_OTP_LockWord_CA_reserved0_W, &u32Value);
1542 break;
1543 case E_LockWord_CA_reserved1:
1544 ret = _HAL_CA_OTP_GetConfig(U_OTP_LockWord_CA_reserved1_W, &u32Value);
1545 break;
1546 case E_LockWord_CA_reserved2:
1547 ret = _HAL_CA_OTP_GetConfig(U_OTP_LockWord_CA_reserved2_W, &u32Value);
1548 break;
1549 case E_LockWord_CA_reserved3:
1550 ret = _HAL_CA_OTP_GetConfig(U_OTP_LockWord_CA_reserved3_W, &u32Value);
1551 break;
1552
1553 default:
1554 ret = FALSE;
1555 }
1556
1557 if(ret == FALSE)
1558 return FALSE;
1559
1560 if(u32Value == 0x01) // 0x01 : unlock, xx : locked
1561 return FALSE;
1562
1563 return TRUE;
1564 }
1565
HAL_CA_OTP_SetRSAextID(MS_U32 u32Value)1566 MS_BOOL HAL_CA_OTP_SetRSAextID(MS_U32 u32Value)
1567 {
1568 return _HAL_CA_OTP_SetConfig(U_OTP_MSID, u32Value);
1569 }
1570
HAL_CA_OTP_GetRSAextID(void)1571 MS_U32 HAL_CA_OTP_GetRSAextID(void)
1572 {
1573
1574 MS_U32 u32Value = 0;
1575 MS_BOOL ret = FALSE;
1576
1577 ret = _HAL_CA_OTP_GetConfig(U_OTP_MSID, &u32Value);
1578
1579 if (ret == FALSE)
1580 {
1581 return FALSE;
1582 }
1583 return u32Value;
1584 }
1585
1586
HAL_CA_OTP_SetHASH_REF_VER_Ex(MS_U32 u32HASH0_REF_VER,MS_U32 u32HASH1_REF_VER,MS_U32 u32HASH2_REF_VER)1587 MS_BOOL HAL_CA_OTP_SetHASH_REF_VER_Ex(MS_U32 u32HASH0_REF_VER, MS_U32 u32HASH1_REF_VER, MS_U32 u32HASH2_REF_VER)
1588 {
1589 if(_HAL_CA_OTP_SetConfig(U_OTP_HASH0_VER_REF, u32HASH0_REF_VER) == FALSE)
1590 {
1591 return FALSE;
1592 }
1593
1594 if(_HAL_CA_OTP_SetConfig(U_OTP_HASH1_VER_REF, u32HASH1_REF_VER) == FALSE)
1595 {
1596 return FALSE;
1597 }
1598
1599 if(_HAL_CA_OTP_SetConfig(U_OTP_HASH2_VER_REF, u32HASH2_REF_VER) == FALSE)
1600 {
1601 return FALSE;
1602 }
1603
1604 return TRUE;
1605 }
1606
HAL_CA_OTP_GetHASH_REF_VER_Ex(MS_U32 * pu32HASH0_REF_VER,MS_U32 * pu32HASH1_REF_VER,MS_U32 * pu32HASH2_REF_VER)1607 MS_BOOL HAL_CA_OTP_GetHASH_REF_VER_Ex(MS_U32 *pu32HASH0_REF_VER, MS_U32 *pu32HASH1_REF_VER, MS_U32 *pu32HASH2_REF_VER)
1608 {
1609 MS_U32 u32Value = 0;
1610
1611 if(pu32HASH0_REF_VER != NULL)
1612 {
1613 if(_HAL_CA_OTP_GetConfig(U_OTP_HASH0_VER_REF, &u32Value) == FALSE)
1614 {
1615 return FALSE;
1616 }
1617
1618 *pu32HASH0_REF_VER = (u32Value);
1619 }
1620
1621 if(pu32HASH1_REF_VER != NULL)
1622 {
1623 if(_HAL_CA_OTP_GetConfig(U_OTP_HASH1_VER_REF, &u32Value) == FALSE)
1624 {
1625 return FALSE;
1626 }
1627 *pu32HASH1_REF_VER = (u32Value);
1628 }
1629
1630 if(pu32HASH2_REF_VER != NULL)
1631 {
1632 if(_HAL_CA_OTP_GetConfig(U_OTP_HASH2_VER_REF, &u32Value) == FALSE)
1633 {
1634 return FALSE;
1635 }
1636
1637 *pu32HASH2_REF_VER = (u32Value);
1638 }
1639
1640 return TRUE;
1641 }
1642
HAL_CA_OTP_SetHASH1_REF_VER(MS_U32 u32HASH1_REF_VER)1643 MS_BOOL HAL_CA_OTP_SetHASH1_REF_VER(MS_U32 u32HASH1_REF_VER)
1644 {
1645 if(HAL_CA_OTP_SetHASH_REF_VER_Ex(0, u32HASH1_REF_VER, 0) == FALSE)
1646 {
1647 return FALSE;
1648 }
1649
1650 return TRUE;
1651 }
1652
HAL_CA_OTP_GetHASH1_REF_VER(MS_U32 * pu32HASH1_REF_VER)1653 MS_BOOL HAL_CA_OTP_GetHASH1_REF_VER(MS_U32 *pu32HASH1_REF_VER)
1654 {
1655 if(HAL_CA_OTP_GetHASH_REF_VER_Ex(NULL, pu32HASH1_REF_VER, NULL) == FALSE)
1656 {
1657 return FALSE;
1658 }
1659
1660 return TRUE;
1661 }
1662
1663
HAL_CA_OTP_SetHASH_REF_VER(MS_U32 u32HASH0_REF_VER,MS_U32 u32HASH2_REF_VER)1664 MS_BOOL HAL_CA_OTP_SetHASH_REF_VER(MS_U32 u32HASH0_REF_VER, MS_U32 u32HASH2_REF_VER)
1665 {
1666 if(HAL_CA_OTP_SetHASH_REF_VER_Ex(u32HASH0_REF_VER, 0, u32HASH2_REF_VER) == FALSE)
1667 {
1668 return FALSE;
1669 }
1670
1671 return TRUE;
1672 }
1673
HAL_CA_OTP_GetHASH_REF_VER(MS_U32 * pu32HASH0_REF_VER,MS_U32 * pu32HASH2_REF_VER)1674 MS_BOOL HAL_CA_OTP_GetHASH_REF_VER(MS_U32 *pu32HASH0_REF_VER, MS_U32 *pu32HASH2_REF_VER)
1675 {
1676 if(HAL_CA_OTP_GetHASH_REF_VER_Ex(pu32HASH0_REF_VER, NULL, pu32HASH2_REF_VER) == FALSE)
1677 {
1678 return FALSE;
1679 }
1680
1681 return TRUE;
1682 }
1683
1684
HAL_CA_MaxDeviceIdSize(void)1685 MS_U32 HAL_CA_MaxDeviceIdSize(void)
1686 {
1687 return MAX_DEVICEID_SIZE;
1688 }
1689
HAL_CA_OTP_SetDeviceId(const MS_U8 * pu8Did,MS_U32 u32Size)1690 MS_BOOL HAL_CA_OTP_SetDeviceId(const MS_U8 *pu8Did, MS_U32 u32Size)
1691 {
1692 MS_U32 did[8] = {0};
1693 MS_U32 i, u32Addr;
1694 MS_U32 Did_Size = 2;
1695 MS_U8 *p = (MS_U8 *)did;
1696
1697 for(i = 0; i < sizeof(did) && i < u32Size; i++)
1698 {
1699 p[i] = pu8Did[i];
1700 }
1701
1702 u32Addr = _HAL_CA_OTP_Addr[U_OTP_v_pubOtpUniqueID1].u32Addr;
1703 for(i = 0; i < Did_Size; i++)
1704 {
1705 if(HAL_CA_OTP_Write(u32Addr,did[i]) == FALSE)
1706 {
1707 return FALSE;
1708 }
1709 u32Addr += 4;
1710 }
1711 u32Addr = _HAL_CA_OTP_Addr[U_OTP_v_pubOtpUniqueID2].u32Addr;
1712 for(i = Did_Size; i < (2*Did_Size); i++)
1713 {
1714 if(HAL_CA_OTP_Write(u32Addr,did[i]) == FALSE)
1715 {
1716 return FALSE;
1717 }
1718 u32Addr += 4;
1719 }
1720 u32Addr = _HAL_CA_OTP_Addr[U_OTP_v_pubOtpUniqueID3].u32Addr;
1721 for(i = (2*Did_Size); i < (3*Did_Size); i++)
1722 {
1723 if(HAL_CA_OTP_Write(u32Addr,did[i]) == FALSE)
1724 {
1725 return FALSE;
1726 }
1727 u32Addr += 4;
1728 }
1729 u32Addr = _HAL_CA_OTP_Addr[U_OTP_v_pubOtpUniqueID4].u32Addr;
1730 for(i = (3*Did_Size); i < (4*Did_Size); i++)
1731 {
1732 if(HAL_CA_OTP_Write(u32Addr,did[i]) == FALSE)
1733 {
1734 return FALSE;
1735 }
1736 u32Addr += 4;
1737 }
1738
1739 return TRUE;
1740 }
1741
HAL_CA_OTP_GetDeviceId(MS_U8 * pu8Did,MS_U32 u32Size)1742 MS_BOOL HAL_CA_OTP_GetDeviceId(MS_U8 *pu8Did, MS_U32 u32Size)
1743 {
1744 MS_U32 did[8] = {0};
1745 MS_U32 Did_Size = 2;
1746 MS_U32 i, u32Addr;
1747 MS_U8 *p = (MS_U8 *)did;
1748
1749 u32Addr = _HAL_CA_OTP_Addr[U_OTP_v_pubOtpUniqueID1].u32Addr;
1750 for(i = 0; i < Did_Size; i++)
1751 {
1752 did[i] = HAL_CA_OTP_Read(u32Addr);
1753 u32Addr += 4;
1754 }
1755 u32Addr = _HAL_CA_OTP_Addr[U_OTP_v_pubOtpUniqueID2].u32Addr;
1756 for(i = Did_Size; i < (2*Did_Size) ; i++)
1757 {
1758 did[i] = HAL_CA_OTP_Read(u32Addr);
1759 u32Addr += 4;
1760 }
1761 u32Addr = _HAL_CA_OTP_Addr[U_OTP_v_pubOtpUniqueID3].u32Addr;
1762 for(i = (2*Did_Size) ; i < (3*Did_Size) ; i++)
1763 {
1764 did[i] = HAL_CA_OTP_Read(u32Addr);
1765 u32Addr += 4;
1766 }
1767 u32Addr = _HAL_CA_OTP_Addr[U_OTP_v_pubOtpUniqueID4].u32Addr;
1768 for(i = (3*Did_Size); i < (4*Did_Size) ; i++)
1769 {
1770 did[i] = HAL_CA_OTP_Read(u32Addr);
1771 u32Addr += 4;
1772 }
1773
1774 for(i = 0; i < sizeof(did) && i < u32Size; i++)
1775 {
1776 pu8Did[i] = p[i];
1777 }
1778
1779 return TRUE;
1780 }
1781
1782
HAL_CA_OTP_SetDebugPortMode(CA_DEBUG_PORT eDebugPort,CA_DEBUG_PORT_MODE eMode)1783 MS_BOOL HAL_CA_OTP_SetDebugPortMode(CA_DEBUG_PORT eDebugPort, CA_DEBUG_PORT_MODE eMode)
1784 {
1785 MS_U32 idx = 0;
1786 MS_U32 v = 0;
1787
1788 switch(eDebugPort)
1789 {
1790 case E_CA_DEBUG_PORT_I2C:
1791 idx = U_OTP_I2C_MODE;
1792 break;
1793 case E_CA_DEBUG_PORT_JTAG:
1794 idx = U_OTP_EJTAG_MODE;
1795 break;
1796 case E_CA_DEBUG_PORT_SCAN:
1797 idx = U_OTP_SCAN_MODE;
1798 break;
1799 default:
1800 return FALSE;
1801 }
1802
1803 switch(eMode)
1804 {
1805 case E_CA_DEBUG_PORT_OPEN:
1806 return TRUE;
1807 case E_CA_DEBUG_PORT_PASSWD:
1808 v = 0x7;
1809 break;
1810 case E_CA_DEBUG_PORT_CLOSE:
1811 v = 0x3f;
1812 break;
1813 default:
1814 return FALSE;
1815 }
1816
1817 return _HAL_CA_OTP_SetConfig(idx, v);
1818
1819 }
1820
1821
HAL_CA_OTP_GetDebugPortMode(CA_DEBUG_PORT eDebugPort,CA_DEBUG_PORT_MODE * eMode)1822 MS_BOOL HAL_CA_OTP_GetDebugPortMode(CA_DEBUG_PORT eDebugPort, CA_DEBUG_PORT_MODE *eMode)
1823 {
1824 MS_U32 v = 0;
1825 MS_BOOL ret = FALSE;
1826
1827 if(eMode == NULL)
1828 {
1829 return FALSE;
1830 }
1831
1832 switch(eDebugPort)
1833 {
1834 case E_CA_DEBUG_PORT_I2C:
1835 ret = _HAL_CA_OTP_GetConfig(U_OTP_I2C_MODE, &v);
1836 break;
1837 case E_CA_DEBUG_PORT_JTAG:
1838 ret = _HAL_CA_OTP_GetConfig(U_OTP_EJTAG_MODE, &v);
1839 break;
1840 case E_CA_DEBUG_PORT_SCAN:
1841 ret = _HAL_CA_OTP_GetConfig(U_OTP_SCAN_MODE, &v);
1842 break;
1843 default:
1844 return FALSE;
1845 }
1846
1847 if (ret == FALSE)
1848 {
1849 return FALSE;
1850 }
1851
1852 if(v & 0x38)
1853 {
1854 *eMode = E_CA_DEBUG_PORT_CLOSE;
1855 }
1856 else if(v)
1857 {
1858 *eMode = E_CA_DEBUG_PORT_PASSWD;
1859 }
1860 else
1861 {
1862 *eMode = E_CA_DEBUG_PORT_OPEN;
1863 }
1864
1865 return TRUE;
1866 }
1867
1868
1869 // This function is created to used for another hal driver: NSK2
HAL_CA_OTP_GetCfg(MS_U32 u32Idx,MS_U32 * pu32Value)1870 MS_BOOL HAL_CA_OTP_GetCfg(MS_U32 u32Idx,MS_U32 * pu32Value)
1871 {
1872 return _HAL_CA_OTP_GetConfig(u32Idx, pu32Value);
1873 }
1874
HAL_CA_OTP_EnableSecureCWMode(void)1875 MS_BOOL HAL_CA_OTP_EnableSecureCWMode(void)
1876 {
1877 return _HAL_CA_OTP_SetConfig(U_OTP_ena_ACPU2KT, 0xF);
1878 }
1879
HAL_CA_OTP_IsSecureCWMode(void)1880 MS_BOOL HAL_CA_OTP_IsSecureCWMode(void)
1881 {
1882 MS_U32 u32Value = 0;
1883 MS_BOOL ret = FALSE;
1884 ret = _HAL_CA_OTP_GetConfig(U_OTP_ena_ACPU2KT, &u32Value);
1885
1886 if (ret == FALSE)
1887 {
1888 return FALSE;
1889 }
1890
1891 if(u32Value == 1)
1892 {
1893 return FALSE;
1894 }
1895 else
1896 {
1897 return TRUE;
1898 }
1899 }
1900
_HAL_CA_Random(void)1901 MS_U16 _HAL_CA_Random(void)
1902 {
1903 MS_U32 n = 0;
1904
1905 REG32(REG_RNG_TRNG) |= REG_RNG_TRNG_ACK;// Every one can read this value so it can not be trusted.
1906
1907 do{
1908 n = REG32(REG_RNG_TRNG);
1909 if( n & REG_RNG_TRNG_VALID_MASK) //check valid
1910 {
1911 n &= REG_RNG_TRNG_OUT_MASK; // Request a trusted value to RNG
1912 break;
1913 }
1914 }while(1);
1915
1916 REG32(REG_RNG_TRNG) |= REG_RNG_TRNG_ACK;// Request a new value to RNG to prevent an other process to read the generated value.
1917
1918 return n;
1919 }
1920
1921
HAL_CA_Random(void)1922 MS_U32 HAL_CA_Random(void)
1923 {
1924 MS_U32 u32Val = 0;
1925
1926 u32Val += _HAL_CA_Random()<<16;
1927 u32Val += _HAL_CA_Random();
1928
1929 return u32Val;
1930
1931 }
1932
HAL_CA_OTP_ReadCAVendor(void)1933 MS_U32 HAL_CA_OTP_ReadCAVendor(void)
1934 {
1935 MS_U32 u32CAV_Key_VendorID[CA_SCK_NUM] = {0}; // Store all VendorID
1936 MS_U32 u32CAV_Key_VendorID_Hi = 24; //High bit of VendorID in Key property
1937 MS_U32 u32CAV_Key_VendorID_Lo = 20; //Low bit of VendorID in Key property
1938
1939 MS_U32 u32CAV1_VendorID = 0;
1940 MS_U32 u32CAV2_VendorID = 0;
1941 MS_U32 u32CAV_Vendor = 0;
1942 MS_U32 u32CAV_Vendor_Shift = 16;
1943 MS_U32 u32CAV_Vendor_Num = 0; // Calculate how many different VendorID
1944
1945 MS_U32 u32Idx = 0;
1946 MS_U32 u32Addr = 0;
1947 MS_U32 u32Shift = 0;
1948 MS_U32 u32Len = 0;
1949 MS_U32 u32Mask = 0;
1950
1951 // Read VendorID of U_OTP_CAV_Keyn_Property
1952 for(u32Idx = 0; u32Idx < CA_SCK_NUM; u32Idx++)
1953 {
1954 u32Addr = _HAL_CA_OTP_Addr[u32Idx + U_OTP_CAV_Key1_Property].u32Addr;
1955 u32Shift = u32CAV_Key_VendorID_Lo;
1956 u32Len = u32CAV_Key_VendorID_Hi - u32CAV_Key_VendorID_Lo + 1;
1957 u32Mask = bitmask(u32CAV_Key_VendorID_Hi, u32CAV_Key_VendorID_Lo);
1958
1959 u32CAV_Key_VendorID[u32Idx] = (HAL_CA_OTP_Read(u32Addr) & u32Mask) >> u32Shift;
1960 }
1961
1962 // Assign VendorID
1963 for(u32Idx = 0; u32Idx < CA_SCK_NUM; u32Idx++)
1964 {
1965 // First non NULL VendorID assign to u32CAV1_VendorID
1966 if( (0 == u32CAV_Vendor_Num) && (CA_OTP_VENDOR_ID_NULL != u32CAV_Key_VendorID[u32Idx]) )
1967 {
1968 u32CAV1_VendorID = u32CAV_Key_VendorID[u32Idx];
1969 u32CAV_Vendor_Num++;
1970 }
1971 // Second non NULL and not u32CAV1_VendorID VendorID assign to u32CAV2_VendorID
1972 else if( (1 == u32CAV_Vendor_Num) && (CA_OTP_VENDOR_ID_NULL != u32CAV_Key_VendorID[u32Idx]) )
1973 {
1974 if(u32CAV1_VendorID != u32CAV_Key_VendorID[u32Idx])
1975 {
1976 u32CAV2_VendorID = u32CAV_Key_VendorID[u32Idx];
1977 u32CAV_Vendor_Num++;
1978 }
1979 }
1980 // If third non NULL, not u32CAV1_VendorID and not u32CAV2_VendorID VendorID
1981 else if( (2 <= u32CAV_Vendor_Num) && (CA_OTP_VENDOR_ID_NULL != u32CAV_Key_VendorID[u32Idx]) )
1982 {
1983 if( (u32CAV1_VendorID != u32CAV_Key_VendorID[u32Idx]) && (u32CAV2_VendorID != u32CAV_Key_VendorID[u32Idx]) )
1984 {
1985 u32CAV1_VendorID = CA_OTP_VENDOR_ID_UNKNOW;
1986 u32CAV2_VendorID = CA_OTP_VENDOR_ID_UNKNOW;
1987 u32CAV_Vendor_Num++;
1988 }
1989
1990 }
1991 }
1992
1993 // Transform VendorID to Vendor code
1994 switch(u32CAV1_VendorID)
1995 {
1996 case CA_OTP_VENDOR_ID_NULL:
1997 break;
1998 case CA_OTP_VENDOR_ID_NDS:
1999 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_NDS;
2000 break;
2001 case CA_OTP_VENDOR_ID_NAGRA:
2002 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_NAGRA;
2003 break;
2004 case CA_OTP_VENDOR_ID_VIACCESS:
2005 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_VIACCESS;
2006 break;
2007 case CA_OTP_VENDOR_ID_IRDETO:
2008 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_IRDETO;
2009 break;
2010 case CA_OTP_VENDOR_ID_VERIMATRIX:
2011 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_VERIMATRIX;
2012 break;
2013 case CA_OTP_VENDOR_ID_SMI:
2014 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_SMI;
2015 break;
2016 case CA_OTP_VENDOR_ID_CONAX:
2017 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_CONAX;
2018 break;
2019 case CA_OTP_VENDOR_ID_LATENS:
2020 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_LATENS;
2021 break;
2022 case CA_OTP_VENDOR_ID_ECHOSTAR:
2023 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_ECHOSTAR;
2024 break;
2025 default:
2026 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_UNKNOW;
2027 }
2028
2029 switch(u32CAV2_VendorID)
2030 {
2031 case CA_OTP_VENDOR_ID_NULL:
2032 break;
2033 case CA_OTP_VENDOR_ID_NDS:
2034 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_NDS << u32CAV_Vendor_Shift;
2035 break;
2036 case CA_OTP_VENDOR_ID_NAGRA:
2037 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_NAGRA << u32CAV_Vendor_Shift;
2038 break;
2039 case CA_OTP_VENDOR_ID_VIACCESS:
2040 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_VIACCESS << u32CAV_Vendor_Shift;
2041 break;
2042 case CA_OTP_VENDOR_ID_IRDETO:
2043 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_IRDETO << u32CAV_Vendor_Shift;
2044 break;
2045 case CA_OTP_VENDOR_ID_VERIMATRIX:
2046 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_VERIMATRIX << u32CAV_Vendor_Shift;
2047 break;
2048 case CA_OTP_VENDOR_ID_SMI:
2049 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_SMI << u32CAV_Vendor_Shift;
2050 break;
2051 case CA_OTP_VENDOR_ID_CONAX:
2052 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_CONAX << u32CAV_Vendor_Shift;
2053 break;
2054 case CA_OTP_VENDOR_ID_LATENS:
2055 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_LATENS << u32CAV_Vendor_Shift;
2056 break;
2057 case CA_OTP_VENDOR_ID_ECHOSTAR:
2058 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_ECHOSTAR << u32CAV_Vendor_Shift;
2059 break;
2060 default:
2061 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_UNKNOW << u32CAV_Vendor_Shift;
2062 }
2063
2064 return u32CAV_Vendor;
2065 }
2066
2067
HAL_CA_STR_SetBank(MS_U32 u32Bank)2068 void HAL_CA_STR_SetBank(MS_U32 u32Bank)
2069 {
2070 _u32REGPMBase = u32Bank;
2071
2072 return;
2073 }
2074
HAL_CA_STR_EnableKey(void)2075 void HAL_CA_STR_EnableKey(void)
2076 {
2077 MS_U16 u16Tmp = 0;
2078 u16Tmp = REG16_PM(REG_STR_KEY);
2079 u16Tmp |= REG_STR_DMA_KEY_VALID;
2080 REG16_PM(REG_STR_KEY) = u16Tmp;
2081
2082 return;
2083 }
2084
HAL_CA_STR_SetMAC(MS_U8 * pu8STRMAC,MS_U32 u32STRMACSize)2085 void HAL_CA_STR_SetMAC(MS_U8* pu8STRMAC, MS_U32 u32STRMACSize)
2086 {
2087 MS_U8 i = 0;
2088
2089 for(i = 0; i < (u32STRMACSize/2); i++) {
2090 REG16_PM(REG_STR_AUTH_RESULT + i*4) = (pu8STRMAC[i*2 + 1]<<8 |pu8STRMAC[i*2]);
2091 }
2092
2093 return;
2094 }
2095
HAL_CA_STR_SetParamAddr(MS_U8 * pu8BAddr)2096 void HAL_CA_STR_SetParamAddr(MS_U8 *pu8BAddr)
2097 {
2098 MS_U16 u16Tmp = 0;
2099
2100 u16Tmp = ((MS_VIRT)pu8BAddr & 0x0000FFFF);
2101 REG16_PM(REG_STR_PTR) = u16Tmp;
2102
2103 u16Tmp = ((MS_VIRT)pu8BAddr & 0xFFFF0000)>>16;
2104 REG16_PM(REG_STR_PTR + 4) = u16Tmp;
2105
2106 return;
2107 }
2108
HAL_CA_STR_EnableWarmBoot(void)2109 void HAL_CA_STR_EnableWarmBoot(void)
2110 {
2111 //Oneway
2112 REG16_PM(REG_WARM_BOOT_IND) = REG_WARM_BOOT_IND_MAGIC;
2113
2114 return;
2115 }
2116
HAL_CA_OTP_SetSecretKey(CA_SECRET_KEY eKeySel,const MS_U8 * pu8SecretKey,MS_U32 u32Size)2117 MS_BOOL HAL_CA_OTP_SetSecretKey(CA_SECRET_KEY eKeySel, const MS_U8 *pu8SecretKey, MS_U32 u32Size)
2118 {
2119
2120 MS_U32 secret_key[4] = {0};
2121 MS_U32 i, j, u32Addr;
2122 MS_U8 *p = (MS_U8 *)secret_key;
2123 switch(eKeySel)
2124 {
2125 case E_CA_SECRET_KEY1:
2126 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CAV_SecretKey1].u32Addr;
2127 break;
2128 case E_CA_SECRET_KEY2:
2129 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CAV_SecretKey2].u32Addr;
2130 break;
2131 case E_CA_SECRET_KEY3:
2132 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CAV_SecretKey3].u32Addr;
2133 break;
2134 case E_CA_SECRET_KEY4:
2135 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CAV_SecretKey4].u32Addr;
2136 break;
2137 case E_CA_SECRET_KEY5:
2138 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CAV_SecretKey5].u32Addr;
2139 break;
2140 case E_CA_SECRET_KEY6:
2141 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CAV_SecretKey6].u32Addr;
2142 break;
2143 case E_CA_SECRET_KEY7:
2144 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CAV_SecretKey7].u32Addr;
2145 break;
2146 case E_CA_SECRET_KEY8:
2147 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CAV_SecretKey8].u32Addr;
2148 break;
2149 default:
2150 return FALSE;
2151 }
2152
2153 if(sizeof(secret_key)>u32Size)
2154 {
2155 j = u32Size;
2156 }
2157 else
2158 {
2159 j=sizeof(secret_key);
2160 }
2161 for(i = 0; i < sizeof(secret_key) && i < u32Size; i++)
2162 {
2163 p[i] = pu8SecretKey[(j-1)-i]; // Array reverse, for user easy viewing
2164 }
2165
2166 for(i = 0; i < 4; i++)
2167 {
2168 if(HAL_CA_OTP_Write(u32Addr,secret_key[i]) == FALSE)
2169 {
2170 return FALSE;
2171 }
2172 u32Addr += 4;
2173 }
2174 return TRUE;
2175 }
2176
HAL_CA_OTP_GetSecretKey(CA_SECRET_KEY eKeySel,MS_U8 * pu8SecretKey,MS_U32 u32Size)2177 MS_BOOL HAL_CA_OTP_GetSecretKey(CA_SECRET_KEY eKeySel, MS_U8 *pu8SecretKey, MS_U32 u32Size)
2178 {
2179 MS_U32 secret_key[4] = {0};
2180 MS_U32 i, j, u32Addr;
2181 MS_U8 *p = (MS_U8 *)secret_key;
2182
2183 switch(eKeySel)
2184 {
2185 case E_CA_SECRET_KEY1:
2186 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CAV_SecretKey1].u32Addr;
2187 break;
2188 case E_CA_SECRET_KEY2:
2189 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CAV_SecretKey2].u32Addr;
2190 break;
2191 case E_CA_SECRET_KEY3:
2192 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CAV_SecretKey3].u32Addr;
2193 break;
2194 case E_CA_SECRET_KEY4:
2195 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CAV_SecretKey4].u32Addr;
2196 break;
2197 case E_CA_SECRET_KEY5:
2198 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CAV_SecretKey5].u32Addr;
2199 break;
2200 case E_CA_SECRET_KEY6:
2201 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CAV_SecretKey6].u32Addr;
2202 break;
2203 case E_CA_SECRET_KEY7:
2204 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CAV_SecretKey7].u32Addr;
2205 break;
2206 case E_CA_SECRET_KEY8:
2207 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CAV_SecretKey8].u32Addr;
2208 break;
2209 default:
2210 return FALSE;
2211 }
2212 for(i = 0; i < 4; i++)
2213 {
2214 secret_key[i] = HAL_CA_OTP_Read(u32Addr);
2215 u32Addr += 4;
2216 }
2217
2218 if(sizeof(secret_key)>u32Size)
2219 {
2220 j = u32Size;
2221 }
2222 else
2223 {
2224 j=sizeof(secret_key);
2225 }
2226
2227 for(i = 0; i < sizeof(secret_key) && i < u32Size; i++)
2228 {
2229 pu8SecretKey[i] = p[(j-1)-i]; // Array reverse, for user easy viewing
2230 }
2231
2232 return TRUE;
2233 }
2234
HAL_CA_OTP_SetRSAKey(CA_RSA_KEY eKeySel,const MS_U8 * pu8RSAKey,MS_U32 u32Size)2235 MS_BOOL HAL_CA_OTP_SetRSAKey(CA_RSA_KEY eKeySel, const MS_U8 *pu8RSAKey, MS_U32 u32Size)
2236 {
2237 MS_U32 RSA_key[64] = {0};
2238 MS_U32 i, u32Addr;
2239 MS_U8 *p = (MS_U8 *)RSA_key;
2240
2241 switch(eKeySel)
2242 {
2243 case E_CA_RSA_KEY0:
2244 return FALSE;
2245 case E_CA_RSA_KEY1:
2246 u32Addr = _HAL_CA_OTP_Addr[U_OTP_RSA_1].u32Addr;
2247 break;
2248 default:
2249 return FALSE;
2250 }
2251
2252 for(i = 0; i < sizeof(RSA_key) && i < u32Size; i++)
2253 {
2254 p[i] = pu8RSAKey[i];
2255 }
2256 for(i = 0; i < 64; i++)
2257 {
2258 if(HAL_CA_OTP_Write(u32Addr,RSA_key[i]) == FALSE)
2259 {
2260 return FALSE;
2261 }
2262 u32Addr += 4;
2263 }
2264
2265 return TRUE;
2266 }
HAL_CA_OTP_GetRSAKey(CA_RSA_KEY eKeySel,MS_U8 * pu8RSAKey,MS_U32 u32Size)2267 MS_BOOL HAL_CA_OTP_GetRSAKey(CA_RSA_KEY eKeySel, MS_U8 *pu8RSAKey, MS_U32 u32Size)
2268 {
2269 MS_U32 RSA_key[64] = {0};
2270 MS_U32 i, u32Addr;
2271 MS_U8 *p = (MS_U8 *)RSA_key;
2272
2273 switch(eKeySel)
2274 {
2275 case E_CA_RSA_KEY0:
2276 return FALSE;
2277 break;
2278 case E_CA_RSA_KEY1:
2279 u32Addr = _HAL_CA_OTP_Addr[U_OTP_RSA_1].u32Addr;
2280 break;
2281 default:
2282 return FALSE;
2283 }
2284 for(i = 0; i < 64; i++)
2285 {
2286 RSA_key[i] = HAL_CA_OTP_Read(u32Addr);
2287 u32Addr += 4;
2288 }
2289 for(i = 0; i < sizeof(RSA_key) && i < u32Size; i++)
2290 {
2291 pu8RSAKey[i] = p[i];
2292 }
2293
2294 return TRUE;
2295 }
2296
2297
HAL_CA_OTP_SetDebugPortPassword(CA_DEBUG_PORT eDebugPort,const MS_U8 * pu8Password,MS_U32 u32Size)2298 MS_BOOL HAL_CA_OTP_SetDebugPortPassword(CA_DEBUG_PORT eDebugPort, const MS_U8 *pu8Password, MS_U32 u32Size)
2299 {
2300
2301 MS_U32 pwd[4] = {0};
2302 MS_U32 i, j, u32Addr;
2303 MS_U8 *p = (MS_U8 *)pwd;
2304
2305 switch(eDebugPort)
2306 {
2307 case E_CA_DEBUG_PORT_I2C:
2308 u32Addr = _HAL_CA_OTP_Addr[U_OTP_I2C_PWD].u32Addr;
2309 break;
2310 case E_CA_DEBUG_PORT_JTAG:
2311 u32Addr = _HAL_CA_OTP_Addr[U_OTP_EJTAG_PWD].u32Addr;
2312 break;
2313 case E_CA_DEBUG_PORT_SCAN:
2314 u32Addr = _HAL_CA_OTP_Addr[U_OTP_SCAN_PWD].u32Addr;
2315 break;
2316 default:
2317 return FALSE;
2318 }
2319 if(sizeof(pwd)>u32Size)
2320 {
2321 j = u32Size;
2322 }
2323 else
2324 {
2325 j=sizeof(pwd);
2326 }
2327
2328 for(i = 0; i < sizeof(pwd) && i < u32Size; i++)
2329 {
2330 p[i] = pu8Password[(j-1)-i]; // Array reverse, for user easy viewing
2331 }
2332
2333
2334 for(i = 0; i < 4; i++)
2335 {
2336 if(HAL_CA_OTP_Write(u32Addr,pwd[i]) == FALSE)
2337 {
2338 return FALSE;
2339 }
2340 u32Addr += 4;
2341 }
2342
2343 return TRUE;
2344 }
2345
HAL_CA_OTP_GetDebugPortPassword(CA_DEBUG_PORT eDebugPort,MS_U8 * pu8Password,MS_U32 u32Size)2346 MS_BOOL HAL_CA_OTP_GetDebugPortPassword(CA_DEBUG_PORT eDebugPort, MS_U8 *pu8Password, MS_U32 u32Size)
2347 {
2348 MS_U32 pwd[4] = {0};
2349 MS_U32 i, j, u32Addr;
2350 MS_U8 *p = (MS_U8 *)pwd;
2351
2352 switch(eDebugPort)
2353 {
2354 case E_CA_DEBUG_PORT_I2C:
2355 u32Addr = _HAL_CA_OTP_Addr[U_OTP_I2C_PWD].u32Addr;
2356 break;
2357 case E_CA_DEBUG_PORT_JTAG:
2358 u32Addr = _HAL_CA_OTP_Addr[U_OTP_EJTAG_PWD].u32Addr;
2359 break;
2360 case E_CA_DEBUG_PORT_SCAN:
2361 u32Addr = _HAL_CA_OTP_Addr[U_OTP_SCAN_PWD].u32Addr;
2362 break;
2363 default:
2364 return FALSE;
2365 }
2366 for(i = 0; i < 4; i++)
2367 {
2368 pwd[i] = HAL_CA_OTP_Read(u32Addr);
2369 u32Addr += 4;
2370 }
2371 if(sizeof(pwd)>u32Size)
2372 {
2373 j = u32Size;
2374 }
2375 else
2376 {
2377 j=sizeof(pwd);
2378 }
2379 for(i = 0; i < sizeof(pwd) &&i < u32Size; i++)
2380 {
2381 pu8Password[i] = p[(j-1)-i]; // Array reverse, for user easy viewing
2382 }
2383 return TRUE;
2384 }
HAL_CA_OTP_WriteReserved(const MS_U8 * pu8RData,MS_U32 u32Size)2385 MS_BOOL HAL_CA_OTP_WriteReserved(const MS_U8 *pu8RData, MS_U32 u32Size)
2386 {
2387 MS_U32 u32rdata[32] = {0};
2388 MS_U32 i, u32Addr;
2389 MS_U32 u32ReservedSize = 8 ;
2390 MS_U8 *p = (MS_U8 *)u32rdata;
2391
2392 for(i = 0; i < sizeof(u32rdata) && i < u32Size; i++)
2393 {
2394 p[i] = pu8RData[i];
2395 }
2396
2397 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CA_reserved0].u32Addr;
2398 for(i = 0; i <u32ReservedSize; i++)
2399 {
2400 if(HAL_CA_OTP_Write(u32Addr,u32rdata[i]) == FALSE)
2401 {
2402 return FALSE;
2403 }
2404 u32Addr += 4;
2405 }
2406
2407 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CA_reserved1].u32Addr;
2408 for(i = u32ReservedSize; i < (2*u32ReservedSize); i++)
2409 {
2410 if(HAL_CA_OTP_Write(u32Addr,u32rdata[i]) == FALSE)
2411 {
2412 return FALSE;
2413 }
2414 u32Addr += 4;
2415 }
2416 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CA_reserved2].u32Addr;
2417 for(i = (2*u32ReservedSize); i < (3*u32ReservedSize); i++)
2418 {
2419 if(HAL_CA_OTP_Write(u32Addr,u32rdata[i]) == FALSE)
2420 {
2421 return FALSE;
2422 }
2423 u32Addr += 4;
2424 }
2425 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CA_reserved3].u32Addr;
2426 for(i = (3*u32ReservedSize); i < (4*u32ReservedSize); i++)
2427 {
2428 if(HAL_CA_OTP_Write(u32Addr,u32rdata[i]) == FALSE)
2429 {
2430 return FALSE;
2431 }
2432 u32Addr += 4;
2433 }
2434 return TRUE;
2435 }
2436
HAL_CA_OTP_ReadReserved(MS_U8 * pu8RData,MS_U32 u32Size)2437 MS_BOOL HAL_CA_OTP_ReadReserved(MS_U8 *pu8RData, MS_U32 u32Size)
2438 {
2439 MS_U32 u32rdata[32] = {0};
2440 MS_U32 i, u32Addr;
2441 MS_U32 u32ReservedSize = 8 ;
2442 MS_U8 *p = (MS_U8 *)u32rdata;
2443
2444 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CA_reserved0].u32Addr;
2445 for(i = 0; i < u32ReservedSize; i++)
2446 {
2447 u32rdata[i] = HAL_CA_OTP_Read(u32Addr);
2448 u32Addr += 4;
2449 }
2450 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CA_reserved1].u32Addr;
2451 for(i = u32ReservedSize; i < (2*u32ReservedSize); i++)
2452 {
2453 u32rdata[i] = HAL_CA_OTP_Read(u32Addr);
2454 u32Addr += 4;
2455 }
2456 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CA_reserved2].u32Addr;
2457 for(i = (2*u32ReservedSize); i < (3*u32ReservedSize); i++)
2458 {
2459 u32rdata[i] = HAL_CA_OTP_Read(u32Addr);
2460 u32Addr += 4;
2461 }
2462 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CA_reserved3].u32Addr;
2463 for(i = (3*u32ReservedSize); i < (4*u32ReservedSize); i++)
2464 {
2465 u32rdata[i] = HAL_CA_OTP_Read(u32Addr);
2466 u32Addr += 4;
2467 }
2468
2469 for(i = 0; i < sizeof(u32rdata) && i < u32Size; i++)
2470 {
2471 pu8RData[i] = p[i];
2472 }
2473
2474 return TRUE;
2475 }
2476
HAL_CA_MaxReservedSize(void)2477 MS_U32 HAL_CA_MaxReservedSize(void)
2478 {
2479 return MAX_RESERVED_SIZE;
2480 }
2481