Searched refs:MIU3_REG_BASE (Results 1 – 14 of 14) sorted by relevance
95 #define MIU3_REG_BASE (0x62400UL) macro194 #define MIU3_PROTECT_EN (MIU3_REG_BASE + 0xD2)195 #define MIU3_PROTECT_DDR_SIZE (MIU3_REG_BASE + 0xD3)196 #define MIU3_PROTECT0_ID0 (MIU3_REG_BASE + 0x2E)197 #define MIU3_BW_REQUEST (MIU3_REG_BASE + 0x1A)198 #define MIU3_BW_RESULT (MIU3_REG_BASE + 0x1C)199 #define MIU3_PROTECT0_ID_ENABLE (MIU3_REG_BASE + 0x20)200 #define MIU3_PROTECT1_ID_ENABLE (MIU3_REG_BASE + 0x22)201 #define MIU3_PROTECT2_ID_ENABLE (MIU3_REG_BASE + 0x24)202 #define MIU3_PROTECT3_ID_ENABLE (MIU3_REG_BASE + 0x26)[all …]
1204 u32Reg = MIU3_REG_BASE; in HAL_MIU_Protect()1303 u32Reg = MIU3_REG_BASE; in HAL_MIU_GetProtectInfo()1921 u32RegAddr += MIU3_REG_BASE; in HAL_MIU_SetGroupPriority()1970 u32Reg += MIU3_REG_BASE; in HAL_MIU_SetHPriorityMask()
1163 u32Reg = MIU3_REG_BASE; in HAL_MIU_Protect()1262 u32Reg = MIU3_REG_BASE; in HAL_MIU_GetProtectInfo()1880 u32RegAddr += MIU3_REG_BASE; in HAL_MIU_SetGroupPriority()1929 u32Reg += MIU3_REG_BASE; in HAL_MIU_SetHPriorityMask()
120 #define MIU3_REG_BASE (0x62400UL) macro218 #define MIU3_PROTECT_EN (MIU3_REG_BASE+0xD2)219 #define MIU3_PROTECT_DDR_SIZE (MIU3_REG_BASE+0xD3)220 #define MIU3_PROTECT0_ID0 (MIU3_REG_BASE+0x2E)221 #define MIU3_BW_REQUEST (MIU3_REG_BASE+0x1A)222 #define MIU3_BW_RESULT (MIU3_REG_BASE+0x1C)223 #define MIU3_PROTECT0_ID_ENABLE (MIU3_REG_BASE+0x20)224 #define MIU3_PROTECT1_ID_ENABLE (MIU3_REG_BASE+0x22)225 #define MIU3_PROTECT2_ID_ENABLE (MIU3_REG_BASE+0x24)226 #define MIU3_PROTECT3_ID_ENABLE (MIU3_REG_BASE+0x26)[all …]
1229 u32Reg = MIU3_REG_BASE; in HAL_MIU_Protect()
120 #define MIU3_REG_BASE (0x62400UL) macro232 #define MIU3_PROTECT_EN (MIU3_REG_BASE+0xD2)233 #define MIU3_PROTECT_DDR_SIZE (MIU3_REG_BASE+0xD3)234 #define MIU3_PROTECT0_ID0 (MIU3_REG_BASE+0x2E)235 #define MIU3_BW_REQUEST (MIU3_REG_BASE+0x1A)236 #define MIU3_BW_RESULT (MIU3_REG_BASE+0x1C)237 #define MIU3_PROTECT0_ID_ENABLE (MIU3_REG_BASE+0x20)238 #define MIU3_PROTECT1_ID_ENABLE (MIU3_REG_BASE+0x22)239 #define MIU3_PROTECT2_ID_ENABLE (MIU3_REG_BASE+0x24)240 #define MIU3_PROTECT3_ID_ENABLE (MIU3_REG_BASE+0x26)[all …]
1312 u32Reg = MIU3_REG_BASE; in HAL_MIU_Protect()
1306 u32Reg = MIU3_REG_BASE; in HAL_MIU_Protect()
120 #define MIU3_REG_BASE (0x62400UL) macro239 #define MIU3_PROTECT_EN (MIU3_REG_BASE+0xD2)240 #define MIU3_PROTECT_DDR_SIZE (MIU3_REG_BASE+0xD3)241 #define MIU3_PROTECT0_ID0 (MIU3_REG_BASE+0x2E)242 #define MIU3_BW_REQUEST (MIU3_REG_BASE+0x1A)243 #define MIU3_BW_RESULT (MIU3_REG_BASE+0x1C)244 #define MIU3_PROTECT0_ID_ENABLE (MIU3_REG_BASE+0x20)245 #define MIU3_PROTECT1_ID_ENABLE (MIU3_REG_BASE+0x22)246 #define MIU3_PROTECT2_ID_ENABLE (MIU3_REG_BASE+0x24)247 #define MIU3_PROTECT3_ID_ENABLE (MIU3_REG_BASE+0x26)[all …]
1119 u32Reg = MIU3_REG_BASE; in HAL_MIU_Protect()