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Searched refs:FIQ_STR2MI2_ADDR_MASK (Results 1 – 22 of 22) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dmx/hal/macan/fq/
H A DhalFQ.c164 FQ32_W(&(_REGFIQ[u32FQEng].str2mi_head), MIU_FQ(u32StartAddr) & FIQ_STR2MI2_ADDR_MASK); in HAL_FQ_PVR_SetBuf()
165 FQ32_W(&(_REGFIQ[u32FQEng].str2mi_tail), MIU_FQ(u32EndAddr) & FIQ_STR2MI2_ADDR_MASK); in HAL_FQ_PVR_SetBuf()
166 FQ32_W(&(_REGFIQ[u32FQEng].str2mi_mid), MIU_FQ(u32StartAddr) & FIQ_STR2MI2_ADDR_MASK); in HAL_FQ_PVR_SetBuf()
171 FQ32_W(&(_REGFIQ[u32FQEng].rush_addr), MIU_FQ(u32RushAddr) & FIQ_STR2MI2_ADDR_MASK); in HAL_FQ_PVR_SetRushAddr()
H A DregFQ.h139 #define FIQ_STR2MI2_ADDR_MASK 0x0FFFFFFF macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/manhattan/fq/
H A DhalFQ.c167 FQ32_W(&(_REGFIQ[u32FQEng].str2mi_head), MIU_FQ(u32StartAddr) & FIQ_STR2MI2_ADDR_MASK); in HAL_FQ_PVR_SetBuf()
168 FQ32_W(&(_REGFIQ[u32FQEng].str2mi_tail), MIU_FQ(u32EndAddr) & FIQ_STR2MI2_ADDR_MASK); in HAL_FQ_PVR_SetBuf()
169 FQ32_W(&(_REGFIQ[u32FQEng].str2mi_mid), MIU_FQ(u32StartAddr) & FIQ_STR2MI2_ADDR_MASK); in HAL_FQ_PVR_SetBuf()
174 FQ32_W(&(_REGFIQ[u32FQEng].rush_addr), MIU_FQ(u32RushAddr) & FIQ_STR2MI2_ADDR_MASK); in HAL_FQ_PVR_SetRushAddr()
H A DregFQ.h139 #define FIQ_STR2MI2_ADDR_MASK 0x0FFFFFFF macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/kano/fq/
H A DhalFQ.c154 FQ32_W(&(_REGFIQ[u32FQEng].str2mi_head), MIU_FQ(phyMiuOffsetFQBuf) & FIQ_STR2MI2_ADDR_MASK); in HAL_FQ_PVR_SetBuf()
155 FQ32_W(&(_REGFIQ[u32FQEng].str2mi_tail), MIU_FQ(u32EndAddr) & FIQ_STR2MI2_ADDR_MASK); in HAL_FQ_PVR_SetBuf()
156 FQ32_W(&(_REGFIQ[u32FQEng].str2mi_mid), MIU_FQ(phyMiuOffsetFQBuf) & FIQ_STR2MI2_ADDR_MASK); in HAL_FQ_PVR_SetBuf()
161 FQ32_W(&(_REGFIQ[u32FQEng].rush_addr), MIU_FQ(u32RushAddr) & FIQ_STR2MI2_ADDR_MASK); in HAL_FQ_PVR_SetRushAddr()
H A DregFQ.h139 #define FIQ_STR2MI2_ADDR_MASK 0x0FFFFFFFUL macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6lite/fq/
H A DhalFQ.c153 FQ32_W(&(_REGFIQ[u32FQEng].str2mi_head), MIU_FQ(phyMiuOffsetFQBuf) & FIQ_STR2MI2_ADDR_MASK); in HAL_FQ_PVR_SetBuf()
154 FQ32_W(&(_REGFIQ[u32FQEng].str2mi_tail), MIU_FQ(u32EndAddr) & FIQ_STR2MI2_ADDR_MASK); in HAL_FQ_PVR_SetBuf()
155 FQ32_W(&(_REGFIQ[u32FQEng].str2mi_mid), MIU_FQ(phyMiuOffsetFQBuf) & FIQ_STR2MI2_ADDR_MASK); in HAL_FQ_PVR_SetBuf()
160 FQ32_W(&(_REGFIQ[u32FQEng].rush_addr), MIU_FQ(u32RushAddr) & FIQ_STR2MI2_ADDR_MASK); in HAL_FQ_PVR_SetRushAddr()
H A DregFQ.h145 #define FIQ_STR2MI2_ADDR_MASK 0x0FFFFFFFUL macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6/fq/
H A DhalFQ.c153 FQ32_W(&(_REGFIQ[u32FQEng].str2mi_head), MIU_FQ(phyMiuOffsetFQBuf) & FIQ_STR2MI2_ADDR_MASK); in HAL_FQ_PVR_SetBuf()
154 FQ32_W(&(_REGFIQ[u32FQEng].str2mi_tail), MIU_FQ(u32EndAddr) & FIQ_STR2MI2_ADDR_MASK); in HAL_FQ_PVR_SetBuf()
155 FQ32_W(&(_REGFIQ[u32FQEng].str2mi_mid), MIU_FQ(phyMiuOffsetFQBuf) & FIQ_STR2MI2_ADDR_MASK); in HAL_FQ_PVR_SetBuf()
160 FQ32_W(&(_REGFIQ[u32FQEng].rush_addr), MIU_FQ(u32RushAddr) & FIQ_STR2MI2_ADDR_MASK); in HAL_FQ_PVR_SetRushAddr()
H A DregFQ.h139 #define FIQ_STR2MI2_ADDR_MASK 0x0FFFFFFFUL macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/curry/fq/
H A DhalFQ.c176 FQ32_W(&(_REGFIQ[u32FQEng].str2mi_head), MIU_FQ(u32StartAddr) & FIQ_STR2MI2_ADDR_MASK); in HAL_FQ_PVR_SetBuf()
177 FQ32_W(&(_REGFIQ[u32FQEng].str2mi_tail), MIU_FQ(u32EndAddr) & FIQ_STR2MI2_ADDR_MASK); in HAL_FQ_PVR_SetBuf()
178 FQ32_W(&(_REGFIQ[u32FQEng].str2mi_mid), MIU_FQ(u32StartAddr) & FIQ_STR2MI2_ADDR_MASK); in HAL_FQ_PVR_SetBuf()
183 FQ32_W(&(_REGFIQ[u32FQEng].rush_addr), MIU_FQ(u32RushAddr) & FIQ_STR2MI2_ADDR_MASK); in HAL_FQ_PVR_SetRushAddr()
H A DregFQ.h139 #define FIQ_STR2MI2_ADDR_MASK 0x0FFFFFFFUL macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7621/fq/
H A DhalFQ.c194 …g].str2mi_head), MIU_FQ((MS_U32)(phyStartAddr-_phyFQMiuOffset[u32FQEng])) & FIQ_STR2MI2_ADDR_MASK); in HAL_FQ_PVR_SetBuf()
195 …Eng].str2mi_tail), MIU_FQ((MS_U32)(phyEndAddr-_phyFQMiuOffset[u32FQEng])) & FIQ_STR2MI2_ADDR_MASK); in HAL_FQ_PVR_SetBuf()
196 …ng].str2mi_mid), MIU_FQ((MS_U32)(phyStartAddr-_phyFQMiuOffset[u32FQEng])) & FIQ_STR2MI2_ADDR_MASK); in HAL_FQ_PVR_SetBuf()
202 …QEng].rush_addr), MIU_FQ((MS_U32)(phyRushAddr-_phyFQMiuOffset[u32FQEng])) & FIQ_STR2MI2_ADDR_MASK); in HAL_FQ_PVR_SetRushAddr()
H A DregFQ.h141 #define FIQ_STR2MI2_ADDR_MASK 0x0FFFFFFF macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/maxim/fq/
H A DhalFQ.c194 …g].str2mi_head), MIU_FQ((MS_U32)(phyStartAddr-_phyFQMiuOffset[u32FQEng])) & FIQ_STR2MI2_ADDR_MASK); in HAL_FQ_PVR_SetBuf()
195 …Eng].str2mi_tail), MIU_FQ((MS_U32)(phyEndAddr-_phyFQMiuOffset[u32FQEng])) & FIQ_STR2MI2_ADDR_MASK); in HAL_FQ_PVR_SetBuf()
196 …ng].str2mi_mid), MIU_FQ((MS_U32)(phyStartAddr-_phyFQMiuOffset[u32FQEng])) & FIQ_STR2MI2_ADDR_MASK); in HAL_FQ_PVR_SetBuf()
202 …QEng].rush_addr), MIU_FQ((MS_U32)(phyRushAddr-_phyFQMiuOffset[u32FQEng])) & FIQ_STR2MI2_ADDR_MASK); in HAL_FQ_PVR_SetRushAddr()
H A DregFQ.h141 #define FIQ_STR2MI2_ADDR_MASK 0x0FFFFFFF macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7821/fq/
H A DhalFQ.c195 …g].str2mi_head), MIU_FQ((MS_U32)(phyStartAddr-_phyFQMiuOffset[u32FQEng])) & FIQ_STR2MI2_ADDR_MASK); in HAL_FQ_PVR_SetBuf()
196 …Eng].str2mi_tail), MIU_FQ((MS_U32)(phyEndAddr-_phyFQMiuOffset[u32FQEng])) & FIQ_STR2MI2_ADDR_MASK); in HAL_FQ_PVR_SetBuf()
197 …ng].str2mi_mid), MIU_FQ((MS_U32)(phyStartAddr-_phyFQMiuOffset[u32FQEng])) & FIQ_STR2MI2_ADDR_MASK); in HAL_FQ_PVR_SetBuf()
203 …QEng].rush_addr), MIU_FQ((MS_U32)(phyRushAddr-_phyFQMiuOffset[u32FQEng])) & FIQ_STR2MI2_ADDR_MASK); in HAL_FQ_PVR_SetRushAddr()
H A DregFQ.h141 #define FIQ_STR2MI2_ADDR_MASK 0x0FFFFFFF macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/maserati/fq/
H A DhalFQ.c195 …g].str2mi_head), MIU_FQ((MS_U32)(phyStartAddr-_phyFQMiuOffset[u32FQEng])) & FIQ_STR2MI2_ADDR_MASK); in HAL_FQ_PVR_SetBuf()
196 …Eng].str2mi_tail), MIU_FQ((MS_U32)(phyEndAddr-_phyFQMiuOffset[u32FQEng])) & FIQ_STR2MI2_ADDR_MASK); in HAL_FQ_PVR_SetBuf()
197 …ng].str2mi_mid), MIU_FQ((MS_U32)(phyStartAddr-_phyFQMiuOffset[u32FQEng])) & FIQ_STR2MI2_ADDR_MASK); in HAL_FQ_PVR_SetBuf()
203 …QEng].rush_addr), MIU_FQ((MS_U32)(phyRushAddr-_phyFQMiuOffset[u32FQEng])) & FIQ_STR2MI2_ADDR_MASK); in HAL_FQ_PVR_SetRushAddr()
H A DregFQ.h141 #define FIQ_STR2MI2_ADDR_MASK 0x0FFFFFFF macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/k7u/fq/
H A DhalFQ.c153 FQ32_W(&(_REGFIQ[u32FQEng].str2mi_head), MIU_FQ(phyMiuOffsetFQBuf) & FIQ_STR2MI2_ADDR_MASK); in HAL_FQ_PVR_SetBuf()
154 FQ32_W(&(_REGFIQ[u32FQEng].str2mi_tail), MIU_FQ(u32EndAddr) & FIQ_STR2MI2_ADDR_MASK); in HAL_FQ_PVR_SetBuf()
155 FQ32_W(&(_REGFIQ[u32FQEng].str2mi_mid), MIU_FQ(phyMiuOffsetFQBuf) & FIQ_STR2MI2_ADDR_MASK); in HAL_FQ_PVR_SetBuf()
160 FQ32_W(&(_REGFIQ[u32FQEng].rush_addr), MIU_FQ(u32RushAddr) & FIQ_STR2MI2_ADDR_MASK); in HAL_FQ_PVR_SetRushAddr()
H A DregFQ.h148 #define FIQ_STR2MI2_ADDR_MASK 0x0FFFFFFFUL macro