1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. MStar shall retain any and all right, ownership and interest to MStar 17 // Software and any modification/derivatives thereof. 18 // No right, ownership, or interest to MStar Software and any 19 // modification/derivatives thereof is transferred to you under Terms. 20 // 21 // 2. You understand that MStar Software might include, incorporate or be 22 // supplied together with third party`s software and the use of MStar 23 // Software may require additional licenses from third parties. 24 // Therefore, you hereby agree it is your sole responsibility to separately 25 // obtain any and all third party right and license necessary for your use of 26 // such third party`s software. 27 // 28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as 29 // MStar`s confidential information and you agree to keep MStar`s 30 // confidential information in strictest confidence and not disclose to any 31 // third party. 32 // 33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any 34 // kind. Any warranties are hereby expressly disclaimed by MStar, including 35 // without limitation, any warranties of merchantability, non-infringement of 36 // intellectual property rights, fitness for a particular purpose, error free 37 // and in conformity with any international standard. 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If requested, MStar may from time to time provide technical supports or 49 // services in relation with MStar Software to you for your use of 50 // MStar Software in conjunction with your or your customer`s product 51 // ("Services"). 52 // You understand and agree that, except otherwise agreed by both parties in 53 // writing, Services are provided on an "AS IS" basis and the warranty 54 // disclaimer set forth in Section 4 above shall apply. 55 // 56 // 6. Nothing contained herein shall be construed as by implication, estoppels 57 // or otherwise: 58 // (a) conferring any license or right to use MStar name, trademark, service 59 // mark, symbol or any other identification; 60 // (b) obligating MStar or any of its affiliates to furnish any person, 61 // including without limitation, you and your customers, any assistance 62 // of any kind whatsoever, or any information; or 63 // (c) conferring any license or right under any intellectual property right. 64 // 65 // 7. These terms shall be governed by and construed in accordance with the laws 66 // of Taiwan, R.O.C., excluding its conflict of law rules. 67 // Any and all dispute arising out hereof or related hereto shall be finally 68 // settled by arbitration referred to the Chinese Arbitration Association, 69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration 70 // Rules of the Association by three (3) arbitrators appointed in accordance 71 // with the said Rules. 72 // The place of arbitration shall be in Taipei, Taiwan and the language shall 73 // be English. 74 // The arbitration award shall be final and binding to both parties. 75 // 76 //****************************************************************************** 77 //////////////////////////////////////////////////////////////////////////////////////////////////// 78 // 79 // File name: regFQ.h 80 // Description: FQ Register Definition 81 // 82 //////////////////////////////////////////////////////////////////////////////////////////////////// 83 84 #ifndef _FQ_REG_H_ 85 #define _FQ_REG_H_ 86 87 //-------------------------------------------------------------------------------------------------- 88 // Global Definition 89 //-------------------------------------------------------------------------------------------------- 90 91 //-------------------------------------------------------------------------------------------------- 92 // Compliation Option 93 //-------------------------------------------------------------------------------------------------- 94 95 //------------------------------------------------------------------------------------------------- 96 // Harware Capability 97 //------------------------------------------------------------------------------------------------- 98 99 //------------------------------------------------------------------------------------------------- 100 // Type and Structure 101 //------------------------------------------------------------------------------------------------- 102 // Software 103 104 // Bank addr: 0x3004 ~ 0x3007 (FIQ 0~7) 105 // Bank addr: 0x3008 ~ 0x3009 (FIQ_Mux 0~2) 106 #define FQ_REG_CTRL_BASE (0x200400UL * 2) 107 108 typedef struct _REG32_FQ 109 { 110 volatile MS_U16 L; 111 volatile MS_U16 empty_L; 112 volatile MS_U16 H; 113 volatile MS_U16 empty_H; 114 } REG32_FQ; 115 116 typedef struct _REG16_FQ 117 { 118 volatile MS_U16 data; 119 volatile MS_U16 _resv; 120 } REG16_FQ; 121 122 typedef struct _REG_FIQ 123 { 124 REG16_FQ Reg_fiq_config0; //0x00 125 #define FIQ_CFG0_SW_RSTZ 0x0001 //sw_rstz 126 #define FIQ_CFG0_PVR_ENABLE 0x0002 //stream2miu_en 127 #define FIQ_CFG0_RESET_WR_PTR 0x0004 //str2miu_rst_wadr 128 #define FIQ_CFG0_PVR_PAUSE 0x0020 129 #define FIQ_CFG0_LOAD_WR_PTR 0x0040 //strm2mi2_wp_ld 130 #define FIQ_CFG0_MIU_HIGH_PRI 0x0080 131 #define FIQ_CFG0_FORCE_SYNC_EN 0x0100 132 #define FIQ_CFG0_REC_AT_SYNC_DIS 0x0200 133 #define FIQ_CFG0_CLR_PVR_OVERFLOW 0x0400 134 #define FIQ_CFG0_FIQ2MI_R_PRT_HIGHT 0x0800 135 #define FIQ_CFG0_BURST_LEN_MASK 0x3000 136 #define FIQ_CFG0_BURST_LEN_SHIFT 12 137 #define FIQ_CFG0_BURST_LEN_8BYTE 0 138 #define FIQ_CFG0_BURST_LEN_4BYTE 1 139 #define FIQ_CFG0_BURST_LEN_1BYTE 3 140 #define FIQ_CFG0_RUSH_ENABLE 0x4000 //rush_en 141 #define FIQ_CFG0_ADDR_MODE 0x8000 //addr_mode 142 143 REG32_FQ str2mi_head; //0x01 144 REG32_FQ str2mi_tail; //0x03 145 REG32_FQ str2mi_mid; //0x05 146 REG32_FQ rush_addr; //0x07 147 REG32_FQ cur_pkt_start_wadr_offset; //0x09 148 #define FIQ_STR2MI2_ADDR_MASK 0x0FFFFFFFUL 149 150 REG16_FQ Reg_fiq_config1; //0x0b 151 //------------------------- no use , just for compatibility -------------------------// 152 #define FIQ_CFG11_SKIP_RUSH_DATA_PATH_NON 0x0000 153 #define FIQ_CFG11_SKIP_PCR_RUSH_DATA 0x0000 154 #define FIQ_CFG11_SKIP_PVR1_RUSH_DATA 0x0000 155 #define FIQ_CFG11_SKIP_PVR2_RUSH_DATA 0x0000 156 #define FIQ_CFG11_SKIP_PVR3_RUSH_DATA 0x0000 157 #define FIQ_CFG11_SKIP_PVR4_RUSH_DATA 0x0000 158 //-----------------------------------------------------------------------------------// 159 #define FIQ_CFGB_FIQ_BYPASS 0x0001 //FIQ_bypass 160 #define FIQ_CFGB_BURST_LEVEL_MASK 0x0006 161 #define FIQ_CFGB_BURST_LEVEL_SHIFT 1 162 #define FIG_CFGB_REG_FIQ_INPUT_SAME_T 0x0008 163 #define FIG_CFGB_REG_ECO_TS_SYNC_OUT_REVERSE_BLOCK 0x0010 164 #define FIG_CFGB_REG_BYPASS_FILEIN_TO_FIQ 0x0020 165 #define FIG_CFGB_READ_BURST_LEN_MASK 0x00C0 166 #define FIG_CFGB_READ_BURST_LEN_SHIFT 6 167 #define FIQ_CFGB_READ_BURST_LEN_12BYTE 0 168 #define FIQ_CFGB_READ_BURST_LEN_8BYTE 1 // not support 169 #define FIQ_CFGB_READ_BURST_LEN_4BYTE 2 170 #define FIQ_CFGB_READ_BURST_LEN_1BYTE 3 // not support 171 #define FIG_CFGB_REG_FIQ_MUX_SRC_MASK 0x0F00 //FIQ_Mux only 172 #define FIG_CFGB_REG_FIQ_MUX_SRC_SHIFT 8 // 173 #define FIQ_CFGB_LPCR1_WLD 0x2000 174 #define FIQ_CFGB_LPCR1_LOAD 0x4000 175 #define FIQ_CFGB_FIQ_SEC_SEL 0x8000 176 177 REG32_FQ pkt_addr_offset; //0x0c 178 REG16_FQ Reg_fig_config2; //0x0e 179 #define FIQ_CFGE_C90K_SEL_90K 0x0000 180 #define FIQ_CFGE_C90K_SEL_27M 0x0001 181 #define FIQ_CFGE_TIMESTAMP_SRC_SEL_MASK 0x0002 182 #define FIQ_CFGE_TIMESTAMP_SRC_SEL_SHIFT 1 183 #define FIQ_CFGE_TIMESTAMP_SRC_SEL_LPCR 0 184 #define FIQ_CFGE_TIMESTAMP_SRC_SEL_PKT_CONVERTER 1 185 #define FIQ_CFGE_REG_FIQ_BYPASS_FIFO 0x0004 186 #define FIQ_CFGE_REG_FIQ_AFIFO_FULL_CONFIG 0x0008 187 #define FIQ_CFGE_REG_RUSH_SKIP_PKT_BY_TIMESTAMP_START 0x0100 188 189 REG16_FQ Reg_fig_config3; //0x0f 190 #define FIQ_CFGF_STREAM2MI_RD 0x0001 // FIQ read enable 191 #define FIQ_CFGF_RUSH_MODE_EN 0x0002 // FIQ rush mode (enable output) 192 #define FIQ_CFGF_SRC_FILTER_EN 0x0004 // FIQ src filter enable 193 194 REG16_FQ Reg_fiq_int; //0x10 195 #define FIQ_CFG10_INT_ENABLE_MASK 0x00FF 196 #define FIQ_CFG10_INT_ENABLE_RUSH_DONE 0x0001 197 #define FIQ_CFG10_INT_ENABLE_PVR_MEET_BUF_TAIL 0x0002 198 #define FIQ_CFG10_INT_ENABLE_PVR_MEET_BUF_MID 0x0004 199 #define FIQ_CFG10_INT_STATUS_MASK 0xFF00 200 #define FIQ_CFG10_INT_STATUS_RUSH_DONE 0x0100 201 202 REG32_FQ str2mi2_wadr_r; //0x11 203 REG32_FQ Fiq2mi2_radr_r; //0x13 204 REG16_FQ Fiq_status; //0x15 205 REG32_FQ lpcr1; //0x16 206 207 REG32_FQ Fiq_Rush_Timestamp_Start; //0x18 208 209 REG16_FQ REG_FIQ_1A; //0x1A 210 #define FIQ_CFG1A_REG_ONEWAY_FIQ 0x0001 211 #define FIQ_CFG1A_REG_REST_FIQ_SRC_FLT 0x0002 212 #define FIQ_CFG1A_REG_REST_TOP 0x0004 213 #define FIQ_CFG1A_REG_MIU_HIGHPRI_THOLD_MASK 0x0018 214 #define FIQ_CFG1A_REG_MIU_HIGHPRI_THOLD_SHIFT 3 215 216 REG16_FQ REG1B_1D_RESERVED[0x1E - 0x1B]; //0x1B~0x1D 217 218 REG16_FQ REG_FIQ_1E; 219 #define FIQ_CFG1E_REG_CHECK_TIMEOUT_CNT_MASK 0x00FF 220 #define FIQ_CFG1E_REG_CHECK_TIMEOUT_CNT_SHIFT 0 221 222 REG16_FQ REG_FIQ_1F; //0x1F 223 #define FIQ_CFG1F_REG_CLK_GATING_TSP_FIQ 0x0001 224 #define FIQ_CFG1F_REG_CLK_GATING_MIU_FIQ 0x0002 225 #define FIQ_CFG1F_REG_CHECK_TIMEOUT_ENABLE_W 0x0004 226 #define FIQ_CFG1F_REG_CHECK_TIMEOUT_ENABLE_R 0x0008 227 228 REG16_FQ Fiq_Src_Filter[8]; //0x20~0x27 229 #define FIQ_SRC_FILTER_SYNC_BYTE_EVEN_MASK 0x00FF 230 #define FIQ_SRC_FILTER_SYNC_BYTE_EVEN_SHIFT 0 231 #define FIQ_SRC_FILTER_SYNC_BYTE_ODD_MASK 0xFF00 232 #define FIQ_SRC_FILTER_SYNC_BYTE_ODD_SHIFT 8 233 234 REG16_FQ REG_FIQ_28; //0x28 235 #define FIQ_CFG28_REG_FIQ_SRC_FILTER_EN 0x0001 // 0 ~ 15 236 237 REG16_FQ Fiq_Filter[4]; //0x29~0x2C 238 #define FIQ_FILTER_PID_MASK 0x1FFF 239 #define FIQ_FILTER_PID_SHIFT 0 240 #define FIQ_FILTER_EN 0x8000 241 242 REG16_FQ Fiq_Filter_SyncByte[2]; //0x2D~0x2E 243 #define FIQ_FILTER_SYNC_BYTE_EVEN_MASK 0x00FF 244 #define FIQ_FILTER_SYNC_BYTE_EVEN_SHIFT 0 245 #define FIQ_FILTER_SYNC_BYTE_ODD_MASK 0xFF00 246 #define FIQ_FILTER_SYNC_BYTE_ODD_SHIFT 8 247 248 REG16_FQ REG2F_3F_RESERVED[0x40 - 0x2F]; //0x2F~0x3F 249 250 } REG_FIQ; 251 252 #endif // _FQ_REG_H_ 253