xref: /utopia/UTPA2-700.0.x/modules/dmx/hal/maxim/fq/regFQ.h (revision 53ee8cc121a030b8d368113ac3e966b4705770ef)

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////////////////////////////////////////////////////////////////////////////////////////////////////
//
//  File name: regFQ.h
//  Description: FQ Register Definition
//
////////////////////////////////////////////////////////////////////////////////////////////////////

#ifndef _FQ_REG_H_
#define _FQ_REG_H_

//--------------------------------------------------------------------------------------------------
//  Global Definition
//--------------------------------------------------------------------------------------------------

//--------------------------------------------------------------------------------------------------
//  Compliation Option
//--------------------------------------------------------------------------------------------------

//-------------------------------------------------------------------------------------------------
//  Harware Capability
//-------------------------------------------------------------------------------------------------

//-------------------------------------------------------------------------------------------------
//  Type and Structure
//-------------------------------------------------------------------------------------------------
// Software
#define FQ_REG_CTRL_BASE           (0x60A80UL * 2UL)

typedef struct _REG32_FQ
{
    volatile MS_U16                 L;
    volatile MS_U16                 empty_L;
    volatile MS_U16                 H;
    volatile MS_U16                 empty_H;
} REG32_FQ;

typedef struct _REG16_FQ
{
    volatile MS_U16                 data;
    volatile MS_U16                 _resv;
} REG16_FQ;

typedef struct _REG_FIQ
{
    REG16_FQ        Reg_fiq_config0;                                //0x40
    #define FIQ_CFG0_SW_RSTZ                            0x0001      //sw_rstz
    #define FIQ_CFG0_PVR_ENABLE                         0x0002      //stream2miu_en
    #define FIQ_CFG0_RESET_WR_PTR                       0x0004      //str2miu_rst_wadr
    #define FIQ_CFG0_FIQ2MI_DSWAP                       0x0008
    #define FIQ_CFG0_FIQ2MI_BITORD_BIG                  0x0010
    #define FIQ_CFG0_PVR_PAUSE                          0x0020
    #define FIQ_CFG0_LOAD_WR_PTR                        0x0040      //strm2mi2_wp_ld
    #define FIQ_CFG0_MIU_HIGH_PRI                       0x0080
    #define FIQ_CFG0_FORCE_SYNC_EN                      0x0100
    #define FIQ_CFG0_REC_AT_SYNC_DIS                    0x0200
    #define FIQ_CFG0_CLR_PVR_OVERFLOW                   0x0400
    #define FIQ_CFG0_FIQ2MI_R_PRT_HIGHT                 0x0800
    #define FIQ_CFG0_BURST_LEN_MASK                     0x3000
        #define FIQ_CFG0_BURST_LEN_8BYTE                0x0000
        #define FIQ_CFG0_BURST_LEN_4BYTE                0x1000
        #define FIQ_CFG0_BURST_LEN_1BYTE                0x3000
    #define FIQ_CFG0_RUSH_ENABLE                        0x4000      //rush_en
    #define FIQ_CFG0_ADDR_MODE                          0x8000      //addr_mode

    #define FIQ_STR2MI2_ADDR_MASK                       0x0FFFFFFF
    REG32_FQ        str2mi_head;                                    //0x41
    REG32_FQ        str2mi_tail;                                    //0x43
    REG32_FQ        str2mi_mid;                                     //0x45
    REG32_FQ        rush_addr;                                      //0x47
    REG32_FQ        cur_pkt_start_wadr_offset;                      //0x49

    REG16_FQ        Reg_fiq_config11;                               //0x4b
    #define FIQ_CFG11_FIQ_BYPASS                        0x0001      //FIQ_bypass
    #define FIQ_CFG11_BURST_LEVEL_MASK                  0x0006
    #define FIQ_CFG11_BURST_LEVEL_25                    0x0000
    #define FIQ_CFG11_BURST_LEVEL_50                    0x0002
    #define FIQ_CFG11_BURST_LEVEL_75                    0x0004
    #define FIQ_CFG11_BURST_LEVEL_100                   0x0006
    #define FIQ_CFG11_SKIP_RUSH_DATA_PATH_MASK          0x13F8
    #define FIQ_CFG11_SKIP_RUSH_DATA_PATH_NON           0x0000
    #define FIQ_CFG11_SKIP_APES_RUSH_DATA               0x0008      //skip_apes_rush_data
    #define FIQ_CFG11_SKIP_APES_B_RUSH_DATA             0x0010      //skip_apes_b_rush_data
    #define FIQ_CFG11_SKIP_VPES_RUSH_DATA               0x0020      //skip_vpes_rush_data
    #define FIQ_CFG11_SKIP_SEC_RUSH_DATA                0x0040      //skip_sec_rush_data
    #define FIQ_CFG11_SKIP_ADP_RUSH_DATA                0x0080      //skip_adp_rush_data
    #define FIQ_CFG11_SKIP_PCR_RUSH_DATA                0x0100      //skip_pcr_rush_data
    #define FIQ_CFG11_SKIP_RASP_RUSH_DATA               0x0000
    #define FIQ_CFG11_SKIP_PVR1_RUSH_DATA               0x0200      //skip_PVR1_rush_data
    #define FIQ_CFG11_LPCR1_WLD                         0x0400
    #define FIQ_CFG11_LPCR1_LOAD                        0x0800
    #define FIQ_CFG11_SKIP_PCR1_RUSH_DATA               0x1000
    #define FIQ_CFG11_TIMESTAMP_SRC_SEL                 0x2000
    #define FIQ_CFG11_C27M_EN_FIQ                       0x4000

    #define FIQ_CFG11_SKIP_RUSH_DATA_PATH1_MASK         0x0238
    #define FIQ_CFG11_SKIP_RUSH_DATA_PATH1_NON          0x0000
    #define FIQ_CFG11_SKIP_APES_C_RUSH_DATA             0x0008
    #define FIQ_CFG11_SKIP_APES_D_RUSH_DATA             0x0010
    #define FIQ_CFG11_SKIP_V3DPES_RUSH_DATA             0x0020
    #define FIQ_CFG11_SKIP_PVR2_RUSH_DATA               0x0200
    #define FIQ_CFG11_SKIP_PVR3_RUSH_DATA               0x0000

    REG32_FQ        pkt_addr_offset;                                //0x4c
    REG16_FQ        REG_FIQ0_CFG2;                                  //0x4e
    REG16_FQ        REG_FIQ0_CFG3;                                  //0x4f

    REG16_FQ        Reg_fiq_config16;                               //0x50
    #define FIQ_CFG16_INT_ENABLE_MASK                   0x00FF
    #define FIQ_CFG16_INT_ENABLE_RUSH_DONE              0x0001
    #define FIQ_CFG16_INT_ENABLE_PVR_MEET_BUFTAIL       0x0002
    #define FIQ_CFG16_INT_ENABLE_PVR_MEET_BUFMID        0x0004
    #define FIQ_CFG16_INT_STATUS_MASK                   0xFF00
    #define FIQ_CFG16_INT_STATUS_RUSH_DONE              0x0100

    REG32_FQ        str2mi2_wadr_r;                                 //0x51
    REG32_FQ        Fiq2mi2_radr_r;                                 //0x53
    REG16_FQ        Fiq_status;                                     //0x55
    #define FIQ_STATUS_PVRFIFO_EMPTY                    0x0001
    #define FIQ_STATUS_PVRFIFO_FULL                     0x0002
    #define FIQ_STATUS_PVRFIFO_WLEVEL_MASK              0x000C
    #define FIQ_STATUS_PVRFIFO_EVEN_OVF                 0x0010
    REG32_FQ        lpcr1;                                          //0x56

    REG32_FQ        REG18_1F_RESERVED[4];                           //0x58~0x5F

}REG_FIQ;


#endif // _FQ_REG_H_