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Searched refs:FIQ_CFG0_ADDR_MODE (Results 1 – 22 of 22) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dmx/hal/macan/fq/
H A DhalFQ.c223 …].Reg_fiq_config0), _SET_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config0)), FIQ_CFG0_ADDR_MODE)); in HAL_FQ_AddrMode()
227 …].Reg_fiq_config0), _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config0)), FIQ_CFG0_ADDR_MODE)); in HAL_FQ_AddrMode()
H A DregFQ.h137 #define FIQ_CFG0_ADDR_MODE 0x8000 //addr_mode macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/manhattan/fq/
H A DhalFQ.c226 …].Reg_fiq_config0), _SET_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config0)), FIQ_CFG0_ADDR_MODE)); in HAL_FQ_AddrMode()
230 …].Reg_fiq_config0), _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config0)), FIQ_CFG0_ADDR_MODE)); in HAL_FQ_AddrMode()
H A DregFQ.h137 #define FIQ_CFG0_ADDR_MODE 0x8000 //addr_mode macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/kano/fq/
H A DhalFQ.c213 …].Reg_fiq_config0), _SET_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config0)), FIQ_CFG0_ADDR_MODE)); in HAL_FQ_AddrMode()
217 …].Reg_fiq_config0), _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config0)), FIQ_CFG0_ADDR_MODE)); in HAL_FQ_AddrMode()
H A DregFQ.h137 #define FIQ_CFG0_ADDR_MODE 0x8000 //addr_mode macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6lite/fq/
H A DhalFQ.c212 …].Reg_fiq_config0), _SET_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config0)), FIQ_CFG0_ADDR_MODE)); in HAL_FQ_AddrMode()
216 …].Reg_fiq_config0), _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config0)), FIQ_CFG0_ADDR_MODE)); in HAL_FQ_AddrMode()
H A DregFQ.h137 #define FIQ_CFG0_ADDR_MODE 0x8000 //addr_mode macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6/fq/
H A DhalFQ.c212 …].Reg_fiq_config0), _SET_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config0)), FIQ_CFG0_ADDR_MODE)); in HAL_FQ_AddrMode()
216 …].Reg_fiq_config0), _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config0)), FIQ_CFG0_ADDR_MODE)); in HAL_FQ_AddrMode()
H A DregFQ.h137 #define FIQ_CFG0_ADDR_MODE 0x8000 //addr_mode macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/curry/fq/
H A DhalFQ.c235 …].Reg_fiq_config0), _SET_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config0)), FIQ_CFG0_ADDR_MODE)); in HAL_FQ_AddrMode()
239 …].Reg_fiq_config0), _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config0)), FIQ_CFG0_ADDR_MODE)); in HAL_FQ_AddrMode()
H A DregFQ.h137 #define FIQ_CFG0_ADDR_MODE 0x8000 //addr_mode macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7621/fq/
H A DhalFQ.c266 …].Reg_fiq_config0), _SET_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config0)), FIQ_CFG0_ADDR_MODE)); in HAL_FQ_AddrMode()
270 …].Reg_fiq_config0), _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config0)), FIQ_CFG0_ADDR_MODE)); in HAL_FQ_AddrMode()
H A DregFQ.h139 #define FIQ_CFG0_ADDR_MODE 0x8000 //addr_mode macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/maxim/fq/
H A DhalFQ.c266 …].Reg_fiq_config0), _SET_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config0)), FIQ_CFG0_ADDR_MODE)); in HAL_FQ_AddrMode()
270 …].Reg_fiq_config0), _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config0)), FIQ_CFG0_ADDR_MODE)); in HAL_FQ_AddrMode()
H A DregFQ.h139 #define FIQ_CFG0_ADDR_MODE 0x8000 //addr_mode macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7821/fq/
H A DhalFQ.c267 …].Reg_fiq_config0), _SET_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config0)), FIQ_CFG0_ADDR_MODE)); in HAL_FQ_AddrMode()
271 …].Reg_fiq_config0), _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config0)), FIQ_CFG0_ADDR_MODE)); in HAL_FQ_AddrMode()
H A DregFQ.h139 #define FIQ_CFG0_ADDR_MODE 0x8000 //addr_mode macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/maserati/fq/
H A DhalFQ.c267 …].Reg_fiq_config0), _SET_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config0)), FIQ_CFG0_ADDR_MODE)); in HAL_FQ_AddrMode()
271 …].Reg_fiq_config0), _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config0)), FIQ_CFG0_ADDR_MODE)); in HAL_FQ_AddrMode()
H A DregFQ.h139 #define FIQ_CFG0_ADDR_MODE 0x8000 //addr_mode macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/k7u/fq/
H A DhalFQ.c252 …].Reg_fiq_config0), _SET_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config0)), FIQ_CFG0_ADDR_MODE)); in HAL_FQ_AddrMode()
256 …].Reg_fiq_config0), _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config0)), FIQ_CFG0_ADDR_MODE)); in HAL_FQ_AddrMode()
H A DregFQ.h141 #define FIQ_CFG0_ADDR_MODE 0x8000 //addr_mode macro