| /utopia/UTPA2-700.0.x/modules/hdmi/hal/curry/hdcp/ |
| H A D | halHDCP.c | 590 …MHalHdcpRegMaskWrite(DEF_HDMITX_PHY_REG_BANK, REG_HDMITX_PHY_39_L, 0xFFFF, u32SetStatus? 0xF000: 0… in MHal_HDCP_HDCPTxHDMIStatus() 591 …MHalHdcpRegMaskWrite(DEF_HDMITX_PHY_REG_BANK, REG_HDMITX_PHY_2E_L, 0xE800, u32SetStatus? 0xE800: 0… in MHal_HDCP_HDCPTxHDMIStatus() 595 if((MHalHdcpRegRead(DEF_HDMITX_PHY_REG_BANK, REG_HDMITX_PHY_2E_L) &0xE800) == 0xE800) in MHal_HDCP_HDCPTxHDMIStatus()
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| H A D | regHDCP.h | 109 #define DEF_HDMITX_PHY_REG_BANK 0x073000U // 0x173000U macro
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/k6/hdcp/ |
| H A D | halHDCP.c | 574 …MHalHdcpRegMaskWrite(DEF_HDMITX_PHY_REG_BANK, REG_HDMITX_PHY_39_L, 0xFFFF, u32SetStatus? 0xF000: 0… in MHal_HDCP_HDCPTxHDMIStatus() 575 …MHalHdcpRegMaskWrite(DEF_HDMITX_PHY_REG_BANK, REG_HDMITX_PHY_2E_L, 0xE800, u32SetStatus? 0xE800: 0… in MHal_HDCP_HDCPTxHDMIStatus() 579 if((MHalHdcpRegRead(DEF_HDMITX_PHY_REG_BANK, REG_HDMITX_PHY_2E_L) &0xE800) == 0xE800) in MHal_HDCP_HDCPTxHDMIStatus()
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| H A D | regHDCP.h | 109 #define DEF_HDMITX_PHY_REG_BANK 0x073000U // 0x173000U macro
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/k6lite/hdcp/ |
| H A D | halHDCP.c | 623 …MHalHdcpRegMaskWrite(DEF_HDMITX_PHY_REG_BANK, REG_HDMITX_PHY_39_L, 0xFFFF, u32SetStatus? 0xF000: 0… in MHal_HDCP_HDCPTxHDMIStatus() 624 …MHalHdcpRegMaskWrite(DEF_HDMITX_PHY_REG_BANK, REG_HDMITX_PHY_2E_L, 0xE800, u32SetStatus? 0xE800: 0… in MHal_HDCP_HDCPTxHDMIStatus() 628 if((MHalHdcpRegRead(DEF_HDMITX_PHY_REG_BANK, REG_HDMITX_PHY_2E_L) &0xE800) == 0xE800) in MHal_HDCP_HDCPTxHDMIStatus()
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| H A D | regHDCP.h | 109 #define DEF_HDMITX_PHY_REG_BANK 0x073000U macro
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/M7621/hdcp/ |
| H A D | halHDCP.c | 625 …MHalHdcpRegMaskWrite(DEF_HDMITX_PHY_REG_BANK, REG_HDMITX_PHY_39_L, 0xFFFF, u32SetStatus? 0xF000: 0… in MHal_HDCP_HDCPTxHDMIStatus() 626 …MHalHdcpRegMaskWrite(DEF_HDMITX_PHY_REG_BANK, REG_HDMITX_PHY_2E_L, 0xE800, u32SetStatus? 0xE800: 0… in MHal_HDCP_HDCPTxHDMIStatus() 630 if((MHalHdcpRegRead(DEF_HDMITX_PHY_REG_BANK, REG_HDMITX_PHY_2E_L) &0xE800) == 0xE800) in MHal_HDCP_HDCPTxHDMIStatus()
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| H A D | regHDCP.h | 109 #define DEF_HDMITX_PHY_REG_BANK 0x072600U // 0x172600U macro
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/maxim/hdcp/ |
| H A D | halHDCP.c | 687 …MHalHdcpRegMaskWrite(DEF_HDMITX_PHY_REG_BANK, REG_HDMITX_PHY_39_L, 0xFFFF, u32SetStatus? 0xF000: 0… in MHal_HDCP_HDCPTxHDMIStatus() 688 …MHalHdcpRegMaskWrite(DEF_HDMITX_PHY_REG_BANK, REG_HDMITX_PHY_2E_L, 0xE800, u32SetStatus? 0xE800: 0… in MHal_HDCP_HDCPTxHDMIStatus() 692 if((MHalHdcpRegRead(DEF_HDMITX_PHY_REG_BANK, REG_HDMITX_PHY_2E_L) &0xE800) == 0xE800) in MHal_HDCP_HDCPTxHDMIStatus()
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| H A D | regHDCP.h | 109 #define DEF_HDMITX_PHY_REG_BANK 0x072600U // 0x172600U macro
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/kano/hdcp/ |
| H A D | halHDCP.c | 694 …MHalHdcpRegMaskWrite(DEF_HDMITX_PHY_REG_BANK, REG_HDMITX_PHY_39_L, 0xFFFF, u32SetStatus? 0xF000: 0… in MHal_HDCP_HDCPTxHDMIStatus() 695 …MHalHdcpRegMaskWrite(DEF_HDMITX_PHY_REG_BANK, REG_HDMITX_PHY_2E_L, 0xE800, u32SetStatus? 0xE800: 0… in MHal_HDCP_HDCPTxHDMIStatus() 699 if((MHalHdcpRegRead(DEF_HDMITX_PHY_REG_BANK, REG_HDMITX_PHY_2E_L) &0xE800) == 0xE800) in MHal_HDCP_HDCPTxHDMIStatus()
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| H A D | regHDCP.h | 109 #define DEF_HDMITX_PHY_REG_BANK 0x073000U // 0x173000U macro
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/mooney/hdcp/ |
| H A D | regHDCP.h | 109 #define DEF_HDMITX_PHY_REG_BANK 0x073000U // 0x173000U macro
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/mainz/hdcp/ |
| H A D | regHDCP.h | 109 #define DEF_HDMITX_PHY_REG_BANK 0x000000U macro
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/M7821/hdcp/ |
| H A D | regHDCP.h | 109 #define DEF_HDMITX_PHY_REG_BANK 0x000000U macro
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/manhattan/hdcp/ |
| H A D | regHDCP.h | 109 #define DEF_HDMITX_PHY_REG_BANK 0x000000U macro
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/messi/hdcp/ |
| H A D | regHDCP.h | 109 #define DEF_HDMITX_PHY_REG_BANK 0x000000U macro
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/maserati/hdcp/ |
| H A D | regHDCP.h | 109 #define DEF_HDMITX_PHY_REG_BANK 0x000000U macro
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