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Searched refs:DEF_HDCP22_TX_REG_BANK (Results 1 – 19 of 19) sorted by relevance

/utopia/UTPA2-700.0.x/modules/hdmi/hal/curry/hdcp/
H A DhalHDCP.c472 …MHalHdcpRegMaskWrite(DEF_HDCP22_TX_REG_BANK + u16BKOffset, 0x0000, 0x11, bEnable ? 0x11 : 0x00); /… in MHal_HDCP_HDCP2TxInit()
475 … MHalHdcpRegMaskWrite(DEF_HDCP22_TX_REG_BANK + u16BKOffset, 0x0000, 0x02, 0x02); //reset hdcp22 FSM in MHal_HDCP_HDCP2TxInit()
476 MHalHdcpRegMaskWrite(DEF_HDCP22_TX_REG_BANK + u16BKOffset, 0x0000, 0x02, 0x00); in MHal_HDCP_HDCP2TxInit()
484 …MHalHdcpRegMaskWrite(DEF_HDCP22_TX_REG_BANK + u16BKOffset, 0x0000, 0x04, bEnable ? 0x04 : 0x00); /… in MHal_HDCP_HDCP2TxEnableEncrypt()
485 …MHalHdcpRegMaskWrite(DEF_HDCP22_TX_REG_BANK + u16BKOffset, 0x0000, 0x08, bEnable ? 0x08 : 0x00); /… in MHal_HDCP_HDCP2TxEnableEncrypt()
513 *pu8State = MHalHdcpRegRead(DEF_HDCP22_TX_REG_BANK + u16BKOffset, 0x00) & 0x0C; in MHal_HDCP_HDCP2TxGetCipherState()
520 …MHalHdcpRegMaskWrite(DEF_HDCP22_TX_REG_BANK + u16BKOffset, 0x0000, 0x04, bEnable ? 0x04 : 0x00); /… in MHal_HDCP_HDCP2TxSetAuthPass()
572 …MHalHdcpRegMaskWrite(DEF_HDCP22_TX_REG_BANK, REG_HDCP22_TX_00_L, BIT(3), u32SetStatus? BIT(3): 0);… in MHal_HDCP_HDCP2TxEncrytionStatus()
576 if(MHalHdcpRegRead(DEF_HDCP22_TX_REG_BANK, REG_HDCP22_TX_00_L) &BIT(3)) in MHal_HDCP_HDCP2TxEncrytionStatus()
H A DregHDCP.h108 #define DEF_HDCP22_TX_REG_BANK 0x072F00U // 0x172F00U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/k6lite/hdcp/
H A DhalHDCP.c472 …MHalHdcpRegMaskWrite(DEF_HDCP22_TX_REG_BANK + u16BKOffset, 0x0000, 0x11, bEnable ? 0x11 : 0x00); /… in MHal_HDCP_HDCP2TxInit()
475 … MHalHdcpRegMaskWrite(DEF_HDCP22_TX_REG_BANK + u16BKOffset, 0x0000, 0x02, 0x02); //reset hdcp22 FSM in MHal_HDCP_HDCP2TxInit()
476 MHalHdcpRegMaskWrite(DEF_HDCP22_TX_REG_BANK + u16BKOffset, 0x0000, 0x02, 0x00); in MHal_HDCP_HDCP2TxInit()
484 …MHalHdcpRegMaskWrite(DEF_HDCP22_TX_REG_BANK + u16BKOffset, 0x0000, 0x04, bEnable ? 0x04 : 0x00); /… in MHal_HDCP_HDCP2TxEnableEncrypt()
485 …MHalHdcpRegMaskWrite(DEF_HDCP22_TX_REG_BANK + u16BKOffset, 0x0000, 0x08, bEnable ? 0x08 : 0x00); /… in MHal_HDCP_HDCP2TxEnableEncrypt()
511 *pu8State = MHalHdcpRegRead(DEF_HDCP22_TX_REG_BANK + u16BKOffset, 0x00) & 0x0C; in MHal_HDCP_HDCP2TxGetCipherState()
518 …MHalHdcpRegMaskWrite(DEF_HDCP22_TX_REG_BANK + u16BKOffset, 0x0000, 0x04, bEnable ? 0x04 : 0x00); /… in MHal_HDCP_HDCP2TxSetAuthPass()
605 …MHalHdcpRegMaskWrite(DEF_HDCP22_TX_REG_BANK, REG_HDCP22_TX_00_L, BIT(3), u32SetStatus? BIT(3): 0);… in MHal_HDCP_HDCP2TxEncrytionStatus()
609 if(MHalHdcpRegRead(DEF_HDCP22_TX_REG_BANK, REG_HDCP22_TX_00_L) &BIT(3)) in MHal_HDCP_HDCP2TxEncrytionStatus()
H A DregHDCP.h108 #define DEF_HDCP22_TX_REG_BANK 0x072F00U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7621/hdcp/
H A DhalHDCP.c469 …MHalHdcpRegMaskWrite(DEF_HDCP22_TX_REG_BANK + u16BKOffset, 0x0000, 0x11, bEnable ? 0x11 : 0x00); /… in MHal_HDCP_HDCP2TxInit()
472 … MHalHdcpRegMaskWrite(DEF_HDCP22_TX_REG_BANK + u16BKOffset, 0x0000, 0x02, 0x02); //reset hdcp22 FSM in MHal_HDCP_HDCP2TxInit()
473 MHalHdcpRegMaskWrite(DEF_HDCP22_TX_REG_BANK + u16BKOffset, 0x0000, 0x02, 0x00); in MHal_HDCP_HDCP2TxInit()
481 …MHalHdcpRegMaskWrite(DEF_HDCP22_TX_REG_BANK + u16BKOffset, 0x0000, 0x04, bEnable ? 0x04 : 0x00); /… in MHal_HDCP_HDCP2TxEnableEncrypt()
482 …MHalHdcpRegMaskWrite(DEF_HDCP22_TX_REG_BANK + u16BKOffset, 0x0000, 0x08, bEnable ? 0x08 : 0x00); /… in MHal_HDCP_HDCP2TxEnableEncrypt()
507 *pu8State = MHalHdcpRegRead(DEF_HDCP22_TX_REG_BANK + u16BKOffset, 0x00) & 0x0C; in MHal_HDCP_HDCP2TxGetCipherState()
514 …MHalHdcpRegMaskWrite(DEF_HDCP22_TX_REG_BANK + u16BKOffset, 0x0000, 0x04, bEnable ? 0x04 : 0x00); /… in MHal_HDCP_HDCP2TxSetAuthPass()
607 …MHalHdcpRegMaskWrite(DEF_HDCP22_TX_REG_BANK, REG_HDCP22_TX_00_L, BIT(3), u32SetStatus? BIT(3): 0);… in MHal_HDCP_HDCP2TxEncrytionStatus()
611 if(MHalHdcpRegRead(DEF_HDCP22_TX_REG_BANK, REG_HDCP22_TX_00_L) &BIT(3)) in MHal_HDCP_HDCP2TxEncrytionStatus()
H A DregHDCP.h108 #define DEF_HDCP22_TX_REG_BANK 0x072500U // 0x172500U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maxim/hdcp/
H A DhalHDCP.c531 …MHalHdcpRegMaskWrite(DEF_HDCP22_TX_REG_BANK + u16BKOffset, 0x0000, 0x11, bEnable ? 0x11 : 0x00); /… in MHal_HDCP_HDCP2TxInit()
534 … MHalHdcpRegMaskWrite(DEF_HDCP22_TX_REG_BANK + u16BKOffset, 0x0000, 0x02, 0x02); //reset hdcp22 FSM in MHal_HDCP_HDCP2TxInit()
535 MHalHdcpRegMaskWrite(DEF_HDCP22_TX_REG_BANK + u16BKOffset, 0x0000, 0x02, 0x00); in MHal_HDCP_HDCP2TxInit()
543 …MHalHdcpRegMaskWrite(DEF_HDCP22_TX_REG_BANK + u16BKOffset, 0x0000, 0x04, bEnable ? 0x04 : 0x00); /… in MHal_HDCP_HDCP2TxEnableEncrypt()
544 …MHalHdcpRegMaskWrite(DEF_HDCP22_TX_REG_BANK + u16BKOffset, 0x0000, 0x08, bEnable ? 0x08 : 0x00); /… in MHal_HDCP_HDCP2TxEnableEncrypt()
569 *pu8State = MHalHdcpRegRead(DEF_HDCP22_TX_REG_BANK + u16BKOffset, 0x00) & 0x0C; in MHal_HDCP_HDCP2TxGetCipherState()
576 …MHalHdcpRegMaskWrite(DEF_HDCP22_TX_REG_BANK + u16BKOffset, 0x0000, 0x04, bEnable ? 0x04 : 0x00); /… in MHal_HDCP_HDCP2TxSetAuthPass()
669 …MHalHdcpRegMaskWrite(DEF_HDCP22_TX_REG_BANK, REG_HDCP22_TX_00_L, BIT(3), u32SetStatus? BIT(3): 0);… in MHal_HDCP_HDCP2TxEncrytionStatus()
673 if(MHalHdcpRegRead(DEF_HDCP22_TX_REG_BANK, REG_HDCP22_TX_00_L) &BIT(3)) in MHal_HDCP_HDCP2TxEncrytionStatus()
H A DregHDCP.h108 #define DEF_HDCP22_TX_REG_BANK 0x072500U // 0x172500U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/kano/hdcp/
H A DhalHDCP.c537 …MHalHdcpRegMaskWrite(DEF_HDCP22_TX_REG_BANK + u16BKOffset, 0x0000, 0x11, bEnable ? 0x11 : 0x00); /… in MHal_HDCP_HDCP2TxInit()
540 … MHalHdcpRegMaskWrite(DEF_HDCP22_TX_REG_BANK + u16BKOffset, 0x0000, 0x02, 0x02); //reset hdcp22 FSM in MHal_HDCP_HDCP2TxInit()
541 MHalHdcpRegMaskWrite(DEF_HDCP22_TX_REG_BANK + u16BKOffset, 0x0000, 0x02, 0x00); in MHal_HDCP_HDCP2TxInit()
549 …MHalHdcpRegMaskWrite(DEF_HDCP22_TX_REG_BANK + u16BKOffset, 0x0000, 0x04, bEnable ? 0x04 : 0x00); /… in MHal_HDCP_HDCP2TxEnableEncrypt()
550 …MHalHdcpRegMaskWrite(DEF_HDCP22_TX_REG_BANK + u16BKOffset, 0x0000, 0x08, bEnable ? 0x08 : 0x00); /… in MHal_HDCP_HDCP2TxEnableEncrypt()
578 *pu8State = MHalHdcpRegRead(DEF_HDCP22_TX_REG_BANK + u16BKOffset, 0x00) & 0x0C; in MHal_HDCP_HDCP2TxGetCipherState()
585 …MHalHdcpRegMaskWrite(DEF_HDCP22_TX_REG_BANK + u16BKOffset, 0x0000, 0x04, bEnable ? 0x04 : 0x00); /… in MHal_HDCP_HDCP2TxSetAuthPass()
676 …MHalHdcpRegMaskWrite(DEF_HDCP22_TX_REG_BANK, REG_HDCP22_TX_00_L, BIT(3), u32SetStatus? BIT(3): 0);… in MHal_HDCP_HDCP2TxEncrytionStatus()
680 if(MHalHdcpRegRead(DEF_HDCP22_TX_REG_BANK, REG_HDCP22_TX_00_L) &BIT(3)) in MHal_HDCP_HDCP2TxEncrytionStatus()
H A DregHDCP.h108 #define DEF_HDCP22_TX_REG_BANK 0x072F00U // 0x172F00U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/k6/hdcp/
H A DhalHDCP.c456 …MHalHdcpRegMaskWrite(DEF_HDCP22_TX_REG_BANK + u16BKOffset, 0x0000, 0x11, bEnable ? 0x11 : 0x00); /… in MHal_HDCP_HDCP2TxInit()
459 … MHalHdcpRegMaskWrite(DEF_HDCP22_TX_REG_BANK + u16BKOffset, 0x0000, 0x02, 0x02); //reset hdcp22 FSM in MHal_HDCP_HDCP2TxInit()
460 MHalHdcpRegMaskWrite(DEF_HDCP22_TX_REG_BANK + u16BKOffset, 0x0000, 0x02, 0x00); in MHal_HDCP_HDCP2TxInit()
468 …MHalHdcpRegMaskWrite(DEF_HDCP22_TX_REG_BANK + u16BKOffset, 0x0000, 0x04, bEnable ? 0x04 : 0x00); /… in MHal_HDCP_HDCP2TxEnableEncrypt()
469 …MHalHdcpRegMaskWrite(DEF_HDCP22_TX_REG_BANK + u16BKOffset, 0x0000, 0x08, bEnable ? 0x08 : 0x00); /… in MHal_HDCP_HDCP2TxEnableEncrypt()
497 *pu8State = MHalHdcpRegRead(DEF_HDCP22_TX_REG_BANK + u16BKOffset, 0x00) & 0x0C; in MHal_HDCP_HDCP2TxGetCipherState()
556 …MHalHdcpRegMaskWrite(DEF_HDCP22_TX_REG_BANK, REG_HDCP22_TX_00_L, BIT(3), u32SetStatus? BIT(3): 0);… in MHal_HDCP_HDCP2TxEncrytionStatus()
560 if(MHalHdcpRegRead(DEF_HDCP22_TX_REG_BANK, REG_HDCP22_TX_00_L) &BIT(3)) in MHal_HDCP_HDCP2TxEncrytionStatus()
H A DregHDCP.h108 #define DEF_HDCP22_TX_REG_BANK 0x072F00U // 0x172F00U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mooney/hdcp/
H A DregHDCP.h108 #define DEF_HDCP22_TX_REG_BANK 0x072F00U // 0x172F00U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mainz/hdcp/
H A DregHDCP.h108 #define DEF_HDCP22_TX_REG_BANK 0x000000U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7821/hdcp/
H A DregHDCP.h108 #define DEF_HDCP22_TX_REG_BANK 0x000000U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/manhattan/hdcp/
H A DregHDCP.h108 #define DEF_HDCP22_TX_REG_BANK 0x000000U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/messi/hdcp/
H A DregHDCP.h108 #define DEF_HDCP22_TX_REG_BANK 0x000000U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maserati/hdcp/
H A DregHDCP.h108 #define DEF_HDCP22_TX_REG_BANK 0x000000U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/macan/hdcp/
H A DhalHDCP.c156 #define DEF_HDCP22_TX_REG_BANK 0x072F00U //0x172F00U macro