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Searched refs:DEF_HDCP22_RX_REG_BANK (Results 1 – 24 of 24) sorted by relevance

/utopia/UTPA2-700.0.x/modules/hdmi/hal/mainz/hdcp/
H A DhalHDCP.c343 MHalHdcpRegMaskWrite(DEF_HDCP22_RX_REG_BANK + u16BKOffset, 0x4E, 0x0006, 0x0006); in MHal_HDCP_HDCP2RxInit()
361 MHalHdcpRegMaskWrite(DEF_HDCP22_RX_REG_BANK + u16BKOffset, 0x4E, 0x0001, 0x0001); in MHal_HDCP_HDCP2RxProcessCipher()
370 …MHalHdcpRegMaskWrite(DEF_HDCP22_RX_REG_BANK + u16BKOffset, 0x4E, 0x0001, bEnable ? 0x0001 : 0x0000… in MHal_HDCP_HDCP2RxSetSKEPass()
395 *pu8State = MHalHdcpRegRead(DEF_HDCP22_RX_REG_BANK + u16BKOffset, 0x4E) & 0x01; in MHal_HDCP_HDCP2RxGetCipherState()
H A DregHDCP.h116 #define DEF_HDCP22_RX_REG_BANK 0x071200U // 0x171200U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/messi/hdcp/
H A DhalHDCP.c343 MHalHdcpRegMaskWrite(DEF_HDCP22_RX_REG_BANK + u16BKOffset, 0x4E, 0x0006, 0x0006); in MHal_HDCP_HDCP2RxInit()
361 MHalHdcpRegMaskWrite(DEF_HDCP22_RX_REG_BANK + u16BKOffset, 0x4E, 0x0001, 0x0001); in MHal_HDCP_HDCP2RxProcessCipher()
370 …MHalHdcpRegMaskWrite(DEF_HDCP22_RX_REG_BANK + u16BKOffset, 0x4E, 0x0001, bEnable ? 0x0001 : 0x0000… in MHal_HDCP_HDCP2RxSetSKEPass()
395 *pu8State = MHalHdcpRegRead(DEF_HDCP22_RX_REG_BANK + u16BKOffset, 0x4E) & 0x01; in MHal_HDCP_HDCP2RxGetCipherState()
H A DregHDCP.h116 #define DEF_HDCP22_RX_REG_BANK 0x071200U // 0x171200U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/manhattan/hdcp/
H A DhalHDCP.c406 MHalHdcpRegMaskWrite(DEF_HDCP22_RX_REG_BANK + u16BKOffset, 0x4E, 0x0006, 0x0006); in MHal_HDCP_HDCP2RxInit()
427 MHalHdcpRegMaskWrite(DEF_HDCP22_RX_REG_BANK + u16BKOffset, 0x4E, 0x0001, 0x0001); in MHal_HDCP_HDCP2RxProcessCipher()
436 …MHalHdcpRegMaskWrite(DEF_HDCP22_RX_REG_BANK + u16BKOffset, 0x4E, 0x0001, bEnable ? 0x0001 : 0x0000… in MHal_HDCP_HDCP2RxSetSKEPass()
464 *pu8State = MHalHdcpRegRead(DEF_HDCP22_RX_REG_BANK + u16BKOffset, 0x4E) & 0x01; in MHal_HDCP_HDCP2RxGetCipherState()
H A DregHDCP.h116 #define DEF_HDCP22_RX_REG_BANK 0x071200U // 0x171200U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maserati/hdcp/
H A DhalHDCP.c406 MHalHdcpRegMaskWrite(DEF_HDCP22_RX_REG_BANK + u16BKOffset, 0x4E, 0x0006, 0x0006); in MHal_HDCP_HDCP2RxInit()
429 MHalHdcpRegMaskWrite(DEF_HDCP22_RX_REG_BANK + u16BKOffset, 0x4E, 0x0001, 0x0001); in MHal_HDCP_HDCP2RxProcessCipher()
438 …MHalHdcpRegMaskWrite(DEF_HDCP22_RX_REG_BANK + u16BKOffset, 0x4E, 0x0001, bEnable ? 0x0001 : 0x0000… in MHal_HDCP_HDCP2RxSetSKEPass()
466 *pu8State = MHalHdcpRegRead(DEF_HDCP22_RX_REG_BANK + u16BKOffset, 0x4E) & 0x01; in MHal_HDCP_HDCP2RxGetCipherState()
H A DregHDCP.h116 #define DEF_HDCP22_RX_REG_BANK 0x071200U // 0x171200U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7821/hdcp/
H A DhalHDCP.c406 …MHalHdcpRegMaskWrite(DEF_HDCP22_RX_REG_BANK + u16BKOffset, 0x4E, BIT(10)| 0x0006, BIT(10)| 0x0006); in MHal_HDCP_HDCP2RxInit()
429 MHalHdcpRegMaskWrite(DEF_HDCP22_RX_REG_BANK + u16BKOffset, 0x4E, 0x0001, 0x0001); in MHal_HDCP_HDCP2RxProcessCipher()
438 …MHalHdcpRegMaskWrite(DEF_HDCP22_RX_REG_BANK + u16BKOffset, 0x4E, 0x0001, bEnable ? 0x0001 : 0x0000… in MHal_HDCP_HDCP2RxSetSKEPass()
466 *pu8State = MHalHdcpRegRead(DEF_HDCP22_RX_REG_BANK + u16BKOffset, 0x4E) & 0x01; in MHal_HDCP_HDCP2RxGetCipherState()
H A DregHDCP.h116 #define DEF_HDCP22_RX_REG_BANK 0x071200U // 0x171200U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/k6lite/hdcp/
H A DhalHDCP.c526 MHalHdcpRegMaskWrite(DEF_HDCP22_RX_REG_BANK + u16BKOffset, 0x4E, 0x0006, 0x0006); in MHal_HDCP_HDCP2RxInit()
544 MHalHdcpRegMaskWrite(DEF_HDCP22_RX_REG_BANK + u16BKOffset, 0x4E, 0x0001, 0x0001); in MHal_HDCP_HDCP2RxProcessCipher()
553 …MHalHdcpRegMaskWrite(DEF_HDCP22_RX_REG_BANK + u16BKOffset, 0x4E, 0x0001, bEnable ? 0x0001 : 0x0000… in MHal_HDCP_HDCP2RxSetSKEPass()
578 *pu8State = MHalHdcpRegRead(DEF_HDCP22_RX_REG_BANK + u16BKOffset, 0x4E) & 0x01; in MHal_HDCP_HDCP2RxGetCipherState()
H A DregHDCP.h116 #define DEF_HDCP22_RX_REG_BANK 0x000000U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7621/hdcp/
H A DhalHDCP.c523 MHalHdcpRegMaskWrite(DEF_HDCP22_RX_REG_BANK + u16BKOffset, 0x4E, 0x0006, 0x0006); in MHal_HDCP_HDCP2RxInit()
546 MHalHdcpRegMaskWrite(DEF_HDCP22_RX_REG_BANK + u16BKOffset, 0x4E, 0x0001, 0x0001); in MHal_HDCP_HDCP2RxProcessCipher()
555 …MHalHdcpRegMaskWrite(DEF_HDCP22_RX_REG_BANK + u16BKOffset, 0x4E, 0x0001, bEnable ? 0x0001 : 0x0000… in MHal_HDCP_HDCP2RxSetSKEPass()
580 *pu8State = MHalHdcpRegRead(DEF_HDCP22_RX_REG_BANK + u16BKOffset, 0x4E) & 0x01; in MHal_HDCP_HDCP2RxGetCipherState()
H A DregHDCP.h116 #define DEF_HDCP22_RX_REG_BANK 0x071200U // 0x171200U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maxim/hdcp/
H A DhalHDCP.c585 MHalHdcpRegMaskWrite(DEF_HDCP22_RX_REG_BANK + u16BKOffset, 0x4E, 0x0006, 0x0006); in MHal_HDCP_HDCP2RxInit()
608 MHalHdcpRegMaskWrite(DEF_HDCP22_RX_REG_BANK + u16BKOffset, 0x4E, 0x0001, 0x0001); in MHal_HDCP_HDCP2RxProcessCipher()
617 …MHalHdcpRegMaskWrite(DEF_HDCP22_RX_REG_BANK + u16BKOffset, 0x4E, 0x0001, bEnable ? 0x0001 : 0x0000… in MHal_HDCP_HDCP2RxSetSKEPass()
642 *pu8State = MHalHdcpRegRead(DEF_HDCP22_RX_REG_BANK + u16BKOffset, 0x4E) & 0x01; in MHal_HDCP_HDCP2RxGetCipherState()
H A DregHDCP.h116 #define DEF_HDCP22_RX_REG_BANK 0x071200U // 0x171200U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/kano/hdcp/
H A DhalHDCP.c593 MHalHdcpRegMaskWrite(DEF_HDCP22_RX_REG_BANK + u16BKOffset, 0x4E, 0x0006, 0x0006); in MHal_HDCP_HDCP2RxInit()
615 MHalHdcpRegMaskWrite(DEF_HDCP22_RX_REG_BANK + u16BKOffset, 0x4E, 0x0001, 0x0001); in MHal_HDCP_HDCP2RxProcessCipher()
624 …MHalHdcpRegMaskWrite(DEF_HDCP22_RX_REG_BANK + u16BKOffset, 0x4E, 0x0001, bEnable ? 0x0001 : 0x0000… in MHal_HDCP_HDCP2RxSetSKEPass()
649 *pu8State = MHalHdcpRegRead(DEF_HDCP22_RX_REG_BANK + u16BKOffset, 0x4E) & 0x01; in MHal_HDCP_HDCP2RxGetCipherState()
H A DregHDCP.h116 #define DEF_HDCP22_RX_REG_BANK 0x072200U // 0x172200U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/macan/hdcp/
H A DhalHDCP.c162 #define DEF_HDCP22_RX_REG_BANK 0x071200U //0x171200U macro
345 MHalHdcpRegMaskWrite(DEF_HDCP22_RX_REG_BANK + u16BKOffset, 0x4E, 0x0001, 0x0001); in MHal_HDCP_HDCP2RxProcessCipher()
355 *pu8State = MHalHdcpRegRead(DEF_HDCP22_RX_REG_BANK + u16BKOffset, 0x4E) & 0x01; in MHal_HDCP_HDCP2RxGetCipherState()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mooney/hdcp/
H A DhalHDCP.c333 MHalHdcpRegMaskWrite(DEF_HDCP22_RX_REG_BANK + u16BKOffset, 0x4E, 0x0001, 0x0001); in MHal_HDCP_HDCP2RxProcessCipher()
343 *pu8State = MHalHdcpRegRead(DEF_HDCP22_RX_REG_BANK + u16BKOffset, 0x4E) & 0x01; in MHal_HDCP_HDCP2RxGetCipherState()
H A DregHDCP.h114 #define DEF_HDCP22_RX_REG_BANK 0x071200U // 0x171200U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/k6/hdcp/
H A DhalHDCP.c519 MHalHdcpRegMaskWrite(DEF_HDCP22_RX_REG_BANK + u16BKOffset, 0x4E, 0x0001, 0x0001); in MHal_HDCP_HDCP2RxProcessCipher()
529 *pu8State = MHalHdcpRegRead(DEF_HDCP22_RX_REG_BANK + u16BKOffset, 0x4E) & 0x01; in MHal_HDCP_HDCP2RxGetCipherState()
H A DregHDCP.h114 #define DEF_HDCP22_RX_REG_BANK 0x072200U // 0x172200U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/curry/hdcp/
H A DregHDCP.h116 #define DEF_HDCP22_RX_REG_BANK 0x072200U // 0x172200U macro