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Searched refs:DEF_HDCP14_TX_REG_BANK (Results 1 – 19 of 19) sorted by relevance

/utopia/UTPA2-700.0.x/modules/hdmi/hal/curry/hdcp/
H A DhalHDCP.c221 MHalHdcpRegMaskWrite(DEF_HDCP14_TX_REG_BANK, 0x0001, 0x8000, 0x8000); // Enable HDCP encryption in MHal_HDCP_HDCP14TxInitHdcp()
222 …MHalHdcpRegMaskWrite(DEF_HDCP14_TX_REG_BANK, 0x0002, 0x001C, 0x0000); //[4]: 1: km new mode; 0: km… in MHal_HDCP_HDCP14TxInitHdcp()
238 MHalHdcpRegMaskWrite(DEF_HDCP14_TX_REG_BANK, 0x0002, 0x000F, 0x000C); in MHal_HDCP_HDCP14TxSetAuthPass()
247 MHalHdcpRegMaskWrite(DEF_HDCP14_TX_REG_BANK, 0x0002, 0x0008, 0x0008); in MHal_HDCP_HDCP14TxEnableENC_EN()
249 MHalHdcpRegMaskWrite(DEF_HDCP14_TX_REG_BANK, 0x0002, 0x0008, 0x0000); in MHal_HDCP_HDCP14TxEnableENC_EN()
260 MHalHdcpRegMaskWrite(DEF_HDCP14_TX_REG_BANK, 0x0001, 0x0100, 0x0100); in MHal_HDCP_HDCP14TxProcessAn()
261 MHalHdcpRegMaskWrite(DEF_HDCP14_TX_REG_BANK, 0x0002, 0x0002, 0x0002); in MHal_HDCP_HDCP14TxProcessAn()
262 MHalHdcpRegMaskWrite(DEF_HDCP14_TX_REG_BANK, 0x0002, 0x0002, 0x0000); in MHal_HDCP_HDCP14TxProcessAn()
268 *(pu8An + 2*i) = MHalHdcpRegRead(DEF_HDCP14_TX_REG_BANK, 0x0008 + i) & 0x00FF; in MHal_HDCP_HDCP14TxProcessAn()
269 … *(pu8An + 2*i + 1) = (MHalHdcpRegRead(DEF_HDCP14_TX_REG_BANK, 0x0008 + i) & 0xFF00) >> 8; in MHal_HDCP_HDCP14TxProcessAn()
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H A DregHDCP.h107 #define DEF_HDCP14_TX_REG_BANK 0x072B00U // 0x172B00U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/k6/hdcp/
H A DhalHDCP.c221 MHalHdcpRegMaskWrite(DEF_HDCP14_TX_REG_BANK, 0x0001, 0x8000, 0x8000); // Enable HDCP encryption in MHal_HDCP_HDCP14TxInitHdcp()
222 …MHalHdcpRegMaskWrite(DEF_HDCP14_TX_REG_BANK, 0x0002, 0x001C, 0x0000); //[4]: 1: km new mode; 0: km… in MHal_HDCP_HDCP14TxInitHdcp()
238 MHalHdcpRegMaskWrite(DEF_HDCP14_TX_REG_BANK, 0x0002, 0x000F, 0x000C); in MHal_HDCP_HDCP14TxSetAuthPass()
247 MHalHdcpRegMaskWrite(DEF_HDCP14_TX_REG_BANK, 0x0002, 0x0008, 0x0008); in MHal_HDCP_HDCP14TxEnableENC_EN()
249 MHalHdcpRegMaskWrite(DEF_HDCP14_TX_REG_BANK, 0x0002, 0x0008, 0x0000); in MHal_HDCP_HDCP14TxEnableENC_EN()
260 MHalHdcpRegMaskWrite(DEF_HDCP14_TX_REG_BANK, 0x0001, 0x0100, 0x0100); in MHal_HDCP_HDCP14TxProcessAn()
261 MHalHdcpRegMaskWrite(DEF_HDCP14_TX_REG_BANK, 0x0002, 0x0002, 0x0002); in MHal_HDCP_HDCP14TxProcessAn()
262 MHalHdcpRegMaskWrite(DEF_HDCP14_TX_REG_BANK, 0x0002, 0x0002, 0x0000); in MHal_HDCP_HDCP14TxProcessAn()
268 *(pu8An + 2*i) = MHalHdcpRegRead(DEF_HDCP14_TX_REG_BANK, 0x0008 + i) & 0x00FF; in MHal_HDCP_HDCP14TxProcessAn()
269 … *(pu8An + 2*i + 1) = (MHalHdcpRegRead(DEF_HDCP14_TX_REG_BANK, 0x0008 + i) & 0xFF00) >> 8; in MHal_HDCP_HDCP14TxProcessAn()
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H A DregHDCP.h107 #define DEF_HDCP14_TX_REG_BANK 0x072B00U // 0x172B00U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/k6lite/hdcp/
H A DhalHDCP.c221 MHalHdcpRegMaskWrite(DEF_HDCP14_TX_REG_BANK, 0x0001, 0x8000, 0x8000); // Enable HDCP encryption in MHal_HDCP_HDCP14TxInitHdcp()
222 …MHalHdcpRegMaskWrite(DEF_HDCP14_TX_REG_BANK, 0x0002, 0x001C, 0x0000); //[4]: 1: km new mode; 0: km… in MHal_HDCP_HDCP14TxInitHdcp()
238 MHalHdcpRegMaskWrite(DEF_HDCP14_TX_REG_BANK, 0x0002, 0x000F, 0x000C); in MHal_HDCP_HDCP14TxSetAuthPass()
247 MHalHdcpRegMaskWrite(DEF_HDCP14_TX_REG_BANK, 0x0002, 0x0008, 0x0008); in MHal_HDCP_HDCP14TxEnableENC_EN()
249 MHalHdcpRegMaskWrite(DEF_HDCP14_TX_REG_BANK, 0x0002, 0x0008, 0x0000); in MHal_HDCP_HDCP14TxEnableENC_EN()
260 MHalHdcpRegMaskWrite(DEF_HDCP14_TX_REG_BANK, 0x0001, 0x0100, 0x0100); in MHal_HDCP_HDCP14TxProcessAn()
261 MHalHdcpRegMaskWrite(DEF_HDCP14_TX_REG_BANK, 0x0002, 0x0002, 0x0002); in MHal_HDCP_HDCP14TxProcessAn()
262 MHalHdcpRegMaskWrite(DEF_HDCP14_TX_REG_BANK, 0x0002, 0x0002, 0x0000); in MHal_HDCP_HDCP14TxProcessAn()
268 *(pu8An + 2*i) = MHalHdcpRegRead(DEF_HDCP14_TX_REG_BANK, 0x0008 + i) & 0x00FF; in MHal_HDCP_HDCP14TxProcessAn()
269 … *(pu8An + 2*i + 1) = (MHalHdcpRegRead(DEF_HDCP14_TX_REG_BANK, 0x0008 + i) & 0xFF00) >> 8; in MHal_HDCP_HDCP14TxProcessAn()
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H A DregHDCP.h107 #define DEF_HDCP14_TX_REG_BANK 0x072B00U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7621/hdcp/
H A DhalHDCP.c220 MHalHdcpRegMaskWrite(DEF_HDCP14_TX_REG_BANK, 0x0001, 0x8000, 0x8000); // Enable HDCP encryption in MHal_HDCP_HDCP14TxInitHdcp()
221 …MHalHdcpRegMaskWrite(DEF_HDCP14_TX_REG_BANK, 0x0002, 0x001C, 0x0000); //[4]: 1: km new mode; 0: km… in MHal_HDCP_HDCP14TxInitHdcp()
236 MHalHdcpRegMaskWrite(DEF_HDCP14_TX_REG_BANK, 0x0002, 0x000F, 0x000C); in MHal_HDCP_HDCP14TxSetAuthPass()
244 MHalHdcpRegMaskWrite(DEF_HDCP14_TX_REG_BANK, 0x0002, 0x0008, 0x0008); in MHal_HDCP_HDCP14TxEnableENC_EN()
246 MHalHdcpRegMaskWrite(DEF_HDCP14_TX_REG_BANK, 0x0002, 0x0008, 0x0000); in MHal_HDCP_HDCP14TxEnableENC_EN()
256 MHalHdcpRegMaskWrite(DEF_HDCP14_TX_REG_BANK, 0x0001, 0x0100, 0x0100); in MHal_HDCP_HDCP14TxProcessAn()
257 MHalHdcpRegMaskWrite(DEF_HDCP14_TX_REG_BANK, 0x0002, 0x0002, 0x0002); in MHal_HDCP_HDCP14TxProcessAn()
258 MHalHdcpRegMaskWrite(DEF_HDCP14_TX_REG_BANK, 0x0002, 0x0002, 0x0000); in MHal_HDCP_HDCP14TxProcessAn()
264 *(pu8An + 2*i) = MHalHdcpRegRead(DEF_HDCP14_TX_REG_BANK, 0x0008 + i) & 0x00FF; in MHal_HDCP_HDCP14TxProcessAn()
265 … *(pu8An + 2*i + 1) = (MHalHdcpRegRead(DEF_HDCP14_TX_REG_BANK, 0x0008 + i) & 0xFF00) >> 8; in MHal_HDCP_HDCP14TxProcessAn()
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H A DregHDCP.h107 #define DEF_HDCP14_TX_REG_BANK 0x072100U // 0x172100U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maxim/hdcp/
H A DhalHDCP.c220 MHalHdcpRegMaskWrite(DEF_HDCP14_TX_REG_BANK, 0x0001, 0x8000, 0x8000); // Enable HDCP encryption in MHal_HDCP_HDCP14TxInitHdcp()
221 …MHalHdcpRegMaskWrite(DEF_HDCP14_TX_REG_BANK, 0x0002, 0x001C, 0x0000); //[4]: 1: km new mode; 0: km… in MHal_HDCP_HDCP14TxInitHdcp()
236 MHalHdcpRegMaskWrite(DEF_HDCP14_TX_REG_BANK, 0x0002, 0x000F, 0x000C); in MHal_HDCP_HDCP14TxSetAuthPass()
244 MHalHdcpRegMaskWrite(DEF_HDCP14_TX_REG_BANK, 0x0002, 0x0008, 0x0008); in MHal_HDCP_HDCP14TxEnableENC_EN()
246 MHalHdcpRegMaskWrite(DEF_HDCP14_TX_REG_BANK, 0x0002, 0x0008, 0x0000); in MHal_HDCP_HDCP14TxEnableENC_EN()
256 MHalHdcpRegMaskWrite(DEF_HDCP14_TX_REG_BANK, 0x0001, 0x0100, 0x0100); in MHal_HDCP_HDCP14TxProcessAn()
257 MHalHdcpRegMaskWrite(DEF_HDCP14_TX_REG_BANK, 0x0002, 0x0002, 0x0002); in MHal_HDCP_HDCP14TxProcessAn()
258 MHalHdcpRegMaskWrite(DEF_HDCP14_TX_REG_BANK, 0x0002, 0x0002, 0x0000); in MHal_HDCP_HDCP14TxProcessAn()
264 *(pu8An + 2*i) = MHalHdcpRegRead(DEF_HDCP14_TX_REG_BANK, 0x0008 + i) & 0x00FF; in MHal_HDCP_HDCP14TxProcessAn()
265 … *(pu8An + 2*i + 1) = (MHalHdcpRegRead(DEF_HDCP14_TX_REG_BANK, 0x0008 + i) & 0xFF00) >> 8; in MHal_HDCP_HDCP14TxProcessAn()
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H A DregHDCP.h107 #define DEF_HDCP14_TX_REG_BANK 0x072100U // 0x172100U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/kano/hdcp/
H A DhalHDCP.c221 MHalHdcpRegMaskWrite(DEF_HDCP14_TX_REG_BANK, 0x0001, 0x8000, 0x8000); // Enable HDCP encryption in MHal_HDCP_HDCP14TxInitHdcp()
222 …MHalHdcpRegMaskWrite(DEF_HDCP14_TX_REG_BANK, 0x0002, 0x001C, 0x0000); //[4]: 1: km new mode; 0: km… in MHal_HDCP_HDCP14TxInitHdcp()
238 MHalHdcpRegMaskWrite(DEF_HDCP14_TX_REG_BANK, 0x0002, 0x000F, 0x000C); in MHal_HDCP_HDCP14TxSetAuthPass()
247 MHalHdcpRegMaskWrite(DEF_HDCP14_TX_REG_BANK, 0x0002, 0x0008, 0x0008); in MHal_HDCP_HDCP14TxEnableENC_EN()
249 MHalHdcpRegMaskWrite(DEF_HDCP14_TX_REG_BANK, 0x0002, 0x0008, 0x0000); in MHal_HDCP_HDCP14TxEnableENC_EN()
260 MHalHdcpRegMaskWrite(DEF_HDCP14_TX_REG_BANK, 0x0001, 0x0100, 0x0100); in MHal_HDCP_HDCP14TxProcessAn()
261 MHalHdcpRegMaskWrite(DEF_HDCP14_TX_REG_BANK, 0x0002, 0x0002, 0x0002); in MHal_HDCP_HDCP14TxProcessAn()
262 MHalHdcpRegMaskWrite(DEF_HDCP14_TX_REG_BANK, 0x0002, 0x0002, 0x0000); in MHal_HDCP_HDCP14TxProcessAn()
268 *(pu8An + 2*i) = MHalHdcpRegRead(DEF_HDCP14_TX_REG_BANK, 0x0008 + i) & 0x00FF; in MHal_HDCP_HDCP14TxProcessAn()
269 … *(pu8An + 2*i + 1) = (MHalHdcpRegRead(DEF_HDCP14_TX_REG_BANK, 0x0008 + i) & 0xFF00) >> 8; in MHal_HDCP_HDCP14TxProcessAn()
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H A DregHDCP.h107 #define DEF_HDCP14_TX_REG_BANK 0x072B00U // 0x172B00U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mooney/hdcp/
H A DregHDCP.h107 #define DEF_HDCP14_TX_REG_BANK 0x072B00U // 0x172B00U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mainz/hdcp/
H A DregHDCP.h107 #define DEF_HDCP14_TX_REG_BANK 0x000000U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7821/hdcp/
H A DregHDCP.h107 #define DEF_HDCP14_TX_REG_BANK 0x000000U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/manhattan/hdcp/
H A DregHDCP.h107 #define DEF_HDCP14_TX_REG_BANK 0x000000U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/messi/hdcp/
H A DregHDCP.h107 #define DEF_HDCP14_TX_REG_BANK 0x000000U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maserati/hdcp/
H A DregHDCP.h107 #define DEF_HDCP14_TX_REG_BANK 0x000000U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/macan/hdcp/
H A DhalHDCP.c155 #define DEF_HDCP14_TX_REG_BANK 0x072B00U //0x172B00U macro