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/utopia/UTPA2-700.0.x/modules/gpio/hal/maldives/gpio/
H A DhalGPIO.c112 #define BIT7 BIT(7) macro
274 #define GPIO29_OUT 0x0e4e, BIT7
393 #define GPIO53_OEN 0x101e5C, BIT7
394 #define GPIO53_OUT 0x101e56, BIT7
395 #define GPIO53_IN 0x101e50, BIT7
433 #define GPIO61_OEN 0x101e5D, BIT7
434 #define GPIO61_OUT 0x101e57, BIT7
435 #define GPIO61_IN 0x101e51, BIT7
473 #define GPIO69_OEN 0x101e5E, BIT7
474 #define GPIO69_OUT 0x101e58, BIT7
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/utopia/UTPA2-700.0.x/modules/gpio/hal/mustang/gpio/
H A DhalGPIO.c112 #define BIT7 BIT(7) macro
274 #define GPIO29_OUT 0x0e4e, BIT7
408 #define GPIO56_OEN 0x101e5C, BIT7
409 #define GPIO56_OUT 0x101e56, BIT7
410 #define GPIO56_IN 0x101e50, BIT7
448 #define GPIO64_OEN 0x101e5D, BIT7
449 #define GPIO64_OUT 0x101e57, BIT7
450 #define GPIO64_IN 0x101e51, BIT7
488 #define GPIO72_OEN 0x101e5E, BIT7
489 #define GPIO72_OUT 0x101e58, BIT7
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/utopia/UTPA2-700.0.x/modules/mvop/hal/k7u/mvop/
H A DregMVOP.h153 #define VOP_MVD_VS_SEL BIT7
158 #define VOP_SC_VS_INV BIT7
166 #define VOP_BURST_ST_SEL BIT7
183 #define VOP_FORCE_HIGH BIT7 //Force DMA High priority
190 #define VOP_SYNC_2_DC_TIMING BIT7
219 #define EVD_ENABLE BIT7
227 #define VOP_DEBUG_SEL (BIT5 | BIT6 | BIT7) //u3 new: MVOP debug out select
230 #define VOP_RAMAP_LUMA_EN BIT7
235 #define VOP_RAMAP_CHROMA_EN BIT7
243 #define VOP_SEND_DATA_FLAG BIT7
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/utopia/UTPA2-700.0.x/modules/mvop/hal/k6lite/mvop/
H A DregMVOP.h152 #define VOP_MVD_VS_SEL BIT7
157 #define VOP_SC_VS_INV BIT7
165 #define VOP_BURST_ST_SEL BIT7
182 #define VOP_FORCE_HIGH BIT7 //Force DMA High priority
214 #define EVD_ENABLE BIT7
222 #define VOP_DEBUG_SEL (BIT5 | BIT6 | BIT7) //u3 new: MVOP debug out select
225 #define VOP_RAMAP_LUMA_EN BIT7
230 #define VOP_RAMAP_CHROMA_EN BIT7
238 #define VOP_SEND_DATA_FLAG BIT7
242 #define VOP_DMA_STATUS (BIT7 | BIT6 | BIT5 | BIT4)
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/utopia/UTPA2-700.0.x/modules/mvop/hal/kastor/mvop/
H A DregMVOP.h152 #define VOP_MVD_VS_SEL BIT7
156 #define VOP_SC_VS_INV BIT7
164 #define VOP_BURST_ST_SEL BIT7
181 #define VOP_FORCE_HIGH BIT7 //Force DMA High priority
211 #define EVD_ENABLE BIT7
219 #define VOP_DEBUG_SEL (BIT5 | BIT6 | BIT7) //u3 new: MVOP debug out select
222 #define VOP_RAMAP_LUMA_EN BIT7
227 #define VOP_RAMAP_CHROMA_EN BIT7
235 #define VOP_SEND_DATA_FLAG BIT7
239 #define VOP_DMA_STATUS (BIT7 | BIT6 | BIT5 | BIT4)
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/utopia/UTPA2-700.0.x/modules/mvop/hal/curry/mvop/
H A DregMVOP.h150 #define VOP_MVD_VS_SEL BIT7
154 #define VOP_SC_VS_INV BIT7
162 #define VOP_BURST_ST_SEL BIT7
179 #define VOP_FORCE_HIGH BIT7 //Force DMA High priority
208 #define EVD_ENABLE BIT7
216 #define VOP_DEBUG_SEL (BIT5 | BIT6 | BIT7) //u3 new: MVOP debug out select
219 #define VOP_RAMAP_LUMA_EN BIT7
224 #define VOP_RAMAP_CHROMA_EN BIT7
232 #define VOP_SEND_DATA_FLAG BIT7
236 #define VOP_DMA_STATUS (BIT7 | BIT6 | BIT5 | BIT4)
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/utopia/UTPA2-700.0.x/modules/mvop/hal/kano/mvop/
H A DregMVOP.h150 #define VOP_MVD_VS_SEL BIT7
155 #define VOP_SC_VS_INV BIT7
163 #define VOP_BURST_ST_SEL BIT7
180 #define VOP_FORCE_HIGH BIT7 //Force DMA High priority
209 #define EVD_ENABLE BIT7
217 #define VOP_DEBUG_SEL (BIT5 | BIT6 | BIT7) //u3 new: MVOP debug out select
220 #define VOP_RAMAP_LUMA_EN BIT7
225 #define VOP_RAMAP_CHROMA_EN BIT7
233 #define VOP_SEND_DATA_FLAG BIT7
237 #define VOP_DMA_STATUS (BIT7 | BIT6 | BIT5 | BIT4)
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/utopia/UTPA2-700.0.x/modules/mvop/hal/k6/mvop/
H A DregMVOP.h152 #define VOP_MVD_VS_SEL BIT7
157 #define VOP_SC_VS_INV BIT7
165 #define VOP_BURST_ST_SEL BIT7
182 #define VOP_FORCE_HIGH BIT7 //Force DMA High priority
214 #define EVD_ENABLE BIT7
222 #define VOP_DEBUG_SEL (BIT5 | BIT6 | BIT7) //u3 new: MVOP debug out select
225 #define VOP_RAMAP_LUMA_EN BIT7
230 #define VOP_RAMAP_CHROMA_EN BIT7
238 #define VOP_SEND_DATA_FLAG BIT7
242 #define VOP_DMA_STATUS (BIT7 | BIT6 | BIT5 | BIT4)
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/utopia/UTPA2-700.0.x/modules/mvop/hal/mooney/mvop/
H A DregMVOP.h153 #define VOP_MVD_VS_SEL BIT7
164 #define VOP_BURST_ST_SEL BIT7
181 #define VOP_FORCE_HIGH BIT7 //Force DMA High priority
186 #define VOP_SYNC_2_DC_TIMING BIT7
216 #define VOP_DEBUG_SEL (BIT5 | BIT6 | BIT7) //u3 new: MVOP debug out select
219 #define EVD_ENABLE BIT7
224 #define VOP_RAMAP_LUMA_EN BIT7
229 #define VOP_RAMAP_CHROMA_EN BIT7
245 #define VOP_RIU_DEBUG_SEL (BIT6|BIT7) //RIU debug register select
266 #define VOP_MSB_BUF1_MIU_SEL (BIT6|BIT7) // UV miu select: miu0~3 = 0x0~0x3
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/utopia/UTPA2-700.0.x/modules/mvop/hal/M7621/mvop/
H A DregMVOP.h153 #define VOP_MVD_VS_SEL BIT7
164 #define VOP_BURST_ST_SEL BIT7
181 #define VOP_FORCE_HIGH BIT7 //Force DMA High priority
186 #define VOP_SYNC_2_DC_TIMING BIT7
216 #define VOP_DEBUG_SEL (BIT5 | BIT6 | BIT7) //u3 new: MVOP debug out select
220 #define EVD_ENABLE BIT7
225 #define VOP_RAMAP_LUMA_EN BIT7
230 #define VOP_RAMAP_CHROMA_EN BIT7
246 #define VOP_RIU_DEBUG_SEL (BIT6|BIT7) //RIU debug register select
267 #define VOP_MSB_BUF1_MIU_SEL (BIT6|BIT7) // UV miu select: miu0~3 = 0x0~0x3
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/utopia/UTPA2-700.0.x/modules/mvop/hal/maxim/mvop/
H A DregMVOP.h152 #define VOP_MVD_VS_SEL BIT7
164 #define VOP_BURST_ST_SEL BIT7
181 #define VOP_FORCE_HIGH BIT7 //Force DMA High priority
186 #define VOP_SYNC_2_DC_TIMING BIT7
216 #define VOP_DEBUG_SEL (BIT5 | BIT6 | BIT7) //u3 new: MVOP debug out select
220 #define EVD_ENABLE BIT7
225 #define VOP_RAMAP_LUMA_EN BIT7
230 #define VOP_RAMAP_CHROMA_EN BIT7
246 #define VOP_RIU_DEBUG_SEL (BIT6|BIT7) //RIU debug register select
267 #define VOP_MSB_BUF1_MIU_SEL (BIT6|BIT7) // UV miu select: miu0~3 = 0x0~0x3
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/utopia/UTPA2-700.0.x/modules/mvop/hal/M7821/mvop/
H A DregMVOP.h151 #define VOP_MVD_VS_SEL BIT7
162 #define VOP_BURST_ST_SEL BIT7
179 #define VOP_FORCE_HIGH BIT7 //Force DMA High priority
184 #define VOP_SYNC_2_DC_TIMING BIT7
214 #define VOP_DEBUG_SEL (BIT5 | BIT6 | BIT7) //u3 new: MVOP debug out select
218 #define EVD_ENABLE BIT7
223 #define VOP_RAMAP_LUMA_EN BIT7
228 #define VOP_RAMAP_CHROMA_EN BIT7
244 #define VOP_RIU_DEBUG_SEL (BIT6|BIT7) //RIU debug register select
265 #define VOP_MSB_BUF1_MIU_SEL (BIT6|BIT7) // UV miu select: miu0~3 = 0x0~0x3
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/utopia/UTPA2-700.0.x/modules/mvop/hal/maserati/mvop/
H A DregMVOP.h151 #define VOP_MVD_VS_SEL BIT7
163 #define VOP_BURST_ST_SEL BIT7
180 #define VOP_FORCE_HIGH BIT7 //Force DMA High priority
185 #define VOP_SYNC_2_DC_TIMING BIT7
215 #define VOP_DEBUG_SEL (BIT5 | BIT6 | BIT7) //u3 new: MVOP debug out select
219 #define EVD_ENABLE BIT7
224 #define VOP_RAMAP_LUMA_EN BIT7
229 #define VOP_RAMAP_CHROMA_EN BIT7
245 #define VOP_RIU_DEBUG_SEL (BIT6|BIT7) //RIU debug register select
266 #define VOP_MSB_BUF1_MIU_SEL (BIT6|BIT7) // UV miu select: miu0~3 = 0x0~0x3
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/utopia/UTPA2-700.0.x/modules/mvop/hal/M5621/mvop/
H A DregMVOP.h150 #define VOP_MVD_VS_SEL BIT7
155 #define VOP_SC_VS_INV BIT7
163 #define VOP_BURST_ST_SEL BIT7
180 #define VOP_FORCE_HIGH BIT7 //Force DMA High priority
211 #define VOP_DEBUG_SEL (BIT5 | BIT6 | BIT7) //u3 new: MVOP debug out select
215 #define EVD_ENABLE BIT7
220 #define VOP_RAMAP_LUMA_EN BIT7
225 #define VOP_RAMAP_CHROMA_EN BIT7
241 #define VOP_RIU_DEBUG_SEL (BIT6|BIT7) //RIU debug register select
262 #define VOP_MSB_BUF1_MIU_SEL (BIT6|BIT7) // UV miu select: miu0~3 = 0x0~0x3
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/utopia/UTPA2-700.0.x/modules/mvop/hal/macan/mvop/
H A DregMVOP.h151 #define VOP_MVD_VS_SEL BIT7
162 #define VOP_BURST_ST_SEL BIT7
179 #define VOP_FORCE_HIGH BIT7 //Force DMA High priority
184 #define VOP_SYNC_2_DC_TIMING BIT7
212 #define VOP_DEBUG_SEL (BIT5 | BIT6 | BIT7) //u3 new: MVOP debug out select
215 #define EVD_ENABLE BIT7
220 #define VOP_RAMAP_LUMA_EN BIT7
225 #define VOP_RAMAP_CHROMA_EN BIT7
241 #define VOP_RIU_DEBUG_SEL (BIT6|BIT7) //RIU debug register select
262 #define VOP_MSB_BUF1_MIU_SEL (BIT6|BIT7) // UV miu select: miu0~3 = 0x0~0x3
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/utopia/UTPA2-700.0.x/modules/mvop/hal/mustang/mvop/
H A DregMVOP.h150 #define VOP_MVD_VS_SEL BIT7
161 #define VOP_BURST_ST_SEL BIT7
178 #define VOP_FORCE_HIGH BIT7 //Force DMA High priority
209 #define VOP_DEBUG_SEL (BIT5 | BIT6 | BIT7) //u3 new: MVOP debug out select
213 #define EVD_ENABLE BIT7
218 #define VOP_RAMAP_LUMA_EN BIT7
223 #define VOP_RAMAP_CHROMA_EN BIT7
239 #define VOP_RIU_DEBUG_SEL (BIT6|BIT7) //RIU debug register select
260 #define VOP_MSB_BUF1_MIU_SEL (BIT6|BIT7) // UV miu select: miu0~3 = 0x0~0x3
278 #define VOP_INFO_FROM_CODEC_422_FMT (BIT7) //422 format
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/utopia/UTPA2-700.0.x/modules/mvop/hal/messi/mvop/
H A DregMVOP.h151 #define VOP_MVD_VS_SEL BIT7
162 #define VOP_BURST_ST_SEL BIT7
179 #define VOP_FORCE_HIGH BIT7 //Force DMA High priority
208 #define VOP_DEBUG_SEL (BIT5 | BIT6 | BIT7) //u3 new: MVOP debug out select
211 #define EVD_ENABLE BIT7
216 #define VOP_RAMAP_LUMA_EN BIT7
221 #define VOP_RAMAP_CHROMA_EN BIT7
237 #define VOP_RIU_DEBUG_SEL (BIT6|BIT7) //RIU debug register select
258 #define VOP_MSB_BUF1_MIU_SEL (BIT6|BIT7) // UV miu select: miu0~3 = 0x0~0x3
276 #define VOP_INFO_FROM_CODEC_422_FMT (BIT7) //422 format
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/utopia/UTPA2-700.0.x/modules/mvop/hal/manhattan/mvop/
H A DregMVOP.h151 #define VOP_MVD_VS_SEL BIT7
162 #define VOP_BURST_ST_SEL BIT7
179 #define VOP_FORCE_HIGH BIT7 //Force DMA High priority
208 #define VOP_DEBUG_SEL (BIT5 | BIT6 | BIT7) //u3 new: MVOP debug out select
211 #define EVD_ENABLE BIT7
216 #define VOP_RAMAP_LUMA_EN BIT7
221 #define VOP_RAMAP_CHROMA_EN BIT7
237 #define VOP_RIU_DEBUG_SEL (BIT6|BIT7) //RIU debug register select
258 #define VOP_MSB_BUF1_MIU_SEL (BIT6|BIT7) // UV miu select: miu0~3 = 0x0~0x3
276 #define VOP_INFO_FROM_CODEC_422_FMT (BIT7) //422 format
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/utopia/UTPA2-700.0.x/modules/mvop/hal/mainz/mvop/
H A DregMVOP.h151 #define VOP_MVD_VS_SEL BIT7
162 #define VOP_BURST_ST_SEL BIT7
179 #define VOP_FORCE_HIGH BIT7 //Force DMA High priority
208 #define VOP_DEBUG_SEL (BIT5 | BIT6 | BIT7) //u3 new: MVOP debug out select
211 #define EVD_ENABLE BIT7
216 #define VOP_RAMAP_LUMA_EN BIT7
221 #define VOP_RAMAP_CHROMA_EN BIT7
237 #define VOP_RIU_DEBUG_SEL (BIT6|BIT7) //RIU debug register select
258 #define VOP_MSB_BUF1_MIU_SEL (BIT6|BIT7) // UV miu select: miu0~3 = 0x0~0x3
276 #define VOP_INFO_FROM_CODEC_422_FMT (BIT7) //422 format
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/utopia/UTPA2-700.0.x/modules/pws/hal/maldives/pws/
H A DregCLKGEN.h113 #define CKG_MIU_MASK (BIT7 | BIT6)
138 #define CKG_AEON_INVERT BIT7
152 #define CKG_STC0_MASK (BIT7 | BIT6)
161 #define CKG_MAD_STC_MASK (BIT7 | BIT6)
179 #define CKG_MVD_MASK (BIT7 | BIT6)
196 #define CKG_DC0_MASK (BIT7 | BIT6)
220 #define CKG_GE_MASK (BIT7 | BIT6)
238 #define CKG_GOPG1_MASK (BIT7 | BIT6)
256 #define CKG_VD_MASK (BIT7 | BIT6)
274 #define CKG_VD200_MASK (BIT7 | BIT6)
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/utopia/UTPA2-700.0.x/modules/pws/hal/k6/pws/
H A DregCLKGEN.h113 #define CKG_MIU_MASK (BIT7 | BIT6)
138 #define CKG_AEON_INVERT BIT7
152 #define CKG_STC0_MASK (BIT7 | BIT6)
161 #define CKG_MAD_STC_MASK (BIT7 | BIT6)
179 #define CKG_MVD_MASK (BIT7 | BIT6)
196 #define CKG_DC0_MASK (BIT7 | BIT6)
220 #define CKG_GE_MASK (BIT7 | BIT6)
238 #define CKG_GOPG1_MASK (BIT7 | BIT6)
256 #define CKG_VD_MASK (BIT7 | BIT6)
274 #define CKG_VD200_MASK (BIT7 | BIT6)
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/utopia/UTPA2-700.0.x/modules/pws/hal/macan/pws/
H A DregCLKGEN.h113 #define CKG_MIU_MASK (BIT7 | BIT6)
138 #define CKG_AEON_INVERT BIT7
152 #define CKG_STC0_MASK (BIT7 | BIT6)
161 #define CKG_MAD_STC_MASK (BIT7 | BIT6)
179 #define CKG_MVD_MASK (BIT7 | BIT6)
196 #define CKG_DC0_MASK (BIT7 | BIT6)
220 #define CKG_GE_MASK (BIT7 | BIT6)
238 #define CKG_GOPG1_MASK (BIT7 | BIT6)
256 #define CKG_VD_MASK (BIT7 | BIT6)
274 #define CKG_VD200_MASK (BIT7 | BIT6)
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/utopia/UTPA2-700.0.x/modules/pws/hal/mooney/pws/
H A DregCLKGEN.h113 #define CKG_MIU_MASK (BIT7 | BIT6)
138 #define CKG_AEON_INVERT BIT7
152 #define CKG_STC0_MASK (BIT7 | BIT6)
161 #define CKG_MAD_STC_MASK (BIT7 | BIT6)
179 #define CKG_MVD_MASK (BIT7 | BIT6)
196 #define CKG_DC0_MASK (BIT7 | BIT6)
220 #define CKG_GE_MASK (BIT7 | BIT6)
238 #define CKG_GOPG1_MASK (BIT7 | BIT6)
256 #define CKG_VD_MASK (BIT7 | BIT6)
274 #define CKG_VD200_MASK (BIT7 | BIT6)
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/utopia/UTPA2-700.0.x/modules/pws/hal/messi/pws/
H A DregCLKGEN.h113 #define CKG_MIU_MASK (BIT7 | BIT6)
138 #define CKG_AEON_INVERT BIT7
152 #define CKG_STC0_MASK (BIT7 | BIT6)
161 #define CKG_MAD_STC_MASK (BIT7 | BIT6)
179 #define CKG_MVD_MASK (BIT7 | BIT6)
196 #define CKG_DC0_MASK (BIT7 | BIT6)
220 #define CKG_GE_MASK (BIT7 | BIT6)
238 #define CKG_GOPG1_MASK (BIT7 | BIT6)
256 #define CKG_VD_MASK (BIT7 | BIT6)
274 #define CKG_VD200_MASK (BIT7 | BIT6)
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/utopia/UTPA2-700.0.x/modules/pws/hal/manhattan/pws/
H A DregCLKGEN.h113 #define CKG_MIU_MASK (BIT7 | BIT6)
138 #define CKG_AEON_INVERT BIT7
152 #define CKG_STC0_MASK (BIT7 | BIT6)
161 #define CKG_MAD_STC_MASK (BIT7 | BIT6)
179 #define CKG_MVD_MASK (BIT7 | BIT6)
196 #define CKG_DC0_MASK (BIT7 | BIT6)
220 #define CKG_GE_MASK (BIT7 | BIT6)
238 #define CKG_GOPG1_MASK (BIT7 | BIT6)
256 #define CKG_VD_MASK (BIT7 | BIT6)
274 #define CKG_VD200_MASK (BIT7 | BIT6)
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