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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 #ifndef _REG_VOP_H_ 96 #define _REG_VOP_H_ 97 98 99 //------------------------------------------------------------------------------------------------- 100 // Hardware Capability 101 //------------------------------------------------------------------------------------------------- 102 103 104 //------------------------------------------------------------------------------------------------- 105 // Macro and Define 106 //------------------------------------------------------------------------------------------------- 107 108 109 //------------------------------------------------------------------------------ 110 // Base Address 111 //------------------------------------------------------------------------------ 112 #define MVOP_REG_BASE 0x1400 // 0x1400 - 0x14FF 113 #define MVOP_SUB_REG_BASE 0x1300 // 0x1300 - 0x13FF 114 #define CHIP_REG_BASE 0x0B00 //chiptop CLKGEN0 115 #define SC_FE_REG_BASE 0x00037F00 //SC_FE 116 117 //------------------------------------------------------------------------------ 118 // MVOP Reg 119 //------------------------------------------------------------------------------ 120 #define VOP_FRAME_VCOUNT (MVOP_REG_BASE + 0x00) 121 #define VOP_FRAME_HCOUNT (MVOP_REG_BASE + 0x02) 122 #define VOP_VB0_STR (MVOP_REG_BASE + 0x04) 123 #define VOP_VB0_END (MVOP_REG_BASE + 0x06) 124 #define VOP_VB1_STR (MVOP_REG_BASE + 0x08) 125 #define VOP_VB1_END (MVOP_REG_BASE + 0x0A) 126 #define VOP_TF_STR (MVOP_REG_BASE + 0x0C) 127 #define VOP_BF_STR (MVOP_REG_BASE + 0x0E) 128 #define VOP_HACT_STR (MVOP_REG_BASE + 0x10) 129 #define VOP_IMG_HSTR (MVOP_REG_BASE + 0x12) 130 #define VOP_IMG_VSTR0 (MVOP_REG_BASE + 0x14) 131 #define VOP_IMG_VSTR1 (MVOP_REG_BASE + 0x16) 132 #define VOP_TF_VS (MVOP_REG_BASE + 0x18) 133 #define VOP_BF_VS (MVOP_REG_BASE + 0x1A) 134 135 136 ///TOP field Vsync start line number to MVD 137 #define VOP_TF_VS_MVD (MVOP_REG_BASE + 0x1C) //u3 new 138 ///Bottom field Vsync start line number to MVD 139 #define VOP_BF_VS_MVD (MVOP_REG_BASE + 0x1E) //u3 new 140 141 #define VOP_FSYNC_EN BIT4 //frame sync enable 142 #define VOP_CTRL0 (MVOP_REG_BASE + 0x22) 143 144 #define VOP_FLIP_UV BIT0 145 #define VOP_FLIP_YC BIT1 146 #define VOP_FLD_INV BIT2 147 #define VOP_OFLD_INV BIT4 148 #define VOP_CCIR_MD BIT5 149 #define VOP_MVD_VS_MD BIT6 //u3 new 0: Original mode;1: Use new vsync (tf_vs_mvd, bf_vs_mvd) 150 #define VOP_MVD_VS_SEL BIT7 151 #define VOP_CTRL1 (MVOP_REG_BASE + 0x23) 152 153 #define VOP_TST_IMG (MVOP_REG_BASE + 0x24) 154 155 #define VOP_U_PAT (MVOP_REG_BASE + 0x26) 156 157 #define VOP_DMA_THD (BIT0|BIT1|BIT2|BIT3|BIT4) 158 //DMA FIFO threshold 159 //= reg_dma_thd x 2 (reg_miu128b=1) 160 //= reg_dma_thd x 4 (reg_miu128b=0) 161 #define VOP_BURST_ST_SEL BIT7 162 //Timing to calculate burst length (only valid when reg_burst_ext = all) 163 //0: at mi2dc_rdy; 1: at dc2mi_rdy 164 #define VOP_DMA0 (MVOP_REG_BASE + 0x28) //t3 new 165 166 #define VOP_BURST_EXT (BIT0|BIT1|BIT2) 167 //DMA burst length 168 //0: 4 (reg_miu128b=1), 8 (reg_miu128b=0) 169 //1: 8 (reg_miu128b=1), 16 (reg_miu128b=0) 170 //2: 16 (reg_miu128b=1), 32 (reg_miu128b=0) 171 //3: 24 (reg_miu128b=1), 48 (reg_miu128b=0) 172 //4: 32 (reg_miu128b=1), 64 (reg_miu128b=0) 173 //5: 48 (reg_miu128b=1), 96 (reg_miu128b=0) 174 //6: 64 (reg_miu128b=1), 128 (reg_miu128b=0) 175 //7: all 176 #define VOP_HI_TSH (BIT3|BIT4|BIT5|BIT6) //DMA High priority threshold 177 //(assert high priority if data count less then reg_hi_tsh x 8) 178 #define VOP_FORCE_HIGH BIT7 //Force DMA High priority 179 #define VOP_DMA1 (MVOP_REG_BASE + 0x29) //t3 new 180 181 #define VOP_DC_STRIP_H (MVOP_REG_BASE + 0x30) 182 #define VOP_SRAM_SD_MASK BIT3 183 #define MFDEC_SRAM_SD_MASK BIT4 184 185 #define VOP_INT_MASK (MVOP_REG_BASE + 0x3E) 186 #define VOP_MPG_JPG_SWITCH (MVOP_REG_BASE + 0x40) 187 #define VOP_DRAM_RD_MODE BIT5 188 #define VOP_DC_STRIP (MVOP_REG_BASE + 0x41) 189 #define VOP_JPG_YSTR0_L (MVOP_REG_BASE + 0x42) 190 #define VOP_JPG_YSTR0_H (MVOP_REG_BASE + 0x44) 191 #define VOP_JPG_UVSTR0_L (MVOP_REG_BASE + 0x46) 192 #define VOP_JPG_UVSTR0_H (MVOP_REG_BASE + 0x48) 193 #define VOP_YUV_STR_HIBITS (BIT4 | BIT3 | BIT2 |BIT1 | BIT0) //Bits(28:24) 194 195 #define VOP_JPG_HSIZE (MVOP_REG_BASE + 0x4A) 196 #define VOP_JPG_VSIZE (MVOP_REG_BASE + 0x4C) 197 198 #define VOP_LOAD_REG BIT0 //load new value into active registers 0x20-0x26 199 #define VOP_TILE_FORMAT BIT1 //0: 8x32, 1: 16x32 200 #define VOP_BUF_DUAL BIT2 201 #define VOP_FORCELOAD_REG BIT4 //force load registers 202 #define VOP_REG_WR (MVOP_REG_BASE + 0x4E) 203 204 #define VOP_MVD_EN BIT0 //t8 new 205 #define VOP_H264_PUREY BIT1 206 //#define VOP_RVD_EN BIT2 //a3: removed 207 #define VOP_HVD_EN BIT3 208 #define VOP_FORCE_SC_RDY BIT4 //u3 new: force sc2mvop_rdy = 1 209 #define VOP_DEBUG_SEL (BIT5 | BIT6 | BIT7) //u3 new: MVOP debug out select 210 #define VOP_INPUT_SWITCH0 (MVOP_REG_BASE + 0x50) 211 #define VOP_TILE_32x32 BIT5 212 #define VOP_R2_WISHBONE BIT6 213 #define EVD_ENABLE BIT7 214 215 #define VOP_INPUT_SWITCH1 (MVOP_REG_BASE + 0x51) 216 217 #define VOP_RAMAP_LUMA_VAL 0x1f 218 #define VOP_RAMAP_LUMA_EN BIT7 219 #define VOP_RAMAP_LUMA (MVOP_REG_BASE + 0x52) 220 //u3 new: Luma range mapping for VC1 (value = 8~16) 221 222 #define VOP_RAMAP_CHROMA_VAL 0x1f 223 #define VOP_RAMAP_CHROMA_EN BIT7 224 #define VOP_RAMAP_CHROMA (MVOP_REG_BASE + 0x53) 225 //u3 new: Chroma range mapping for VC1 (value = 8~16) 226 227 // [T3 new 228 #define VOP_DEBUG_2A (MVOP_REG_BASE + 0x54) //2-byte 229 #define VOP_DEBUG_2B (MVOP_REG_BASE + 0x56) 230 #define VOP_DEBUG_2C (MVOP_REG_BASE + 0x58) 231 #define VOP_DEBUG_2D (MVOP_REG_BASE + 0x5A) 232 #define VOP_DEBUG_2E (MVOP_REG_BASE + 0x5C) 233 234 #define VOP_UF BIT0 //buf underflow 235 #define VOP_OF BIT1 //buf overflow 236 #define VOP_DEBUG_2F_L (MVOP_REG_BASE + 0x5E) 237 238 #define VOP_BIST_FAIL BIT0 //YUV fifo bist fail 239 #define VOP_RIU_DEBUG_SEL (BIT6|BIT7) //RIU debug register select 240 #define VOP_DEBUG_2F_H (MVOP_REG_BASE + 0x5F) 241 // ] 242 243 #define VOP_UV_SHIFT (MVOP_REG_BASE + 0x60) 244 245 #define VOP_GCLK_MIU_ON BIT2 //clk_miu use 0: free-run clock; 1: gated clock 246 #define VOP_GCLK_VCLK_ON BIT3 //clk_dc0 use 0: free-run clock; 1: gated clock 247 #define VOP_GCLK (MVOP_REG_BASE + 0x60) //u3 new 248 249 #define VOP_MIU_IF (MVOP_REG_BASE + 0x60) 250 #define VOP_MIU_128BIT BIT4 //MIU bus use 0: 64bit 1:128bit 251 #define VOP_MIU_128B_I64 BIT5 252 #define VOP_MIU_REQ_DIS BIT6 253 254 #define VOP_MIU_BUS (MVOP_REG_BASE + 0x60) //t3 new 255 256 #define VOP_MIU_SEL (MVOP_REG_BASE + 0x61) //kaiser new 257 #define VOP_MSB_MIU_DIFF BIT0 258 #define VOP_LSB_MIU_DIFF BIT1 259 #define VOP_MSB_BUF0_MIU_SEL (BIT4|BIT5) // Y miu select: miu0~3 = 0x0~0x3 260 #define VOP_MSB_BUF1_MIU_SEL (BIT6|BIT7) // UV miu select: miu0~3 = 0x0~0x3 261 262 #define VOP_JPG_YSTR1_L (MVOP_REG_BASE + 0x62) 263 #define VOP_JPG_YSTR1_H (MVOP_REG_BASE + 0x64) 264 #define VOP_JPG_UVSTR1_L (MVOP_REG_BASE + 0x66) 265 #define VOP_JPG_UVSTR1_H (MVOP_REG_BASE + 0x68) 266 267 #define VOP_SYNC_FRAME_V (MVOP_REG_BASE + 0x6A) 268 #define VOP_SYNC_FRAME_H (MVOP_REG_BASE + 0x6C) 269 270 #define VOP_INFO_FROM_CODEC_L (MVOP_REG_BASE + 0x70) 271 #define VOP_INFO_FROM_CODEC_BASE_ADDR (BIT0) //base address 272 #define VOP_INFO_FROM_CODEC_PITCH (BIT1) //pitch 273 #define VOP_INFO_FROM_CODEC_SIZE (BIT2) //size 274 #define VOP_INFO_FROM_CODEC_PROG_SEQ (BIT3) //progressive sequence 275 #define VOP_INFO_FROM_CODEC_FIELD (BIT4) //field 276 #define VOP_INFO_FROM_CODEC_RANGE_MAP (BIT5) //range map 277 #define VOP_INFO_FROM_CODEC_COMP_MODE (BIT6) //compression mode 278 #define VOP_INFO_FROM_CODEC_422_FMT (BIT7) //422 format 279 280 #define VOP_INFO_FROM_CODEC_H (MVOP_REG_BASE + 0x71) 281 #define VOP_INFO_FROM_CODEC_DUAL_BUFF (BIT0) //dual buffer flag 282 #define VOP_INFO_FROM_CODEC_BPIC_REDUCT (BIT1) //bpic reduction 283 #define VOP_INFO_FROM_CODEC_MIU_BUF0_SEL (BIT4) //MSB miu select 284 #define VOP_INFO_FROM_CODEC_MIU_BUF1_SEL (BIT5) //LSB miu select 285 #define VOP_INFO_FROM_CODEC_10BIT (BIT6) //10 bits enable 286 #define VOP_INFO_FROM_CODEC_DS_IDX (BIT7) //dynamic scaling index 287 288 #define VOP_EVD_10B_EN (MVOP_REG_BASE + 0x73) 289 #define VOP_INT_TYPE (MVOP_REG_BASE + 0x73) 290 #define VOP_EVD_INT_SEP (BIT0) 291 #define VOP_EVD_10B_Y_EN (BIT1) //Enable EVD Y 10 bits mode 292 #define VOP_EVD_10B_UV_EN (BIT2) //Enable EVD UV 10 bits mode 293 294 #define VOP_NOT_WAIT_READ_DATA (MVOP_REG_BASE + 0x72) 295 #define VOP_NOT_WAIT_RDLAT (BIT0|BIT1|BIT2) 296 297 #define VOP_MIU_SEL_LSB (MVOP_REG_BASE + 0x75) 298 #define VOP_LSB_BUF0_MIU_SEL (BIT4|BIT5) // LSB Y miu select: miu0~3 = 0x0~0x3 299 #define VOP_LSB_BUF1_MIU_SEL (BIT6|BIT7) // LSB UV miu select: miu0~3 = 0x0~0x3 300 301 #define VOP_MIRROR_CFG (MVOP_REG_BASE + 0x76) 302 #define VOP_MIRROR_CFG_VEN (BIT0) //vertical mirror enable 303 #define VOP_MIRROR_CFG_HEN (BIT1) //horizontal mirror enable 304 #define VOP_FIELD_FROM_ADDR (BIT3) //decide top or bot by diu addr 305 #define VOP_HW_FLD_BASE (BIT5) //Hardware calculate field jump base address 306 #define VOP_MASK_BASE_LSB (BIT7) //mask LSB of base address from Codec (always get top field base address) 307 #define VOP_MIRROR_CFG_ENABLE (BIT3 | BIT4 | BIT5 | BIT6 | BIT7) 308 309 #define VOP_MIRROR_CFG_HI (MVOP_REG_BASE + 0x77) 310 #define VOP_REF_SELF_FLD (BIT1) //source field flag set by internal timing generator 311 312 #define VOP_MULTI_WIN_CFG0 (MVOP_REG_BASE + 0x78) 313 #define VOP_LR_BUF_MODE (BIT0) //3D L/R dual buffer mode 314 #define VOP_P2I_MODE (BIT1) //progressive input, interlace output 315 //to SC vsync is twice of to MVD vsync 316 #define VOP_LR_LA_OUT (BIT2) //3D L/R dual buffer line alternative output 317 #define VOP_LR_LA2SBS_OUT (BIT3) //3D L/R dual buffer line alternative read, side-by-side output 318 #define VOP_LR_DIFF_SIZE (BIT7) //3D L/R dual buffer with difference size 319 320 #define VOP_RGB_FMT (MVOP_REG_BASE + 0x79) 321 #define VOP_RGB_FMT_565 (BIT0) //RGB 565 322 #define VOP_RGB_FMT_888 (BIT1) //RGB 888 323 #define VOP_RGB_FMT_SEL (BIT0 | BIT1) //RGB format selection 324 325 #define VOP_REG_DUMMY (MVOP_REG_BASE + 0x7B) 326 #define VOP_32x32_WB (BIT6) //32x32 from vdec: Reg_evd_en = 0 + reg_diu_sel = 1 327 #define VOP_420_BW_SAVE (BIT7) //420 bw saving mode (MVOP_REG_BASE + 0x7B) 328 329 #define VOP_REG_STRIP_ALIGN (MVOP_REG_BASE + 0x7E) 330 #define VOP_REG_WEIGHT_CTRL (MVOP_REG_BASE + 0x7E) 331 #define VOP_REG_FRAME_RST (MVOP_REG_BASE + 0x7E) //BIT15 332 #define VOP_REG_CSC_EN (MVOP_REG_BASE + 0x7E) //BIT15 333 334 #define VOP_REG_CROP_HSTART (MVOP_REG_BASE + 0x80) 335 #define VOP_REG_CROP_VSTART (MVOP_REG_BASE + 0x82) 336 #define VOP_REG_CROP_HSIZE (MVOP_REG_BASE + 0x84) 337 #define VOP_REG_CROP_VSIZE (MVOP_REG_BASE + 0x86) 338 339 #define VOP_REG_MASK (MVOP_REG_BASE + 0x8E) 340 #define VOP_LSB_REQ_MASK (BIT0 | BIT1) //RGB format selection 341 342 #define VOP_LSB_YSTR0_L (MVOP_REG_BASE + 0x94) 343 #define VOP_LSB_YSTR0_H (MVOP_REG_BASE + 0x96) 344 #define VOP_LSB_UVSTR0_L (MVOP_REG_BASE + 0x98) 345 #define VOP_LSB_UVSTR0_H (MVOP_REG_BASE + 0x9A) 346 #define VOP_LSB_YSTR1_L (MVOP_REG_BASE + 0x9C) 347 #define VOP_LSB_YSTR1_H (MVOP_REG_BASE + 0x9E) 348 #define VOP_LSB_UVSTR1_L (MVOP_REG_BASE + 0xA0) 349 #define VOP_LSB_UVSTR1_H (MVOP_REG_BASE + 0xA2) 350 351 #define VOP_DC_STRIP_LSB (MVOP_REG_BASE + 0xA4) 352 353 354 #define VOP_REG_MFDEC_0_L (MVOP_REG_BASE + 0xA8) 355 #define VOP_MFDEC_EN BIT0 356 #define VOP_MF0_BURST (BIT4 | BIT5) 357 #define VOP_MF1_BURST (BIT6 | BIT7) 358 359 360 #define VOP_REG_BW_SAVE (MVOP_REG_BASE + 0xC0) 361 #define VOP_420_BW_SAVE_EX BIT0 362 363 //------------------------------------------------------------------------------ 364 // chip top 365 //------------------------------------------------------------------------------ 366 #define REG_CKG_DC0 (CHIP_REG_BASE + 0x98) 367 #define CKG_DC0_GATED BIT0 368 #define CKG_DC0_INVERT BIT1 369 #define CKG_DC0_MASK (BIT3 | BIT2) //select clk src 370 #define CKG_DC0_SYNCHRONOUS (0 << 2) 371 #define CKG_DC0_FREERUN (1 << 2) 372 #define CKG_DC0_160MHZ (2 << 2) 373 #define CKG_DC0_144MHZ (3 << 2) 374 375 #define REG_CKG_SUB_DC0 (CHIP_REG_BASE + 0x9A) 376 #define CKG_SUB_DC0_GATED BIT0 377 #define CKG_SUB_DC0_INVERT BIT1 378 #define CKG_SUB_DC0_MASK (BIT3 | BIT2) //select clk src 379 #define CKG_SUB_DC0_SYNCHRONOUS (0 << 2) 380 #define CKG_SUB_DC0_FREERUN (1 << 2) 381 #define CKG_SUB_DC0_160MHZ (2 << 2) 382 #define CKG_SUB_DC0_144MHZ (3 << 2) 383 384 #define REG_CKG_DC_SRAM (CHIP_REG_BASE + 0x9E) 385 #define CKG_DC0_SRAM BIT0 386 #define CKG_DC1_SRAM BIT4 387 388 // For check stc cw 389 #define REG_STC0_CW_L (CHIP_REG_BASE + 0x0C) 390 #define REG_STC0_CW_H (CHIP_REG_BASE + 0x0E) 391 #define REG_STC1_CW_L (CHIP_REG_BASE + 0xE2) 392 #define REG_STC1_CW_H (CHIP_REG_BASE + 0xE4) 393 394 395 #define REG_UPDATE_DC0_CW (CHIP_REG_BASE + 0x0A) 396 #define UPDATE_DC0_FREERUN_CW BIT3 397 #define UPDATE_DC0_SYNC_CW BIT4 398 399 //#define REG_UPDATE_DC0_SYNC_CW (CHIP_REG_BASE + 0x0A) 400 #define REG_DC0_NUM (CHIP_REG_BASE + 0x14) 401 #define REG_DC0_DEN (CHIP_REG_BASE + 0x16) 402 #define REG_DC0_FREERUN_CW_L (CHIP_REG_BASE + 0x10) 403 #define REG_DC0_FREERUN_CW_H (CHIP_REG_BASE + 0x12) 404 405 //For sub mvop 406 #define REG_UPDATE_DC1_CW (CHIP_REG_BASE + 0xE0) 407 #define UPDATE_DC1_FREERUN_CW BIT3 408 #define UPDATE_DC1_SYNC_CW BIT4 409 #define REG_DC1_FREERUN_CW_L (CHIP_REG_BASE + 0xE6) 410 #define REG_DC1_FREERUN_CW_H (CHIP_REG_BASE + 0xE8) 411 #define REG_DC1_NUM (CHIP_REG_BASE + 0xEA) 412 #define REG_DC1_DEN (CHIP_REG_BASE + 0xEC) 413 414 //------------------------------------------------------------------------------ 415 // SC_FE 416 //------------------------------------------------------------------------------ 417 #define REG_MIU_SEL_FROM_IP (SC_FE_REG_BASE + 0x22) 418 #define MVOP_MIU_IP_SEL BIT2 419 420 #endif // _REG_VOP_H_ 421 422