1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. 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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 #ifndef _REG_VOP_H_ 96 #define _REG_VOP_H_ 97 98 99 //------------------------------------------------------------------------------------------------- 100 // Hardware Capability 101 //------------------------------------------------------------------------------------------------- 102 103 104 //------------------------------------------------------------------------------------------------- 105 // Macro and Define 106 //------------------------------------------------------------------------------------------------- 107 108 109 //------------------------------------------------------------------------------ 110 // Base Address 111 //------------------------------------------------------------------------------ 112 #define MVOP_REG_BASE 0x00001400 // 0x1400 - 0x14FF 113 #define MVOP_SUB_REG_BASE 0x1300 // 0x1300 - 0x13FF 114 #define CHIP_REG_BASE 0x0B00 //chiptop CLKGEN0 115 #define SC_FE_REG_BASE 0x00037F00 //SC_FE 116 #define CHIP_REG_1_BASE 0x00003300 // CLKGEN1 117 118 119 120 //------------------------------------------------------------------------------ 121 // MVOP Reg 122 //------------------------------------------------------------------------------ 123 #define VOP_FRAME_VCOUNT (MVOP_REG_BASE + 0x00) 124 #define VOP_FRAME_HCOUNT (MVOP_REG_BASE + 0x02) 125 #define VOP_VB0_STR (MVOP_REG_BASE + 0x04) 126 #define VOP_VB0_END (MVOP_REG_BASE + 0x06) 127 #define VOP_VB1_STR (MVOP_REG_BASE + 0x08) 128 #define VOP_VB1_END (MVOP_REG_BASE + 0x0A) 129 #define VOP_TF_STR (MVOP_REG_BASE + 0x0C) 130 #define VOP_BF_STR (MVOP_REG_BASE + 0x0E) 131 #define VOP_HACT_STR (MVOP_REG_BASE + 0x10) 132 #define VOP_IMG_HSTR (MVOP_REG_BASE + 0x12) 133 #define VOP_IMG_VSTR0 (MVOP_REG_BASE + 0x14) 134 #define VOP_IMG_VSTR1 (MVOP_REG_BASE + 0x16) 135 #define VOP_TF_VS (MVOP_REG_BASE + 0x18) 136 #define VOP_BF_VS (MVOP_REG_BASE + 0x1A) 137 138 139 ///TOP field Vsync start line number to MVD 140 #define VOP_TF_VS_MVD (MVOP_REG_BASE + 0x1C) //u3 new 141 ///Bottom field Vsync start line number to MVD 142 #define VOP_BF_VS_MVD (MVOP_REG_BASE + 0x1E) //u3 new 143 144 #define VOP_FSYNC_EN BIT4 //frame sync enable 145 #define VOP_CTRL0 (MVOP_REG_BASE + 0x22) 146 147 #define VOP_FLIP_UV BIT0 148 #define VOP_FLIP_YC BIT1 149 #define VOP_FLD_INV BIT2 150 #define VOP_OFLD_INV BIT4 151 #define VOP_CCIR_MD BIT5 152 #define VOP_MVD_VS_MD BIT6 //u3 new 0: Original mode;1: Use new vsync (tf_vs_mvd, bf_vs_mvd) 153 #define VOP_MVD_VS_SEL BIT7 154 #define VOP_CTRL1 (MVOP_REG_BASE + 0x23) 155 156 #define VOP_TST_IMG (MVOP_REG_BASE + 0x24) 157 158 #define VOP_U_PAT (MVOP_REG_BASE + 0x26) 159 160 #define VOP_DMA_THD (BIT0|BIT1|BIT2|BIT3|BIT4) 161 //DMA FIFO threshold 162 //= reg_dma_thd x 2 (reg_miu128b=1) 163 //= reg_dma_thd x 4 (reg_miu128b=0) 164 #define VOP_BURST_ST_SEL BIT7 165 //Timing to calculate burst length (only valid when reg_burst_ext = all) 166 //0: at mi2dc_rdy; 1: at dc2mi_rdy 167 #define VOP_DMA0 (MVOP_REG_BASE + 0x28) //t3 new 168 169 #define VOP_BURST_EXT (BIT0|BIT1|BIT2) 170 //DMA burst length 171 //0: 4 (reg_miu128b=1), 8 (reg_miu128b=0) 172 //1: 8 (reg_miu128b=1), 16 (reg_miu128b=0) 173 //2: 16 (reg_miu128b=1), 32 (reg_miu128b=0) 174 //3: 24 (reg_miu128b=1), 48 (reg_miu128b=0) 175 //4: 32 (reg_miu128b=1), 64 (reg_miu128b=0) 176 //5: 48 (reg_miu128b=1), 96 (reg_miu128b=0) 177 //6: 64 (reg_miu128b=1), 128 (reg_miu128b=0) 178 //7: all 179 #define VOP_HI_TSH (BIT3|BIT4|BIT5|BIT6) //DMA High priority threshold 180 //(assert high priority if data count less then reg_hi_tsh x 8) 181 #define VOP_FORCE_HIGH BIT7 //Force DMA High priority 182 #define VOP_DMA1 (MVOP_REG_BASE + 0x29) //t3 new 183 184 #define VOP_LSB_DMA0 (MVOP_REG_BASE + 0x2C) 185 #define VOP_LSB_DMA1 (MVOP_REG_BASE + 0x2D) 186 #define VOP_SYNC_2_DC_TIMING BIT7 187 188 #define VOP_DC_STRIP_H (MVOP_REG_BASE + 0x30) 189 #define VOP_SRAM_SD_MASK BIT3 190 #define MFDEC_SRAM_SD_MASK BIT4 191 192 #define VOP_INT_MASK (MVOP_REG_BASE + 0x3E) 193 #define VOP_MPG_JPG_SWITCH (MVOP_REG_BASE + 0x40) 194 #define VOP_DRAM_RD_MODE BIT5 195 #define VOP_DC_STRIP (MVOP_REG_BASE + 0x41) 196 #define VOP_JPG_YSTR0_L (MVOP_REG_BASE + 0x42) 197 #define VOP_JPG_YSTR0_H (MVOP_REG_BASE + 0x44) 198 #define VOP_JPG_UVSTR0_L (MVOP_REG_BASE + 0x46) 199 #define VOP_JPG_UVSTR0_H (MVOP_REG_BASE + 0x48) 200 #define VOP_YUV_STR_HIBITS (BIT4 | BIT3 | BIT2 |BIT1 | BIT0) //Bits(28:24) 201 202 #define VOP_JPG_HSIZE (MVOP_REG_BASE + 0x4A) 203 #define VOP_JPG_VSIZE (MVOP_REG_BASE + 0x4C) 204 205 #define VOP_LOAD_REG BIT0 //load new value into active registers 0x20-0x26 206 #define VOP_TILE_FORMAT BIT1 //0: 8x32, 1: 16x32 207 #define VOP_BUF_DUAL BIT2 208 #define VOP_FORCELOAD_REG BIT4 //force load registers 209 #define VOP_REG_WR (MVOP_REG_BASE + 0x4E) 210 211 #define VOP_MVD_EN BIT0 //t8 new 212 #define VOP_H264_PUREY BIT1 213 //#define VOP_RVD_EN BIT2 //a3: removed 214 #define VOP_HVD_EN BIT3 215 #define VOP_FORCE_SC_RDY BIT4 //u3 new: force sc2mvop_rdy = 1 216 #define VOP_DEBUG_SEL (BIT5 | BIT6 | BIT7) //u3 new: MVOP debug out select 217 #define VOP_INPUT_SWITCH0 (MVOP_REG_BASE + 0x50) 218 #define VOP_TILE_32x32 BIT5 219 #define VOP_R2_WISHBONE BIT6 220 #define EVD_ENABLE BIT7 221 222 #define VOP_INPUT_SWITCH1 (MVOP_REG_BASE + 0x51) 223 224 #define VOP_RAMAP_LUMA_VAL 0x1f 225 #define VOP_RAMAP_LUMA_EN BIT7 226 #define VOP_RAMAP_LUMA (MVOP_REG_BASE + 0x52) 227 //u3 new: Luma range mapping for VC1 (value = 8~16) 228 229 #define VOP_RAMAP_CHROMA_VAL 0x1f 230 #define VOP_RAMAP_CHROMA_EN BIT7 231 #define VOP_RAMAP_CHROMA (MVOP_REG_BASE + 0x53) 232 //u3 new: Chroma range mapping for VC1 (value = 8~16) 233 234 // [T3 new 235 #define VOP_DEBUG_2A (MVOP_REG_BASE + 0x54) //2-byte 236 #define VOP_DEBUG_2B (MVOP_REG_BASE + 0x56) 237 #define VOP_DEBUG_2C (MVOP_REG_BASE + 0x58) 238 #define VOP_DEBUG_2D (MVOP_REG_BASE + 0x5A) 239 #define VOP_DEBUG_2E (MVOP_REG_BASE + 0x5C) 240 241 #define VOP_UF BIT0 //buf underflow 242 #define VOP_OF BIT1 //buf overflow 243 #define VOP_DEBUG_2F_L (MVOP_REG_BASE + 0x5E) 244 245 #define VOP_BIST_FAIL BIT0 //YUV fifo bist fail 246 #define VOP_RIU_DEBUG_SEL (BIT6|BIT7) //RIU debug register select 247 #define VOP_DEBUG_2F_H (MVOP_REG_BASE + 0x5F) 248 // ] 249 250 #define VOP_UV_SHIFT (MVOP_REG_BASE + 0x60) 251 252 #define VOP_GCLK_MIU_ON BIT2 //clk_miu use 0: free-run clock; 1: gated clock 253 #define VOP_GCLK_VCLK_ON BIT3 //clk_dc0 use 0: free-run clock; 1: gated clock 254 #define VOP_GCLK (MVOP_REG_BASE + 0x60) //u3 new 255 256 #define VOP_MIU_IF (MVOP_REG_BASE + 0x60) 257 #define VOP_MIU_128BIT BIT4 //MIU bus use 0: 64bit 1:128bit 258 #define VOP_MIU_128B_I64 BIT5 259 #define VOP_MIU_REQ_DIS BIT6 260 261 #define VOP_MIU_BUS (MVOP_REG_BASE + 0x60) //t3 new 262 263 #define VOP_MIU_SEL (MVOP_REG_BASE + 0x61) //kaiser new 264 #define VOP_MSB_MIU_DIFF BIT0 265 #define VOP_LSB_MIU_DIFF BIT1 266 #define VOP_MSB_BUF0_MIU_SEL (BIT4|BIT5) // Y miu select: miu0~3 = 0x0~0x3 267 #define VOP_MSB_BUF1_MIU_SEL (BIT6|BIT7) // UV miu select: miu0~3 = 0x0~0x3 268 269 #define VOP_JPG_YSTR1_L (MVOP_REG_BASE + 0x62) 270 #define VOP_JPG_YSTR1_H (MVOP_REG_BASE + 0x64) 271 #define VOP_JPG_UVSTR1_L (MVOP_REG_BASE + 0x66) 272 #define VOP_JPG_UVSTR1_H (MVOP_REG_BASE + 0x68) 273 274 #define VOP_SYNC_FRAME_V (MVOP_REG_BASE + 0x6A) 275 #define VOP_SYNC_FRAME_H (MVOP_REG_BASE + 0x6C) 276 277 #define VOP_INFO_FROM_CODEC_L (MVOP_REG_BASE + 0x70) 278 #define VOP_INFO_FROM_CODEC_BASE_ADDR (BIT0) //base address 279 #define VOP_INFO_FROM_CODEC_PITCH (BIT1) //pitch 280 #define VOP_INFO_FROM_CODEC_SIZE (BIT2) //size 281 #define VOP_INFO_FROM_CODEC_PROG_SEQ (BIT3) //progressive sequence 282 #define VOP_INFO_FROM_CODEC_FIELD (BIT4) //field 283 #define VOP_INFO_FROM_CODEC_RANGE_MAP (BIT5) //range map 284 #define VOP_INFO_FROM_CODEC_COMP_MODE (BIT6) //compression mode 285 #define VOP_INFO_FROM_CODEC_422_FMT (BIT7) //422 format 286 287 #define VOP_INFO_FROM_CODEC_H (MVOP_REG_BASE + 0x71) 288 #define VOP_INFO_FROM_CODEC_DUAL_BUFF (BIT0) //dual buffer flag 289 #define VOP_INFO_FROM_CODEC_BPIC_REDUCT (BIT1) //bpic reduction 290 #define VOP_INFO_FROM_CODEC_MIU_BUF0_SEL (BIT4) //MSB miu select 291 #define VOP_INFO_FROM_CODEC_MIU_BUF1_SEL (BIT5) //LSB miu select 292 #define VOP_INFO_FROM_CODEC_10BIT (BIT6) //10 bits enable 293 #define VOP_INFO_FROM_CODEC_DS_IDX (BIT7) //dynamic scaling index 294 295 #define VOP_EVD_10B_EN (MVOP_REG_BASE + 0x73) 296 #define VOP_INT_TYPE (MVOP_REG_BASE + 0x73) 297 #define VOP_EVD_INT_SEP (BIT0) 298 #define VOP_EVD_10B_Y_EN (BIT1) //Enable EVD Y 10 bits mode 299 #define VOP_EVD_10B_UV_EN (BIT2) //Enable EVD UV 10 bits mode 300 301 #define VOP_NOT_WAIT_READ_DATA (MVOP_REG_BASE + 0x72) 302 #define VOP_NOT_WAIT_RDLAT (BIT0|BIT1|BIT2) 303 304 #define VOP_MIU_SEL_LSB (MVOP_REG_BASE + 0x75) 305 #define VOP_LSB_BUF0_MIU_SEL (BIT4|BIT5) // LSB Y miu select: miu0~3 = 0x0~0x3 306 #define VOP_LSB_BUF1_MIU_SEL (BIT6|BIT7) // LSB UV miu select: miu0~3 = 0x0~0x3 307 308 #define VOP_MIRROR_CFG (MVOP_REG_BASE + 0x76) 309 #define VOP_MIRROR_CFG_VEN (BIT0) //vertical mirror enable 310 #define VOP_MIRROR_CFG_HEN (BIT1) //horizontal mirror enable 311 #define VOP_FIELD_FROM_ADDR (BIT3) //decide top or bot by diu addr 312 #define VOP_HW_FLD_BASE (BIT5) //Hardware calculate field jump base address 313 #define VOP_MASK_BASE_LSB (BIT7) //mask LSB of base address from Codec (always get top field base address) 314 #define VOP_MIRROR_CFG_ENABLE (BIT3 | BIT4 | BIT5 | BIT6 | BIT7) 315 316 #define VOP_MIRROR_CFG_HI (MVOP_REG_BASE + 0x77) 317 #define VOP_DC2MVD_FLD_SEL (BIT0) //from maxim, able to control field timing. 318 #define VOP_REF_SELF_FLD (BIT1) //source field flag set by internal timing generator 319 #define VOP_HK_MASK (BIT4) // HSK show back ground as vdec not ready 320 321 #define VOP_MULTI_WIN_CFG0 (MVOP_REG_BASE + 0x78) 322 #define VOP_LR_BUF_MODE (BIT0) //3D L/R dual buffer mode 323 #define VOP_P2I_MODE (BIT1) //progressive input, interlace output 324 //to SC vsync is twice of to MVD vsync 325 #define VOP_LR_LA_OUT (BIT2) //3D L/R dual buffer line alternative output 326 #define VOP_LR_LA2SBS_OUT (BIT3) //3D L/R dual buffer line alternative read, side-by-side output 327 #define VOP_LR_DIFF_SIZE (BIT7) //3D L/R dual buffer with difference size 328 329 #define VOP_RGB_FMT (MVOP_REG_BASE + 0x79) 330 #define VOP_RGB_FMT_565 (BIT0) //RGB 565 331 #define VOP_RGB_FMT_888 (BIT1) //RGB 888 332 #define VOP_RGB_FMT_SEL (BIT0 | BIT1) //RGB format selection 333 334 #define VOP_REG_DUMMY (MVOP_REG_BASE + 0x7B) 335 #define VOP_32x32_WB (BIT6) //32x32 from vdec: Reg_evd_en = 0 + reg_diu_sel = 1 336 #define VOP_420_BW_SAVE (BIT7) //420 bw saving mode 337 338 #define VOP_REG_HS_OUTPUT (MVOP_REG_BASE + 0x7C) 339 #define VOP_HS_MODE (BIT0) 340 341 #define VOP_REG_STRIP_ALIGN (MVOP_REG_BASE + 0x7E) 342 #define VOP_REG_WEIGHT_CTRL (MVOP_REG_BASE + 0x7E) 343 #define VOP_REG_CSC_EN (MVOP_REG_BASE + 0x7E) //BIT15 344 #define VOP_REG_YC422_EN_H (MVOP_REG_BASE + 0x7F) 345 #define VOP_FRAME_RST (BIT7) 346 347 #define VOP_REG_CROP_HSTART (MVOP_REG_BASE + 0x80) 348 #define VOP_REG_CROP_VSTART (MVOP_REG_BASE + 0x82) 349 #define VOP_REG_CROP_HSIZE (MVOP_REG_BASE + 0x84) 350 #define VOP_REG_CROP_VSIZE (MVOP_REG_BASE + 0x86) 351 352 #define VOP_REG_MASK (MVOP_REG_BASE + 0x8E) 353 #define VOP_LSB_REQ_MASK (BIT0 | BIT1) //RGB format selection 354 355 #define VOP_LSB_YSTR0_L (MVOP_REG_BASE + 0x94) 356 #define VOP_LSB_YSTR0_H (MVOP_REG_BASE + 0x96) 357 #define VOP_LSB_UVSTR0_L (MVOP_REG_BASE + 0x98) 358 #define VOP_LSB_UVSTR0_H (MVOP_REG_BASE + 0x9A) 359 #define VOP_LSB_YSTR1_L (MVOP_REG_BASE + 0x9C) 360 #define VOP_LSB_YSTR1_H (MVOP_REG_BASE + 0x9E) 361 #define VOP_LSB_UVSTR1_L (MVOP_REG_BASE + 0xA0) 362 #define VOP_LSB_UVSTR1_H (MVOP_REG_BASE + 0xA2) 363 364 #define VOP_DC_STRIP_LSB (MVOP_REG_BASE + 0xA4) 365 366 #define VOP_REG_4K2K_2P (MVOP_REG_BASE + 0xA6) 367 #define VOP_4K2K_2P BIT1 368 #define VOP_TRIG_REFER_VB_END BIT3 369 370 #define VOP_REG_MFDEC_0_L (MVOP_REG_BASE + 0xA8) 371 #define VOP_MFDEC_EN BIT0 372 #define VOP_MFDEC_SEL BIT1 373 #define VOP_MF0_BURST (BIT4 | BIT5) 374 #define VOP_MF1_BURST (BIT6 | BIT7) 375 376 #define VOP_REG_MFDEC_2_L (MVOP_REG_BASE + 0xAC) 377 #define VOP_MF_FROM_WB BIT6 378 379 #define VOP_REG_DUMMY_5D_L (MVOP_REG_BASE + 0xBA) 380 #define XC_RESET_HCOUNT BIT0 381 382 #define VOP_REG_BW_SAVE (MVOP_REG_BASE + 0xC0) 383 #define VOP_420_BW_SAVE_EX BIT0 384 385 #define VOP_REG_MRQ (MVOP_REG_BASE + 0xC9) 386 #define VOP_LST_CTRL_DCTOP (BIT3 | BIT4 | BIT5) 387 #define VOP_MRQ_EN BIT6 388 389 #define VOP_REG_BW_THD_L (MVOP_REG_BASE + 0xCC) 390 #define VOP_REG_BW_THD_H (MVOP_REG_BASE + 0xCD) 391 #define REG_MVD_FLD_SEL BIT7 392 393 #define VOP_TF_STR_MVD (MVOP_REG_BASE + 0xCE) 394 #define VOP_BF_STR_MVD (MVOP_REG_BASE + 0xD0) 395 396 //------------------------------------------------------------------------------ 397 // chip top 398 //------------------------------------------------------------------------------ 399 #define REG_CKG_DC0 (CHIP_REG_BASE + 0x98) 400 #define CKG_DC0_GATED BIT0 401 #define CKG_DC0_INVERT BIT1 402 #define CKG_DC0_MASK (BIT4 | BIT3 | BIT2) //select clk src 403 #define CKG_DC0_SYNCHRONOUS (0 << 2) 404 #define CKG_DC0_FREERUN (1 << 2) 405 #define CKG_DC0_160MHZ (2 << 2) 406 #define CKG_DC0_144MHZ (3 << 2) 407 #define CKG_DC0_320MHZ (4 << 2) 408 409 #define REG_CKG_SUB_DC0 (CHIP_REG_BASE + 0x9A) 410 #define CKG_SUB_DC0_GATED BIT0 411 #define CKG_SUB_DC0_INVERT BIT1 412 #define CKG_SUB_DC0_MASK (BIT4 | BIT3 | BIT2) //select clk src 413 #define CKG_SUB_DC0_SYNCHRONOUS (0 << 2) 414 #define CKG_SUB_DC0_FREERUN (1 << 2) 415 #define CKG_SUB_DC0_160MHZ (2 << 2) 416 #define CKG_SUB_DC0_144MHZ (3 << 2) 417 #define CKG_SUB_DC0_320MHZ (4 << 2) 418 419 #define REG_CKG_DC_SRAM (CHIP_REG_BASE + 0x9E) 420 #define CKG_DC0_SRAM BIT0 421 #define CKG_DC1_SRAM BIT4 422 423 // For check stc cw 424 #define REG_STC_CW_SLE_L (CHIP_REG_BASE + 0x08) //reg_stc0_cw_sel 425 #define REG_STC_CW_SLE_H (CHIP_REG_BASE + 0x09) //reg_stc1_cw_sel 426 #define REG_STC0_CW_L (CHIP_REG_BASE + 0x0A) 427 #define REG_STC0_CW_H (CHIP_REG_BASE + 0x0C) 428 #define REG_STC1_CW_L (CHIP_REG_BASE + 0x0E) 429 #define REG_STC1_CW_H (CHIP_REG_BASE + 0x10) 430 #define REG_TSP_CLK (CHIP_REG_BASE + 0x54) //reg_ckg_tsp 431 #define REG_CLK_SYN_STC (CHIP_REG_BASE + 0x56) //reg_ckg_stc0[0-2] stc1[4-6] 432 433 434 //For main mvop 435 #define REG_UPDATE_DC0_CW (CHIP_REG_BASE + 0xE0) 436 #define UPDATE_DC0_FREERUN_CW BIT0 437 #define UPDATE_DC0_SYNC_CW BIT1 438 #define REG_DC0_FREERUN_CW_L (CHIP_REG_BASE + 0xE4) 439 #define REG_DC0_FREERUN_CW_H (CHIP_REG_BASE + 0xE6) 440 #define REG_DC0_NUM (CHIP_REG_BASE + 0xE8) 441 #define REG_DC0_DEN (CHIP_REG_BASE + 0xEA) 442 443 //For sub mvop 444 #define REG_UPDATE_DC1_CW (CHIP_REG_BASE + 0xE1) 445 #define UPDATE_DC1_FREERUN_CW BIT0 446 #define UPDATE_DC1_SYNC_CW BIT1 447 #define REG_DC1_FREERUN_CW_L (CHIP_REG_BASE + 0xEC) 448 #define REG_DC1_FREERUN_CW_H (CHIP_REG_BASE + 0xEE) 449 #define REG_DC1_NUM (CHIP_REG_BASE + 0xF0) 450 #define REG_DC1_DEN (CHIP_REG_BASE + 0xF2) 451 452 //------------------------------------------------------------------------------ 453 // SC_FE 454 //------------------------------------------------------------------------------ 455 #define REG_MIU_SEL_FROM_IP (SC_FE_REG_BASE + 0x22) 456 #define MVOP_MIU_IP_SEL BIT2 457 #define MFDEC0_MIU_IP_SEL BIT3 458 #define MFDEC1_MIU_IP_SEL BIT4 459 460 //------------------------------------------------------------------------------ 461 // CHIP_REG_1_BASE 462 //------------------------------------------------------------------------------ 463 #define REG_CKG_FBDEC (CHIP_REG_1_BASE + 0x4A) 464 #define CKG_FBDEC_GATED BIT0 465 #define CKG_FBDEC_MASK (BIT3 | BIT2 | BIT1) 466 467 #endif // _REG_VOP_H_ 468 469