Home
last modified time | relevance | path

Searched refs:sw54 (Results 1 – 11 of 11) sorted by relevance

/rockchip-linux_mpp/mpp/hal/vpu/m2vd/
H A Dhal_m2vd_vdpu2.c162 p_regs->sw54.dec_strswap32_e = 1; //change in hal_m2vd_vdpu2_init_hwcfg()
163 p_regs->sw54.dec_strendian_e = DEC_LITTLE_ENDIAN; in hal_m2vd_vdpu2_init_hwcfg()
164 p_regs->sw54.dec_inswap32_e = 1; //change in hal_m2vd_vdpu2_init_hwcfg()
165 p_regs->sw54.dec_outswap32_e = 1; //change in hal_m2vd_vdpu2_init_hwcfg()
169 p_regs->sw54.dec_in_endian = DEC_LITTLE_ENDIAN; //change in hal_m2vd_vdpu2_init_hwcfg()
170 p_regs->sw54.dec_out_endian = DEC_LITTLE_ENDIAN; in hal_m2vd_vdpu2_init_hwcfg()
H A Dhal_m2vd_vdpu2_reg.h69 } sw54; member
/rockchip-linux_mpp/mpp/hal/rkdec/avsd/
H A Dhal_avsd_vdpu2.c35 p_regs->sw54.dec_out_endian = 1; in set_defalut_parameters()
36 p_regs->sw54.dec_in_endian = 0; in set_defalut_parameters()
37 p_regs->sw54.dec_strendian_e = 1; in set_defalut_parameters()
46 p_regs->sw54.dec_out_wordsp = 1; in set_defalut_parameters()
47 p_regs->sw54.dec_in_wordsp = 1; in set_defalut_parameters()
48 p_regs->sw54.dec_strm_wordsp = 1; in set_defalut_parameters()
H A Dhal_avsd_vdpu2_reg.h60 } sw54; member
H A Dhal_avsd_plus_reg.h261 RK_U32 sw54; member
/rockchip-linux_mpp/mpp/hal/rkdec/h264d/
H A Dhal_h264d_vdpu2.c48 p_reg->sw54.dec_out_endian = 1; //!< little endian in set_device_regs()
49 p_reg->sw54.dec_in_endian = 0; //!< big endian in set_device_regs()
50 p_reg->sw54.dec_strendian_e = 1; //!< little endian in set_device_regs()
58 p_reg->sw54.dec_out_wordsp = 1;//!< little endian in set_device_regs()
59 p_reg->sw54.dec_in_wordsp = 1;//!< little endian in set_device_regs()
60 p_reg->sw54.dec_strm_wordsp = 1;//!< little endian in set_device_regs()
H A Dhal_h264d_vdpu2_reg.h64 } sw54; member
/rockchip-linux_mpp/mpp/hal/vpu/vp8e/
H A Dhal_vp8e_vepu1_reg.h272 } sw54; member
H A Dhal_vp8e_vepu2_reg.h197 } sw54; member
H A Dhal_vp8e_vepu1_v2.c172 regs->sw54.rgb_coeff_c = hw_cfg->rgb_coeff_c; in vp8e_vpu_frame_start()
173 regs->sw54.rgb_coeff_e = hw_cfg->rgb_coeff_e; in vp8e_vpu_frame_start()
H A Dhal_vp8e_vepu2_v2.c50 regs->sw54.val = 0x1000; in vp8e_vpu_frame_start()