Home
last modified time | relevance | path

Searched refs:reg_out (Results 1 – 15 of 15) sorted by relevance

/rockchip-linux_mpp/mpp/hal/rkenc/jpege/
H A Dhal_jpege_vepu540c.c45 void *reg_out; member
83 ctx->reg_out = mpp_calloc(JpegV540cStatus, 1); in hal_jpege_v540c_init()
114 MPP_FREE(ctx->reg_out); in hal_jpege_v540c_deinit()
241 JpegV540cStatus *reg_out = ctx->reg_out; in hal_jpege_v540c_start() local
282 cfg1.reg = &reg_out->hw_status; in hal_jpege_v540c_start()
292 cfg1.reg = &reg_out->st; in hal_jpege_v540c_start()
314 JpegV540cStatus *elem = (JpegV540cStatus *)ctx->reg_out; in hal_jpege_vepu540c_status_check()
342 JpegV540cStatus *elem = (JpegV540cStatus *)ctx->reg_out; in hal_jpege_v540c_wait()
H A Dhal_jpege_vepu511.c34 void *reg_out; member
72 ctx->reg_out = mpp_calloc(JpegV511Status, 1); in hal_jpege_vepu511_init()
102 MPP_FREE(ctx->reg_out); in hal_jpege_vepu511_deinit()
470 JpegV511Status *reg_out = ctx->reg_out; in hal_jpege_vepu511_start() local
521 cfg1.reg = &reg_out->hw_status; in hal_jpege_vepu511_start()
531 cfg1.reg = &reg_out->st; in hal_jpege_vepu511_start()
552 JpegV511Status *elem = (JpegV511Status *)ctx->reg_out; in hal_jpege_vepu511_status_check()
588 JpegV511Status *elem = (JpegV511Status *)ctx->reg_out; in hal_jpege_vepu511_wait()
/rockchip-linux_mpp/mpp/hal/vpu/jpegd/
H A Dhal_jpegd_rkv.c730 JpegRegSet *reg_out = ctx->regs; in hal_jpegd_rkv_wait() local
750 param.regs = (RK_U32 *)reg_out; in hal_jpegd_rkv_wait()
751 if (!reg_out->reg1_int.dec_irq || !reg_out->reg1_int.dec_rdy_sta in hal_jpegd_rkv_wait()
752 || reg_out->reg1_int.dec_bus_sta || reg_out->reg1_int.dec_error_sta in hal_jpegd_rkv_wait()
753 || reg_out->reg1_int.dec_timeout_sta in hal_jpegd_rkv_wait()
754 || reg_out->reg1_int.dec_buf_empty_sta) { in hal_jpegd_rkv_wait()
755 mpp_err("decode result: failed, irq 0x%08x\n", ((RK_U32 *)reg_out)[1]); in hal_jpegd_rkv_wait()
763 mpp_log_f("read regs[%d]=0x%08x\n", i, ((RK_U32*)reg_out)[i]); in hal_jpegd_rkv_wait()
767 jpegd_dbg_hal("decode one frame in cycles: %d\n", reg_out->reg39_perf_working_cnt); in hal_jpegd_rkv_wait()
791 memset(&reg_out->reg1_int, 0, sizeof(RK_U32)); in hal_jpegd_rkv_wait()
H A Dhal_jpegd_vdpu1.c970 JpegRegSet *reg_out = JpegHalCtx->regs; in hal_jpegd_vdpu1_wait() local
988 param.regs = (RK_U32 *)reg_out; in hal_jpegd_vdpu1_wait()
989 if (reg_out->reg1_interrupt.sw_dec_bus_int) { in hal_jpegd_vdpu1_wait()
991 } else if (reg_out->reg1_interrupt.sw_dec_error_int) { in hal_jpegd_vdpu1_wait()
1000 } else if (reg_out->reg1_interrupt.sw_dec_timeout) { in hal_jpegd_vdpu1_wait()
1002 } else if (reg_out->reg1_interrupt.sw_dec_buffer_int) { in hal_jpegd_vdpu1_wait()
1004 } else if (reg_out->reg1_interrupt.sw_dec_irq) { in hal_jpegd_vdpu1_wait()
1040 memset(&reg_out->reg1_interrupt, 0, sizeof(RK_U32)); in hal_jpegd_vdpu1_wait()
H A Dhal_jpegd_vdpu2.c945 JpegRegSet *reg_out = JpegHalCtx->regs; in hal_jpegd_vdpu2_wait() local
963 param.regs = (RK_U32 *)reg_out; in hal_jpegd_vdpu2_wait()
964 if (reg_out->reg55_Interrupt.sw_dec_bus_int) { in hal_jpegd_vdpu2_wait()
966 } else if (reg_out->reg55_Interrupt.sw_dec_error_int) { in hal_jpegd_vdpu2_wait()
968 } else if (reg_out->reg55_Interrupt.sw_dec_timeout) { in hal_jpegd_vdpu2_wait()
970 } else if (reg_out->reg55_Interrupt.sw_dec_buffer_int) { in hal_jpegd_vdpu2_wait()
972 } else if (reg_out->reg55_Interrupt.sw_dec_irq) { in hal_jpegd_vdpu2_wait()
1007 memset(&reg_out->reg55_Interrupt, 0, sizeof(RK_U32)); in hal_jpegd_vdpu2_wait()
/rockchip-linux_mpp/mpp/hal/vpu/m2vd/
H A Dhal_m2vd_vdpu2.c379 M2vdVdpu2Reg* reg_out = (M2vdVdpu2Reg * )ctx->regs; in hal_m2vd_vdpu2_wait() local
389 RK_U32 *p_reg = (RK_U32*)&reg_out; in hal_m2vd_vdpu2_wait()
395 if (reg_out->sw55.dec_error_int | reg_out->sw55.dec_buffer_int) { in hal_m2vd_vdpu2_wait()
401 mpp_log("mpp_device_wait_reg return interrupt:%08x", reg_out->sw55); in hal_m2vd_vdpu2_wait()
H A Dhal_m2vd_vdpu1.c306 M2vdVdpu1Reg_t* reg_out = (M2vdVdpu1Reg_t * )ctx->regs; in hal_m2vd_vdpu1_wait() local
312 if (reg_out->sw01.dec_error_int | reg_out->sw01.dec_buffer_int) { in hal_m2vd_vdpu1_wait()
/rockchip-linux_mpp/mpp/hal/rkenc/h265e/
H A Dhal_h265e_vepu541.c76 void *reg_out; member
604 ctx->reg_out = mpp_calloc(H265eV541IoctlOutputElem, 1); in hal_h265e_v541_init()
663 MPP_FREE(ctx->reg_out); in hal_h265e_v541_deinit()
1667 H265eV541IoctlOutputElem *reg_out = (H265eV541IoctlOutputElem *)ctx->reg_out; in hal_h265e_v540_start() local
1717 cfg1.reg = &reg_out->hw_status; in hal_h265e_v540_start()
1727 cfg1.reg = &reg_out->st_bsl; in hal_h265e_v540_start()
1749 stream_len += reg_out->st_bsl.bs_lgth; in hal_h265e_v540_start()
1750 fb->qp_sum += reg_out->st_sse_qp.qp_sum; in hal_h265e_v540_start()
1751 fb->out_strm_size += reg_out->st_bsl.bs_lgth; in hal_h265e_v540_start()
1752 fb->sse_sum += reg_out->st_sse_l32.sse_l32 + in hal_h265e_v540_start()
[all …]
H A Dhal_h265e_vepu540c.c73 void *reg_out[MAX_TITLE_NUM]; member
513 ctx->reg_out[i] = mpp_calloc(H265eV540cStatusElem, 1); in hal_h265e_v540c_init()
562 MPP_FREE(ctx->reg_out[i]); in hal_h265e_v540c_deinit()
1331 H265eV540cStatusElem *reg_out = (H265eV540cStatusElem *)ctx->reg_out[0]; in hal_h265e_v540c_start() local
1424 cfg1.reg = &reg_out->hw_status; in hal_h265e_v540c_start()
1434 cfg1.reg = &reg_out->st; in hal_h265e_v540c_start()
1460 H265eV540cStatusElem *elem = (H265eV540cStatusElem *)ctx->reg_out[0]; in vepu540c_h265_set_feedback()
1557 H265eV540cStatusElem *elem = (H265eV540cStatusElem *)ctx->reg_out; in hal_h265e_v540c_wait()
H A Dhal_h265e_vepu580.c2163 …PP_RET hal_h265e_v580_send_regs(MppDev dev, H265eV580RegSet *hw_regs, H265eV580StatusElem *reg_out) in hal_h265e_v580_send_regs() argument
2264 cfg1.reg = &reg_out->hw_status; in hal_h265e_v580_send_regs()
2274 cfg1.reg = &reg_out->st; in hal_h265e_v580_send_regs()
2887 H265eV580StatusElem *reg_out = frm->regs_ret[k]; in hal_h265e_v580_start() local
2893 if (!reg_out) { in hal_h265e_v580_start()
2894 reg_out = mpp_malloc(H265eV580StatusElem, 1); in hal_h265e_v580_start()
2895 frm->regs_ret[k] = reg_out; in hal_h265e_v580_start()
2947 hal_h265e_v580_send_regs(ctx->dev, hw_regs, reg_out); in hal_h265e_v580_start()
2965 stream_len += reg_out->st.bs_lgth_l32; in hal_h265e_v580_start()
2966 fb->qp_sum += reg_out->st.qp_sum; in hal_h265e_v580_start()
[all …]
H A Dhal_h265e_vepu510.c103 void *reg_out; member
2084 H265eV510StatusElem *reg_out = (H265eV510StatusElem *)frm->regs_ret; in hal_h265e_v510_start() local
2193 cfg1.reg = &reg_out->hw_status; in hal_h265e_v510_start()
2203 cfg1.reg = &reg_out->st; in hal_h265e_v510_start()
H A Dhal_h265e_vepu511.c102 void *reg_out; member
2245 H265eV511StatusElem *reg_out = (H265eV511StatusElem *)frm->regs_ret; in hal_h265e_vepu511_start() local
2385 cfg1.reg = &reg_out->hw_status; in hal_h265e_vepu511_start()
2395 cfg1.reg = &reg_out->st; in hal_h265e_vepu511_start()
/rockchip-linux_mpp/mpp/hal/rkdec/avs2d/
H A Dhal_avs2d_rkv.c77 RK_U32 reg_out[VDPU34x_TOTAL_REG_CNT]; member
911 memset(reg_ctx->reg_out, 0, sizeof(reg_ctx->reg_out)); in hal_avs2d_rkv_start()
912 rd_cfg.reg = reg_ctx->reg_out; in hal_avs2d_rkv_start()
913 rd_cfg.size = sizeof(reg_ctx->reg_out); in hal_avs2d_rkv_start()
1061 fprintf(fp_reg, "%08x\n", reg_ctx->reg_out[i]); in hal_avs2d_rkv_wait()
H A Dhal_avs2d_vdpu383.c69 RK_U32 reg_out[VDPU34x_TOTAL_REG_CNT]; member
782 memset(reg_ctx->reg_out, 0, sizeof(reg_ctx->reg_out)); in hal_avs2d_vdpu383_start()
783 rd_cfg.reg = reg_ctx->reg_out; in hal_avs2d_vdpu383_start()
784 rd_cfg.size = sizeof(reg_ctx->reg_out); in hal_avs2d_vdpu383_start()
H A Dhal_avs2d_vdpu382.c77 RK_U32 reg_out[VDPU382_TOTAL_REG_CNT]; member
977 memset(reg_ctx->reg_out, 0, sizeof(reg_ctx->reg_out)); in hal_avs2d_vdpu382_start()
978 rd_cfg.reg = reg_ctx->reg_out; in hal_avs2d_vdpu382_start()
979 rd_cfg.size = sizeof(reg_ctx->reg_out); in hal_avs2d_vdpu382_start()
1127 fprintf(fp_reg, "%08x\n", reg_ctx->reg_out[i]); in hal_avs2d_vdpu382_wait()