| /rockchip-linux_mpp/mpp/base/inc/ |
| H A D | mpp_frame_impl.h | 89 RK_U32 fbc_hdr_stride; member
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| /rockchip-linux_mpp/mpp/codec/dec/h265/ |
| H A D | h265d_refs.c | 108 RK_U32 fbc_hdr_stride = MPP_ALIGN(s->h265dctx->width, 64); in alloc_frame() local
118 fbc_hdr_stride = MPP_ALIGN(s->h265dctx->width, 256) | 256; in alloc_frame()
120 mpp_frame_set_fbc_hdr_stride(frame->frame, fbc_hdr_stride); in alloc_frame()
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| /rockchip-linux_mpp/mpp/hal/rkdec/vp9d/ |
| H A D | hal_vp9d_vdpu34x.c | 631 RK_U32 fbc_hdr_stride = mpp_frame_get_fbc_hdr_stride(mframe); in hal_vp9d_vdpu34x_gen_regs() local
633 RK_U32 fbd_offset = MPP_ALIGN(fbc_hdr_stride * (h + 16) / 16, SZ_4K); in hal_vp9d_vdpu34x_gen_regs()
636 vp9_hw_regs->common.reg018.y_hor_virstride = fbc_hdr_stride >> 4; in hal_vp9d_vdpu34x_gen_regs()
637 vp9_hw_regs->common.reg019.uv_hor_virstride = fbc_hdr_stride >> 4; in hal_vp9d_vdpu34x_gen_regs()
686 RK_U32 fbc_hdr_stride = mpp_frame_get_fbc_hdr_stride(frame); in hal_vp9d_vdpu34x_gen_regs() local
688 RK_U32 fbd_offset = MPP_ALIGN(fbc_hdr_stride * (h + 16) / 16, SZ_4K); in hal_vp9d_vdpu34x_gen_regs()
690 y_hor_virstride = uv_hor_virstride = fbc_hdr_stride >> 4; in hal_vp9d_vdpu34x_gen_regs()
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| H A D | hal_vp9d_vdpu382.c | 641 RK_U32 fbc_hdr_stride = mpp_frame_get_fbc_hdr_stride(mframe); in hal_vp9d_vdpu382_gen_regs() local
643 RK_U32 fbd_offset = MPP_ALIGN(fbc_hdr_stride * (h + 16) / 16, SZ_4K); in hal_vp9d_vdpu382_gen_regs()
646 vp9_hw_regs->common.reg018.y_hor_virstride = fbc_hdr_stride >> 4; in hal_vp9d_vdpu382_gen_regs()
647 vp9_hw_regs->common.reg019.uv_hor_virstride = fbc_hdr_stride >> 4; in hal_vp9d_vdpu382_gen_regs()
696 RK_U32 fbc_hdr_stride = mpp_frame_get_fbc_hdr_stride(frame); in hal_vp9d_vdpu382_gen_regs() local
698 RK_U32 fbd_offset = MPP_ALIGN(fbc_hdr_stride * (h + 16) / 16, SZ_4K); in hal_vp9d_vdpu382_gen_regs()
700 y_hor_virstride = uv_hor_virstride = fbc_hdr_stride >> 4; in hal_vp9d_vdpu382_gen_regs()
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| H A D | hal_vp9d_vdpu383.c | 857 RK_U32 fbc_hdr_stride = mpp_frame_get_fbc_hdr_stride(mframe); in hal_vp9d_vdpu383_gen_regs() local
862 vp9_hw_regs->vp9d_paras.reg68_hor_virstride = fbc_hdr_stride / 64; in hal_vp9d_vdpu383_gen_regs()
866 vp9_hw_regs->vp9d_paras.reg80_error_ref_hor_virstride = fbc_hdr_stride / 64; in hal_vp9d_vdpu383_gen_regs()
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| /rockchip-linux_mpp/mpp/codec/dec/avs2/ |
| H A D | avs2d_dpb.c | 502 RK_U32 fbc_hdr_stride = MPP_ALIGN(vsh->horizontal_size, 64); in dpb_alloc_frame() local
507 fbc_hdr_stride = MPP_ALIGN(vsh->horizontal_size, 256) | 256; in dpb_alloc_frame()
509 mpp_frame_set_fbc_hdr_stride(mframe, fbc_hdr_stride); in dpb_alloc_frame()
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| /rockchip-linux_mpp/mpp/hal/rkdec/avs2d/ |
| H A D | hal_avs2d_rkv.c | 356 RK_U32 fbc_hdr_stride = mpp_frame_get_fbc_hdr_stride(mframe); in fill_registers() local
357 RK_U32 fbd_offset = MPP_ALIGN(fbc_hdr_stride * (ver_virstride + 16) / 16, SZ_4K); in fill_registers()
360 common->reg018.y_hor_virstride = fbc_hdr_stride / 16; in fill_registers()
361 common->reg019.uv_hor_virstride = fbc_hdr_stride / 16; in fill_registers()
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| H A D | hal_avs2d_vdpu382.c | 412 RK_U32 fbc_hdr_stride = mpp_frame_get_fbc_hdr_stride(mframe); in fill_registers() local
413 RK_U32 fbd_offset = MPP_ALIGN(fbc_hdr_stride * (ver_virstride + 16) / 16, SZ_4K); in fill_registers()
416 common->reg018.y_hor_virstride = fbc_hdr_stride / 16; in fill_registers()
417 common->reg019.uv_hor_virstride = fbc_hdr_stride / 16; in fill_registers()
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| H A D | hal_avs2d_vdpu383.c | 383 RK_U32 fbc_hdr_stride = mpp_frame_get_fbc_hdr_stride(mframe); in fill_registers() local
387 regs->avs2d_paras.reg68_hor_virstride = fbc_hdr_stride / 64; in fill_registers()
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| /rockchip-linux_mpp/mpp/hal/rkdec/h264d/ |
| H A D | hal_h264d_vdpu34x.c | 558 RK_U32 fbc_hdr_stride = mpp_frame_get_fbc_hdr_stride(mframe); in set_registers() local
559 RK_U32 fbd_offset = MPP_ALIGN(fbc_hdr_stride * (ver_virstride + 16) / 16, SZ_4K); in set_registers()
562 common->reg018.y_hor_virstride = fbc_hdr_stride / 16; in set_registers()
563 common->reg019.uv_hor_virstride = fbc_hdr_stride / 16; in set_registers()
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| H A D | hal_h264d_vdpu382.c | 567 RK_U32 fbc_hdr_stride = mpp_frame_get_fbc_hdr_stride(mframe); in set_registers() local
568 RK_U32 fbd_offset = MPP_ALIGN(fbc_hdr_stride * (ver_virstride + 16) / 16, SZ_4K); in set_registers()
571 common->reg018.y_hor_virstride = fbc_hdr_stride / 16; in set_registers()
572 common->reg019.uv_hor_virstride = fbc_hdr_stride / 16; in set_registers()
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| H A D | hal_h264d_vdpu384a.c | 376 RK_U32 fbc_hdr_stride = mpp_frame_get_fbc_hdr_stride(mframe); in set_registers() local
379 fbd_offset = fbc_hdr_stride * MPP_ALIGN(ver_virstride, 64) / 16; in set_registers()
385 regs->h264d_paras.reg68_dpb_hor_virstride = fbc_hdr_stride / 64; in set_registers()
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| H A D | hal_h264d_vdpu383.c | 440 RK_U32 fbc_hdr_stride = mpp_frame_get_fbc_hdr_stride(mframe); in set_registers() local
443 fbd_offset = fbc_hdr_stride * MPP_ALIGN(ver_virstride, 64) / 16; in set_registers()
446 regs->h264d_paras.reg68_hor_virstride = fbc_hdr_stride / 64; in set_registers()
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| /rockchip-linux_mpp/inc/ |
| H A D | mpp_frame.h | 400 void mpp_frame_set_fbc_hdr_stride(MppFrame frame, RK_U32 fbc_hdr_stride);
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| /rockchip-linux_mpp/mpp/base/ |
| H A D | mpp_frame.c | 342 MPP_FRAME_ACCESSORS(RK_U32, fbc_hdr_stride)
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| /rockchip-linux_mpp/mpp/hal/rkdec/h265d/ |
| H A D | hal_h265d_vdpu382.c | 747 RK_U32 fbc_hdr_stride = mpp_frame_get_fbc_hdr_stride(mframe); in hal_h265d_vdpu382_gen_regs() local
748 RK_U32 fbd_offset = MPP_ALIGN(fbc_hdr_stride * (ver_virstride + 64) / 16, SZ_4K); in hal_h265d_vdpu382_gen_regs()
751 hw_regs->common.reg018.y_hor_virstride = fbc_hdr_stride >> 4; in hal_h265d_vdpu382_gen_regs()
752 hw_regs->common.reg019.uv_hor_virstride = fbc_hdr_stride >> 4; in hal_h265d_vdpu382_gen_regs()
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| H A D | hal_h265d_vdpu34x.c | 958 RK_U32 fbc_hdr_stride = mpp_frame_get_fbc_hdr_stride(mframe); in hal_h265d_vdpu34x_gen_regs() local
959 RK_U32 fbd_offset = MPP_ALIGN(fbc_hdr_stride * (ver_virstride + 64) / 16, SZ_4K); in hal_h265d_vdpu34x_gen_regs()
962 hw_regs->common.reg018.y_hor_virstride = fbc_hdr_stride >> 4; in hal_h265d_vdpu34x_gen_regs()
963 hw_regs->common.reg019.uv_hor_virstride = fbc_hdr_stride >> 4; in hal_h265d_vdpu34x_gen_regs()
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| H A D | hal_h265d_vdpu384a.c | 903 RK_U32 fbc_hdr_stride = mpp_frame_get_fbc_hdr_stride(mframe); in hal_h265d_vdpu384a_gen_regs() local
910 hw_regs->h265d_paras.reg68_dpb_hor_virstride = fbc_hdr_stride / 64; in hal_h265d_vdpu384a_gen_regs()
911 fbd_offset = fbc_hdr_stride * MPP_ALIGN(ver_virstride, 64) / 16; in hal_h265d_vdpu384a_gen_regs()
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| H A D | hal_h265d_vdpu383.c | 991 RK_U32 fbc_hdr_stride = mpp_frame_get_fbc_hdr_stride(mframe); in hal_h265d_vdpu383_gen_regs() local
995 hw_regs->h265d_paras.reg68_hor_virstride = fbc_hdr_stride / 64; in hal_h265d_vdpu383_gen_regs()
996 fbd_offset = fbc_hdr_stride * MPP_ALIGN(ver_virstride, 64) / 16; in hal_h265d_vdpu383_gen_regs()
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| /rockchip-linux_mpp/mpp/codec/dec/av1/ |
| H A D | av1d_parser.c | 787 RK_U32 fbc_hdr_stride = MPP_ALIGN(ctx->width, 64); in get_current_frame() local
805 fbc_hdr_stride = MPP_ALIGN(ctx->width, 256) | 256; in get_current_frame()
807 mpp_frame_set_fbc_hdr_stride(frame->f, fbc_hdr_stride); in get_current_frame()
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| /rockchip-linux_mpp/mpp/codec/dec/vp9/ |
| H A D | vp9d_parser.c | 401 RK_U32 fbc_hdr_stride = mpp_align_64(ctx->width); in vp9_alloc_frame() local
407 fbc_hdr_stride = mpp_align_256_odd(ctx->width); in vp9_alloc_frame()
409 mpp_frame_set_fbc_hdr_stride(frame->f, fbc_hdr_stride); in vp9_alloc_frame()
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| /rockchip-linux_mpp/mpp/hal/rkdec/av1d/ |
| H A D | hal_av1d_vdpu383.c | 2341 RK_U32 fbc_hdr_stride = mpp_frame_get_fbc_hdr_stride(mframe); in vdpu383_av1d_gen_regs() local
2345 regs->av1d_paras.reg68_hor_virstride = fbc_hdr_stride / 64; in vdpu383_av1d_gen_regs()
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| /rockchip-linux_mpp/mpp/codec/dec/h264/ |
| H A D | h264d_init.c | 485 impl->fbc_hdr_stride = MPP_ALIGN(impl->width, 64); in dpb_mark_malloc()
487 impl->fbc_hdr_stride = MPP_ALIGN(impl->width, 256) | 256; in dpb_mark_malloc()
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| /rockchip-linux_mpp/ |
| H A D | CHANGELOG.md | 310 - [av1d]: Fix uninitialized fbc_hdr_stride issue
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