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Searched refs:dec_mode (Results 1 – 16 of 16) sorted by relevance

/rockchip-linux_mpp/mpp/hal/vpu/m2vd/
H A Dhal_m2vd_vdpu1.c140 p_regs->sw03.dec_mode = 8; in hal_m2vd_vdpu1_init_hwcfg()
167 p_regs->sw03.dec_mode = 5; in hal_m2vd_vdpu1_gen_regs()
173 p_regs->sw03.dec_mode = 6; in hal_m2vd_vdpu1_gen_regs()
H A Dhal_m2vd_vdpu1_reg.h93 RK_U32 dec_mode : 4; member
/rockchip-linux_mpp/mpp/hal/rkdec/h264d/
H A Dhal_h264d_rkv_reg.h75 RK_U32 dec_mode : 2; member
H A Dhal_h264d_rkv_reg.c436 p_regs->sw02.dec_mode = 1; //!< h264 in set_registers()
H A Dhal_h264d_vdpu34x.c670 common->reg009.dec_mode = 1; //!< h264 in init_common_regs()
H A Dhal_h264d_vdpu382.c685 common->reg009.dec_mode = 1; //!< h264 in init_common_regs()
/rockchip-linux_mpp/mpp/hal/rkdec/avsd/
H A Dhal_avsd_vdpu1_reg.h92 RK_U32 dec_mode : 4; member
H A Dhal_avsd_plus_reg.h90 RK_U32 dec_mode : 4; member
H A Dhal_avsd_vdpu1.c103 p_regs->sw03.dec_mode = 11; //!< DEC_MODE_AVS in set_regs_parameters()
H A Dhal_avsd_plus.c107 p_regs->sw03.dec_mode = 11; //!< DEC_MODE_AVS in set_regs_parameters()
/rockchip-linux_mpp/mpp/hal/rkdec/inc/
H A Dvdpu34x_com.h73 RK_U32 dec_mode : 10; member
H A Dvdpu382_com.h73 RK_U32 dec_mode : 10; member
/rockchip-linux_mpp/mpp/hal/rkdec/avs2d/
H A Dhal_avs2d_rkv.c239 common->reg009.dec_mode = 3; // AVS2 in init_common_regs()
H A Dhal_avs2d_vdpu382.c239 common->reg009.dec_mode = 3; // AVS2 in init_common_regs()
/rockchip-linux_mpp/mpp/hal/rkdec/vp9d/
H A Dhal_vp9d_vdpu34x.c611 vp9_hw_regs->common.reg009.dec_mode = 2; //set as vp9 dec in hal_vp9d_vdpu34x_gen_regs()
H A Dhal_vp9d_vdpu382.c621 vp9_hw_regs->common.reg009.dec_mode = 2; //set as vp9 dec in hal_vp9d_vdpu382_gen_regs()